CYRF69213 Programmable Radio on Chip Low Power PRoCTM LP Features * Single Device, Two Functions -- 8-bit, Flash based USB peripheral MCU function and 2.4 GHz radio transceiver function in a single device * Flash-based Microcontroller Function -- M8C based 8-bit CPU, optimized for Human Interface Devices (HID) applications -- 256 Bytes of SRAM -- 8 Kbytes of Flash memory with EEPROM emulation -- In-System reprogrammable through D+/D- pins. -- 16-bit free running timer -- Low power wake up timer -- 12-bit Programmable Interval Timer with interrupts -- Watchdog timer * Industry-Leading 2.4 GHz Radio Transceiver Function -- Operates in the unlicensed worldwide Industrial, Scientific and Medical (ISM) band (2.4 GHz-2.483 GHz) -- DSSS data rates of up to 250 Kbps -- GFSK data rate of 1 Mbps -- -97 dBm receive sensitivity -- Programmable output power of up to +4 dBm -- Auto Transaction Sequencer (ATS) -- Framing CRC and Auto ACK PRoCTM LP CYRF69213 Block Diagram * * * * * * * -- Received Signal Strength Indication (RSSI) -- Automatic Gain Control (AGC) Component Reduction -- Integrated 3.3V regulator -- Integrated pull up on D- -- GPIOs that require no external components -- Operates off a single crystal Flexible I/O -- High current drive on GPIO pins. Configurable 8-mA or 50-mA/pin current sink on designated pins -- Each GPIO pin supports high-impedance inputs, configurable pull up, open-drain output, CMOS/TTL inputs and CMOS output -- Maskable intrrupts on all I/O pins USB Specification Compliance -- Conforms to USB Specification Version 2.0 -- Conforms to USB HID Specification Version 1.1 -- Supports one Low Speed USB device address -- Supports one control endpoint and two data end points -- Integrated USB Transceiver Operating voltage from 4.0V to 5.5V DC Operating temperature from 0 to 70C Lead-free 40-lead QFN package Advanced development tools based on Cypress's PSoC(R) Tools VIO VCC3 VCC2 VReg VCC1 VBat3 VBat1 VBat2 470nF RST P1.2 / VReg VDD_MICRO MOSI 1-2 uF nSS 4.7uF SCK Vbus RFbias RFp RFn 4 Radio Function IRQ/GPIO P1.5/MOSI P1_6:7 2 MISO/GPIO P1.4/SCK P2_0:1 XOUT/GPIO P1.3/nSS 2 PACTL/GPIO 12MHz Cypress Semiconductor Corporation Document #: 001-07552 Rev. *B * 198 Champion Court * ..... GND GND Xtal GND RESV D+/D2 ....... VSS P0_2:4,7 Microcontroller Function 470nF San Jose, CA 95134-1709 * 408-943-2600 Revised February 20, 2007 [+] Feedback CYRF69213 Applications The CYRF69213 PRoC LP Low Speed is targeted for the following applications: * USB Bridge for Human Interface Devices (HID) -- Wireless mice -- Wireless keyboards -- Remote controls -- Gaming applications * USB Bridge for General Purpose Applications -- Consumer electronics -- Industrial applications -- White goods -- Home automation -- Personal health Functional Description PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. Communication between the microcontroller and the radio is via the SPI interface between both functions. Functional Overview The CYRF69213 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69213 is designed to implement low-cost wireless systems operating in the worldwide 2.4-GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz-2.4835 GHz). 2.4 GHz Radio Function The radio meets the following world-wide regulatory requirements: * Europe -- ETSI EN 301 489-1 V1.4.1 -- ETSI EN 300 328-1 V1.3.1 * North America -- FCC CFR 47 Part 15 * Japan -- ARIB STD-T66 Document #: 001-07552 Rev. *B Data Transmission Modes The radio supports four different data transmission modes: * In GFSK mode, data is transmitted at 1 Mbps without any DSSS * In 8DR mode, 1 byte is encoded in each PN code symbol transmitted * In DDR mode, 2 bits are encoded in each PN code symbol transmitted * In SDR mode, a single bit is encoded in each PN code symbol transmitted Both 64-chip and 32-chip data PN codes are supported. The four data transmission modes apply to the data after the Start of Packet (SOP). In particular, the packet length, data and CRC are all sent in the same mode. USB Microcontroller Function The microcontroller function is based on the powerful CYRF69213 microcontroller. It is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The microcontroller has up to 14 GPIO pins to support USB, PS/2 and other applications. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. The microcontroller features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). The PRoC LP has up to 8 Kbytes of Flash for user's firmware code and up to 256 bytes of RAM for stack space and user variables. The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1-ms interrupt and a 16-bit free running timer with capture registers. Page 2 of 85 [+] Feedback CYRF69213 Pinout Pin Name 1 P0.4 2 Xtal_in Function Individually configured GPIO 12 MHz Crystal. External Clock in 3, 7, 16 VCC Connected to pin 24 via 0.047-F Capacitor. 4 P0.3 Individually configured GPIO 5 P0.1 Individually configured GPIO 6, 9, 39 Vbat Connected to pin 24 via 0.047-Fshunt capacitor 8 P2.1 GPIO. Port 2 Bit 1 10 RF Bias RF pin voltage reference 11 RFp Differential RF input to/from antenna 12 GND Ground Differential RF to/from antenna 13 RFn 14, 17, 18, 20, 36 NC 15 P2.0 19 RESV 21 D+ 22 D- 23 VDD_micro GPIO. Port 2 Bit 0 Reserved. Must connect to GND Low-speed USB IO Low-speed USB IO 4.0-5.5 for 12 MHz CPU/4.75-5.5 for 24 MHz CPU 24 P1.2 / VREG Must be configured as 3.3V output. It must have a 1-2 F output capacitor 25 P1.3 / nSS Slave select SPI Pin 26 P1.4 / SCK Serial Clock Pin from MCU function to radio function 27 IRQ 28 P1.5 / MOSI 29 MISO Master In Slave Out, from radio function.Can be configured as GPIO 30 XOUT Bufferd CLK, PACTL_n or GPIO 31 PACTL Control for external PA or GPIO 32 P1.6 GPIO. Port 1 Bit 6 33 VIO I/O interface voltage. Connected to pin 24 via 0.047 F 34 Reset Radio Reset. Connected to VDD via 0.47 F Capacitor or to microcontroller GPIO pin. Must have a RESET = HIGH event the very first time power is applied to the radio otherwise the state of the radio function control registers is unknown. 35 P1.7 GPIO. Port 1 Bit 7 36 VDD_1.8 37 L/D 38 P0.7 GPIO. Port 0 Bit 7 40 Vreg Connected to pin 24 41 E-pad Connected to GND Document #: 001-07552 Rev. *B Interrupt output, configure high/low or GPIO Master Out Slave In. Regulated logic bypass. Connected via 0.47 F to GND Connected to GND Page 3 of 85 [+] Feedback CYRF69213 Pinout Diagram Figure 1. Pinout 40-Lead QFN 7 x 7 mm LF48A PACTL / GPIO 31 33 P1.6 32 VIO RST 34 36 P1.7 35 L/D 37 VDD_1.8 P0.7 38 VBAT 39 VREG 40 Corner tabs P0.4 1 30 XOUT / GPIO XTAL 2 29 MISO / GPIO VCC 3 P0.3 4 P0.1 5 26 P1.4 / SCK VBAT 6 25 P1.3 / SS CYRF69213 WirelessUSB LP 28 P1.5 / MOSI 27 IRQ / GPIO VCC 7 24 P1.2 / VREG P2.1 8 23 VDD_Micro VBAT 9 22 D* E-PAD Bottom Side 21 D+ RFBIAS 10 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP PRoC LP Functional Overview and change to lower data rates at longer distances and/or in high interference environments. The SoC is designed to implement wireless device links operating in the worldwide 2.4-GHz ISM frequency band. It is intended for systems compliant with world-wide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada) and TELEC ARIB_T66_March, 2003 (Japan). The MCU function is an 8-bit Flash-programmable microcontroller with integrated low-speed USB interface. The instruction set has been optimized specifically for USB operations, although it can be used for a variety of other embedded applications. The SoC contains a 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1-MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband performs Start of Frame (SOF), End of Frame (EOF) detection and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low-moderate interference environment, Document #: 001-07552 Rev. *B The MCU function has up to eight Kbytes of Flash for user's code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free-Running Timer, and 12-bit Programmable Interrupt Timer. The MCU function supports in-system programming by using the D+ and D- pins as the serial programming mode interface. The programming protocol is not USB. Backward Compatibility The CYRF69213 IC is fully interoperable with the main modes of other Cypress radios CYWUSB6934 and CYRF6936. The 62.5-kbps mode is supported by selecting 32-chip DATA_CODE_ADR codes, DDR mode, and disabling the SOP, length, and CRC16 fields. Similarly, the 15.675-kHz mode is supported by selecting 64-chip DATA_CODE_ADR codes and SDR mode. In this way, a suitably configured CYRF69213 IC device may transmit data to and/or receive data from a first generation device. Page 4 of 85 [+] Feedback CYRF69213 Functional Block Overview sent in the same mode. In general, lower data rates reduces packet error rate in any given environment. All the blocks that make up the PRoC LP are presented here. By combining the DATA_CODE_ADR code lengths and data transmission modes described above, the CYRF69213 IC supports the following data rates: * 1000-kbps (GFSK) * 250-kbps (32-chip 8DR) * 125-kbps (64-chip 8DR) * 62.5-kbps (32-chip DDR) * 31.25-kbps (64-chip DDR) * 15.625-kbps (64-chip SDR) 2.4-GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in 7 steps. The supply current of the device is reduced as the RF output power is reduced. Table 1. Internal PA Output Power Step Table Lower data rates typically provide longer range and/or a more robust link. PA Setting Typical Output Power (dBm) 7 +4 Link Layer Modes 6 0 5 -5 The CYRF69213 IC device supports the following data packet framing features: 4 -10 3 -15 2 -20 1 -25 0 -30 Frequency Synthesizer Before transmission or reception may commence, it is necessary for the frequency synthesizer to settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The `fast channels' (<100-s settling time) are every third frequency, starting at 2400 MHz up to and including 2472 MHz (for example, 0,3,6,9.......69 & 72). Baseband and Framer The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, as well as EOP detection and length field. Data Rates and Data Transmission Modes The SoC supports four different data transmission modes: * In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. * In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. * In DDR mode, 2-bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. (As in the CYWUSB6934 DDR mode). * In SDR mode, 1 bit is encoded in each DATA_CODE_ADR derived code symbol transmitted. (As in the CYWUSB6934 standard modes.) Both 64-chip and 32-chip DATA_CODE_ADR codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all Document #: 001-07552 Rev. *B SOP - Packets begin with a 2-symbol Start of Packet (SOP) marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode; if framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the `body' of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. EOP - There are two options for detecting the end of a packet. If SOP is enabled, then a packet length field may be enabled. GFSK and 8DR must enable the length field. This is the first 8 bits after the SOP symbol, and is transmitted at the payload data rate. If the length field is enabled, an End of Packet (EOP) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16 (if enabled--see below). The alternative to using the length field is to infer an EOP condition from a configurable number of successive non-correlations; this option is not available in GFSK mode and is only recommended when using SDR mode. CRC16 - The device may be configured to append a 16-bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver will verify the calculated CRC16 for the payload data against the received value in the CRC16 field. The starting value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 will be checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: * Any one bit in error * Any two bits in error (no matter how far apart, which column, and so on) * Any odd number of bits in error (no matter where they are) * An error burst as wide as the checksum itself Figure 2 shows an example packet with SOP, CRC16 and lengths fields enabled. Page 5 of 85 [+] Feedback CYRF69213 Figure 2. Example Default Packet Format Preamble n x 16us 2nd Framing Symbol* P SOP 1 SOP 2 1st Framing Symbol* Length Payload Data Packet length 1 Byte Period Packet Buffers Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet. Configuration registers are provided to allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and others. Packet Buffers CRC 16 *Note:32 or 64us the fully received packet in response to an interrupt request indicating reception of a packet. Interrupts The radio function provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active high or active low, and be either a CMOS or open drain output. The IRQ pin can be multiplexed on the SPI if routed to an external pin. The transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst SPI transaction, and then transmitted with no further MCU intervention. Similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. The radio function features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. The CYRF69213 IC supports packet length of up to 40 bytes; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU function must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. If more than one radio interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without making use of the IRQ pin by polling the status register(s) to wait for an event, rather than using the IRQ pin. All data transmission and reception uses the 16-byte packet buffers--one for transmission and one for reception. Auto Transaction Sequencer (ATS) The CYRF69213 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet--and then automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a timeout period expires. Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, then automatically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next packet. The contents of the packet buffers are not affected by the transmission or reception of ACK packets. The microcontroller function supports 23 maskable interrupts in the vectored interrupt controller. Interrupt sources include a USB bus reset, LVR/POR, a programmable interval timer, a 1.024-ms output from the Free Running Timer, three USB endpoints, two capture timers, five GPIO Ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, an internal wake-up timer, and a bus active interrupt. The wake-up timer causes periodic interrupts when enabled. The USB endpoints interrupt after a USB transaction complete is on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. Clocks In each case, the entire packet transaction takes place without any need for MCU firmware action; to transmit data the MCU simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply needs to retrieve The radio function has a 12-MHz crystal (30-ppm or better) directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. Below are the requirements for the crystal to be directly connected to XTAL pin and GND: Document #: 001-07552 Rev. *B Page 6 of 85 [+] Feedback CYRF69213 Figure 3. Power Management From Internal Regulator 0.047F 0.047F 0.047F The MCU function features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). The clock generator provides the 12-MHz and 24-MHz clocks that remain internal to the microcontroller. 0.047F Power-On Reset/Low-Voltage Detect The power-on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates reset or may be configured to generate interrupt. There is a low-voltage detect circuit that detects when VCC drops below a programmable trip voltage. It may be configurable to generate an LVD interrupt to inform the processor about the low-voltage event. POR and LVD share the same interrupt. There is not a separate interrupt for each. The Watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. Power Management The device draws its power supply from the USB Vbus line. The Vbus supplies power to the MCU function, which has an internal 3.3 V regulator. This 3.3 V is supplied to the radio function via P1.2/VREG after proper filtering as shown in Figure 3. 0.047F VCC3 VCC2 VCC1 VReg VIO VBat2 0.047F GPIO Interface P1.2 / VReg PRoC LP VBUS VDD_MICRO 0.1F L/D The MCU function features up to 20 general-purpose I/O (GPIO) pins to support USB, PS/2, and other applications. The I/O pins are grouped into five ports (Port 0 to 4). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2, 3, and 4 may only be configured as a group. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50-mA sink current. GPIO Port 1 features four pins that interface at a voltage level of 3.3 volts. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.2-P0.4). 0.047F 0.047F VBat3 Nominal Frequency: 12 MHz Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: 30 ppm Series Resistance: <60 ohms Load Capacitance: 10 pF Drive Level: 10 W-100 W VBat1 * * * * * * * Timers The free-running 16-bit timer provides two interrupt sources: the programmable interval timer with 1-s resolution and the 1.024-ms outputs. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. USB Interface The MCU function includes an integrated USB serial interface engine (SIE) that allows the chip to easily interface to a USB host. The hardware supports one USB device address with three endpoints. Low Noise Amplifier (LNA) and Received Signal Strength Indication (RSSI) The gain of the receiver may be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. When the LNA bit is cleared, the receiver gain is reduced by approximately 20 dB, allowing accurate reception of very strong received signals (for example when operating a receiver very close to the transmitter). An additional 20 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit; this allows data reception to be limited to devices at very short ranges. Disabling AGC and enabling LNA is recommended unless receiving from a device using external PA. The RSSI register returns the relative signal strength of the on-channel signal power. When receiving, the device may be configured to automatically measure and store the relative strength of the signal being received as a 5-bit value. When enabled, an RSSI reading is taken and may be read through the SPI interface. Document #: 001-07552 Rev. *B Page 7 of 85 [+] Feedback CYRF69213 Figure 5. 4-WIRE SPI Mode nSS The SPI interface between the MCU function and the radio function is a 3-wire SPI Interface. The three pins are MOSI (Master Out Slave In), SCK (Serial Clock), SS (Slave Select). There is an alternate 4-wire MISO Interface that requires the connection of two external pins. The SPI interface is controlled by configuring the SPI Configure Register (SICR Address: 0x3D). MOSI SPI Interface The device receives SCK from the MCU function on the SCK pin. Data from the MCU function is shifted in on the MOSI pin. Data to the MCU function is shifted out on the MISO pin. The active low SS pin must be asserted for the two functions to communicate. The IRQ function may be optionally multiplexed with the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware should ensure that the MOSI function on MCU function is in a high-impedance state whenever SS is high. SCK An RSSI reading is taken automatically when the start of a packet is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read when no signal is being received. A new reading can occur as fast as once every 12 s. Radio Function MCU Function 3-Wire SPI Interface The radio function receives a clock from the MCU function on the SCK pin. The MOSI pin is multiplexed with the MISO pin. Bidirectional data transfer takes place between the MCU function and the radio function through this multiplexed MOSI pin. When using this mode the user firmware should ensure that the MOSI pin on the MCU function is in a high impedance state, except when the MCU is actively transmitting data. Firmware must also control the direction of data flow and switch directions between MCU function and radio function by setting the SWAP bit [Bit 7] of the SPI Configure Register. The SS pin is asserted prior to initiating a data transfer between the MCU function and the radio function. The IRQ function may be optionally multiplexed with the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware should ensure that the MOSI function on MCU function is in a high-impedance state whenever SS is high. Figure 4. 3-Wire SPI Mode P1.6/MISO P1.5/MOSI MOSI P1.4/SCK SCK P1.3/nSS nSS MISO This connection is external to the PRoC LP Chip SPI Communication and Transactions The SPI transactions can be single byte or multi-byte. The MCU function initiates a data transfer through a Command/Address byte. The following bytes are data bytes. The SPI transaction format is shown in Figure 6. MOSI SCK nSS The DIR bit specifies the direction of data transfer. 0 = Master reads from slave. 1 = Master writes to slave. The INC bit helps to read or write consecutive bytes from contiguous memory locations in a single burst mode operation. Radio Function MCU Function P1.5/MOSI MOSI/MISO multiplexed on one MOSI pin MOSI P1.4/SCK SCK P1.3/nSS nSS 4-Wire SPI Interface The 4-wire SPI communications interface consists of MOSI, MISO, SCK, and SS. Document #: 001-07552 Rev. *B If Slave Select is asserted and INC = 1, then the master MCU function reads a byte from the radio, the address is incremented by a byte location, and then the byte at that location is read, and so on. If Slave Select is asserted and INC = 0, then the MCU function reads/writes the bytes in the same register in burst mode, but if it is a register file then it reads/writes the bytes in that register file. The SPI interface between the radio function and the MCU is not dependent on the internal 12-MHz oscillator of the radio. Therefore, radio function registers can be read from or written into while the radio is in sleep mode. SPI IO Voltage References The SPI interfaces between MCU function and the radio and the IRQ and RST have a separate voltage reference VIO, enabling the radio function to directly interface with the MCU Page 8 of 85 [+] Feedback CYRF69213 SPI Connects to External Devices function, which operates at higher supply voltage. The internal SPIO pins between the MCU function and radio function should be connected with a regulated voltage of 3.3V (by setting [bit4] of Registers P13CR, P14CR, P15CR, and P16CR of the MCU function) and the internal 3.3V regulator of the MCU function should be turned on. The three SPI wires, MOSI, SCK, and SS are also drawn out of the package as external pins to allow the user to interface their own external devices (such as optical sensors and others) through SPI. The radio function also has its own SPI wires MISO and IRQ, which can be used to send data back to the MCU function or send an interrupt request to the MCU function. They can also be configured as GPIO pins. Figure 6. SPI Transaction Format Byte 1 Bit# Bit Name Byte 1+N 7 6 [5:0] [7:0] DIR INC Address Data CPU Architecture The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. This family of microcontrollers is based on a high-performance, 8-bit, Harvard-architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions. Table 2. CPU Registers and Register Names Register Register Name Flags CPU_F Program Counter CPU_PC Accumulator CPU_A Stack Pointer CPU_SP Index CPU_X The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (for example, AND, OR, XOR). See Table 19. The 16-bit Program Counter Register (CPU_PC) allows for direct addressing of the full eight Kbytes of program memory space. CPU Registers Flags Register The Flags Register can only be set or reset with logical instruction. Table 3. CPU Flags Register (CPU_F) [R/W] Bit # 7 Field 6 5 Reserved 4 3 2 1 0 XIO Super Carry Zero Global IE Read/Write - - - R/W R RW RW RW Default 0 0 0 0 0 0 1 0 Document #: 001-07552 Rev. *B Page 9 of 85 [+] Feedback CYRF69213 Table 3. CPU Flags Register (CPU_F) [R/W] Bits 7:5 Reserved Bit 4 XIO Set by the user to select between the register banks 0 = Bank 0 1 = Bank 1 Bit 3 Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.) 0 = User Code 1 = Supervisor Code Bit 2 Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation 0 = No Carry 1 = Carry Bit 1 Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = Not Equal to Zero 1 = Equal to Zero Bit 0 Global IE Determines whether all interrupts are enabled or disabled 0 = Disabled 1 = Enabled Note CPU_F register is only readable with explicit register address 0xF7. The OR F, expr and AND F, expr instructions must be used to set and clear the CPU_F bits Accumulator Register Table 4. CPU Accumulator Register (CPU_A) Bit # 7 6 5 Field 4 3 2 1 0 CPU Accumulator [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bits 7:0 CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode Index Register Table 5. CPU X Register (CPU_X) Bit # 7 6 5 4 3 2 1 0 Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 2 1 0 Field X [7:0] Bits 7:0 X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode Stack Pointer Register Table 6. CPU Stack Pointer Register (CPU_SP) Bit # 7 6 5 Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Field 4 3 Stack Pointer [7:0] Document #: 001-07552 Rev. *B Page 10 of 85 [+] Feedback CYRF69213 Table 6. CPU Stack Pointer Register (CPU_SP) Bits 7:0 Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack CPU Program Counter High Register Table 7. CPU Program Counter High Register (CPU_PCH) Bit # 7 6 5 Read/Write - - - - Default 0 0 0 Field 4 3 2 1 0 - - - - 0 0 0 0 0 4 3 2 1 0 Program Counter [15:8] Bits 7:0 Program Counter [15:8] 8-bit data value holds the higher byte of the program counter CPU Program Counter Low Register Table 8. CPU Program Counter Low Register (CPU_PCL) Bit # 7 6 5 Field Program Counter [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bits 7:0 Program Counter [7:0] 8-bit data value holds the lower byte of the program counter Addressing Modes Source Direct Examples of the different addressing modes are discussed in this section and example code is given. Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources. Instructions using this addressing mode are two bytes in length. Instruction Opcode Instruction Table 9. Source Immediate Opcode The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 10.Source Direct Operand 1 Immediate Value Source Address Examples ADD A, [7] ;In this case, the value in ;the RAM memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the Accumulator. MOV X, REG[8] ;In this case, the value in ;the register space at address ;8 is moved to the X register. Examples ADD A, 7 ;In this case, the immediate value ;of 7 is added with the Accumulator, ;and the result is placed in the ;Accumulator. MOV X, 8 ;In this case, the immediate value ;of 8 is moved to the X register. AND F, 9 ;In this case, the immediate value ;of 9 is logically ANDed with the F ;register and the result is placed ;in the F register. Document #: 001-07552 Rev. *B Operand 1 Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is Page 11 of 85 [+] Feedback CYRF69213 specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 11.Source Indexed the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 13.Destination Indexed Opcode Operand 1 Instruction Opcode Destination Index Operand 1 Instruction Source Index Example ADD [X+7], A Examples ADD A, [X+7] ;In this case, the value in ;the memory location at ;address X + 7 is added with ;the Accumulator, and the ;result is placed in the ;Accumulator. MOV X, REG[X+8] ;In this case, the value in ;the register space at ;address X + 8 is moved to ;the X register. Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 14.Destination Direct Immediate Opcode Instruction Operand 1 Destination Address ADD [7], 5 ;In this case, value in the mem;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. MOV REG[8], 6 ;In this case, the immediate ;value of 6 is moved into the ;register space location at ;address 8. Operand 1 Instruction Destination Address Examples ADD MOV [7], REG[8], A A ;In this case, the value in ;the memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the memory ;location at address 7. The ;Accumulator is unchanged. ;In this case, the Accumula;tor is moved to the regis;ter space location at ;address 8. The Accumulator ;is unchanged. Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for Document #: 001-07552 Rev. *B Operand 2 Immediate Value Examples Table 12.Destination Direct Opcode ;In this case, the value in the ;memory location at address X+7 ;is added with the Accumulator, ;and the result is placed in ;the memory location at address ;x+7. The Accumulator is ;unchanged. Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 15.Destination Indexed Immediate Opcode Instruction Operand 1 Destination Index Operand 2 Immediate Value Page 12 of 85 [+] Feedback CYRF69213 Examples ADD MOV [X+7], REG[X+8], 5 6 ;In this case, the value in ;the memory location at ;address X+7 is added with ;the immediate value of 5, ;and the result is placed ;in the memory location at ;address X+7. ;In this case, the immedi;ate value of 6 is moved ;into the location in the ;register space at ;address X+8. bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 17.Source Indirect Post Increment Opcode Operand 1 Instruction Source Address Address Example MVI A, [8] Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 16.Destination Direct Source Direct Opcode Instruction Operand 1 Destination Address Operand 2 Source Address Example MOV [7], ;In this case, the value in the ;memory location at address 8 is ;an indirect address. The memory ;location pointed to by the indi;rect address is moved into the ;Accumulator. The indirect ;address is then incremented. Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 18.Destination Indirect Post Increment [8] ;In this case, the value in the ;memory location at address 8 is ;moved to the memory location at ;address 7. Opcode Operand 1 Instruction Destination Address Address Example Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two Document #: 001-07552 Rev. *B MVI [8], A ;In this case, the value in ;the memory location at ;address 8 is an indirect ;address. The Accumulator is ;moved into the memory loca;tion pointed to by the indi;rect address. The indirect ;address is then incremented. Page 13 of 85 [+] Feedback CYRF69213 Instruction Set Summary The instruction set is summarized in Table 19 numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site). Bytes Flags Cycles Instruction Format Opcode Hex Bytes Flags Cycles Instruction Format Opcode Hex Bytes Cycles Opcode Hex Table 19.Instruction Set Summary Sorted Numerically by Opcode Order[1, 2] Instruction Format Flags 00 15 1 SSC 2D 8 2 OR [X+expr], A Z 5A 5 2 MOV [expr], X 01 4 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z 5B 4 1 MOV A, X 02 6 2 ADD A, [expr] C, Z 2F 10 3 OR [X+expr], expr Z 5C 4 1 MOV X, A 03 7 2 ADD A, [X+expr] C, Z 30 9 1 HALT 5D 6 2 MOV A, reg[expr] Z 04 7 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z 5E 7 2 MOV A, reg[X+expr] Z 05 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z 5F 10 3 MOV [expr], [expr] 06 9 Z 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z 60 5 2 MOV reg[expr], A 07 10 3 ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z 61 6 2 MOV reg[X+expr], A 08 4 1 PUSH A 35 8 2 XOR [X+expr], A Z 62 8 3 MOV reg[expr], expr 09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z 63 9 3 MOV reg[X+expr], expr 0A 6 2 ADC A, [expr] C, Z 37 10 3 XOR [X+expr], expr Z 64 4 1 ASL A C, Z 0B 7 2 ADC A, [X+expr] C, Z 38 5 2 ADD SP, expr 65 7 2 ASL [expr] C, Z 0C 7 2 ADC [expr], A C, Z 39 5 2 CMP A, expr 66 8 2 ASL [X+expr] C, Z 0D 8 2 ADC [X+expr], A C, Z 3A 7 2 CMP A, [expr] 67 4 1 ASR A C, Z 0E 9 3 ADC [expr], expr C, Z 3B 8 2 CMP A, [X+expr] 68 7 2 ASR [expr] C, Z 0F 10 3 ADC [X+expr], expr C, Z 3C 8 3 CMP [expr], expr 69 8 2 ASR [X+expr] C, Z 10 4 1 PUSH X 3D 9 3 CMP [X+expr], expr 6A 4 1 RLC A C, Z 11 4 2 SUB A, expr C, Z 3E 10 2 MVI A, [ [expr]++ ] 6B 7 2 RLC [expr] C, Z 12 6 2 SUB A, [expr] C, Z 3F 10 2 MVI [ [expr]++ ], A 6C 8 2 RLC [X+expr] C, Z 13 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z 14 7 2 SUB [expr], A C, Z 41 9 3 AND reg[expr], expr Z 6E 7 2 RRC [expr] C, Z 15 8 2 SUB [X+expr], A C, Z 42 10 3 AND reg[X+expr], expr Z 6F 8 2 RRC [X+expr] C, Z 16 9 3 SUB [expr], expr C, Z 43 3 OR reg[expr], expr Z 70 4 2 AND F, expr C, Z 17 10 3 SUB [X+expr], expr C, Z 44 10 3 OR reg[X+expr], expr Z 71 4 2 OR F, expr C, Z 18 5 1 POP A 45 3 XOR reg[expr], expr Z 72 4 2 XOR F, expr C, Z 19 4 2 SBB A, expr C, Z 46 10 3 XOR reg[X+expr], expr Z 73 4 1 CPL A Z 1A 6 2 SBB A, [expr] C, Z 47 8 3 TST [expr], expr Z 74 4 1 INC A C, Z Z 9 9 if (A=B) Z=1 if (A