CC2430_CC2431 ERRATA NOTES CC2430_CC2431 Table Of Contents 1 2 COMMAND STROBES CAN CORRUPT RX FIFO CONTENTS ...................................................................2 DOCUMENT HISTORY ...........................................................................................................................4 SWRZ021 Page 1 of 4 CC2430_CC2431 1 Command Strobes Can Corrupt RX FIFO Contents The following applies only when (MDMCTRL0H.ADDR_DECODE = 1). 1.1 address decoding is enabled Bug Description When a frame is rejected by address decoding, CC2430 will disable SFD search until the frame has been completely received. This prevents detection of a false SFD within the remainder of the frame. No part of the rejected frame should end up in the RX FIFO, but there is a special case where exactly one byte from the rejected frame gets written to the FIFO. This bug is triggered as follows: 1. Address decoding has failed, and CC2430 receives the remainder of the frame (SFD = 0). 2. An SRXON, STXON or SRFOFF strobe is executed in the same clock cycle as another byte of the rejected frame is received. 3. The last received byte of the rejected frame is written to the RX FIFO (byte "X" in the figure). The following status values can be observed when the bug is triggered (not considering special conditions such as RX overflow): * FIFO = 1 * FIFOP = 1 if byte "X" = 0x00 or 0x80 Both immediate strobes and strobes executed as CSP instructions are affected. 1.2 Suggested Workaround The proposed workaround is simple to implement and has few negative side-effects. SRXON and SRFOFF The workaround consists of flushing the RX FIFO after the strobe has been executed. The following procedure reduces the risk of false bug detection: SWRZ021 Page 2 of 4 CC2430_CC2431 // Record the number of bytes in the RX FIFO before the strobe rxfifocntBefore = RXFIFOCNT; RFST = ISRFOFF; // or SRXON // There is a short delay from the strobe until RXFIFOCNT has been updated. ... Wait for 0.75 us or more ... // If RXFIFOCNT changed during the last operation, it is very // likely that the bug has occurred if (RXFIFOCNT != rxfifocntBefore) { // Flush twice, as described in the data sheet SFLUSHRX(); SFLUSHRX(); // Software clean-up ... Reset software for frame reception, and abort DMA if necessary ... } STXON A CCA check will always fail during the critical period, from a frame is rejected until it is completely removed. The bug will never occur when CCA is checked immediately (less than the time it takes to receive one byte) before STXON. For transmission without CCA checking, the receiver must be turned off before STXON is strobed from software, or before the CSP program (containing STXON) is started. Use the procedure described above when strobing SRFOFF to disable the receiver. Note: * * 1.3 SRXON and SRFOFF cannot be used safely in a CSP program to reduce power consumption during CSMA-CA unless all data received during this period is discarded manually by software. However, if SRXON and SRFOFF are used during CSMA-CA, it is probably not expected to receive that much data anyway. When flushing the RX FIFO, received frames still to be read out will be lost. There is also a chance that the lost frames may already have been acknowledged. The effect is that the transmitter gets a false acknowledgment in return, but this is likely to happen sooner or later anyway (the only thing that separates one acknowledgment frame from another is the 8-bit sequence number). Batches Affected This bug affects all batches and revisions of the chip. SWRZ021 Page 3 of 4 CC2430_CC2431 2 Document History Revision Date Description/Changes SWRZ021 2007-07-25 Initial Release TEXAS INSTRUMENTS NORWAY Tel. +47-22958544 Fax +47-22958546 www.ti.com SWRZ021 Page 4 of 4 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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