AD9949KCP - Analog Devices - Datasheet.Directory

12-Bit CCD Signal Processor with

Precision Timing

Core

AD9949

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

New AD9949A supports CCD line length > 4096 pixels

Correlated double sampler (CDS)

0 dB to 18 dB pixel gain amplifier (PxGA®)

6 dB to 42 dB 10-bit variable gain amplifier (VGA)

12-bit, 36 MSPS analog-to-digital converter (ADC)

Black level clamp with variable level control

Complete on-chip timing driver

Precision Timing™ core with < 600 ps resolution

On-chip 3 V horizontal and RG drivers

40-lead LFCSP package

APPLICATIONS

Digital still cameras

High speed digital imaging applications

GENERAL DESCRIPTION

The AD9949 is a highly integrated CCD signal processor for

digital still camera applications. Specified at pixel rates of up to

36 MHz, the AD9949 consists of a complete analog front end

with A/D conversion, combined with a programmable timing

driver. The Precision Timing core allows adjustment of high

speed clocks with < 600 ps resolution.

The analog front end includes black level clamping, CDS,

PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver

provides the high speed CCD clock drivers for RG and H1 to

H4. Operation is programmed using a 3-wire serial interface.

Packaged in a space-saving, 40-lead LFCSP package, the

AD9949 is specified over an operating temperature range of

−20°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

CLAMP

DOUT

CCDIN

REFT REFB

INTERNAL

REGISTERS

6dB TO 42dB

SYNC

GENERATOR

SDATASCK

HBLK

VGA

AD9949

PRECISION

TIMING

CORE

12-BIT

ADC

REF

INTERNAL

CLOCKS

PxGA

CDS

HORIZONTAL

DRIVERS

H1 TO H4

HD VD

CLI

CLP/PBLK

0dB TO 18dB

03751-001

Figure 1.

AD9949

Rev. B | Page 2 of 36

TABLE OF CONTENTS

Specifications..................................................................................... 3

General Specifications ................................................................. 3

Digital Specifications ................................................................... 3

Analog Specifications................................................................... 4

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ...................................................................................... 8

Equivalent Input/Output Circuits .................................................. 9

Typical Performance Characteristics ........................................... 10

System Overview ............................................................................ 11

H-Counter Behavior .................................................................. 11

Serial Interface Timing .................................................................. 12

Complete Register Listing ............................................................. 13

Precision Timing High Speed Timing Generation...................... 18

Timing Resolution...................................................................... 18

High Speed Clock Programmability........................................ 18

H-Driver and RG Outputs ........................................................ 19

Digital Data Outputs.................................................................. 19

Horizontal Clamping and Blanking............................................. 21

Individual CLPOB and PBLK Sequences................................ 21

Individual HBLK Sequences..................................................... 21

Generating Special HBLK Patterns.............................................. 23

Horizontal Sequence Control................................................... 23

External HBLK Signal................................................................ 23

H-Counter Synchronization ..................................................... 24

Power-Up Procedure...................................................................... 25

Recommended Power-Up Sequence ....................................... 25

Analog Front End Description and Operation .......................... 26

DC Restore .................................................................................. 26

Correlated Double Sampler ...................................................... 26

PxGA............................................................................................ 26

Variable Gain Amplifier ............................................................ 29

ADC ............................................................................................. 29

Optical Black Clamp .................................................................. 29

Digital Data Outputs.................................................................. 29

Applications Information .............................................................. 30

Circuit Configuration................................................................ 30

Grounding and Decoupling Recommendations.................... 30

Driving the CLI Input................................................................ 31

Horizontal Timing Sequence Example.................................... 31

Outline Dimensions....................................................................... 34

Ordering Guide .......................................................................... 34

REVISION HISTORY

11/04—Data Sheet Changed from Rev. A to Rev. B

Changes to Ordering Guide .......................................................... 35

9/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Analog Specifications .................................................. 4

Changes to Terminology Section.................................................... 9

Added H-Counter Behavior Section............................................ 12

Changes to Table 7.......................................................................... 14

Changes to Table 12 ....................................................................... 17

Changes to Table 15 ....................................................................... 17

Changes to H-Counter Sync Section ........................................... 24

Changes to Recommended Power-Up Sequence Section......... 25

Changes to Ordering Guide .......................................................... 35

5/03—Revision 0: Initial Version

AD9949

Rev. B | Page 3 of 36

SPECIFICATIONS

GENERAL SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating −20 +85 °C

Storage −65 +150 °C

MAXIMUM CLOCK RATE 36 MHz

POWER SUPPLY VOLTAGE

AVDD, TCVDD (AFE, Timing Core) 2.7 3.0 3.6 V

HVDD (H1 to H4 Drivers) 2.7 3.0 3.6 V

RGVDD (RG Driver) 2.7 3.0 3.6 V

DRVDD (D0 to D11 Drivers) 2.7 3.0 3.6 V

DVDD (All Other Digital) 2.7 3.0 3.6 V

POWER DISSIPATION

36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading1 320 mW

Total Shutdown Mode 1 mW

1 The total power dissipated by the HVDD supply may be approximated using the equation

Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x (Number of H – Outputs Used)

Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation.

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted.

Table 2.

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage VIH 2.1 V

Low Level Input Voltage VIL 0.6 V

High Level Input Current IIH 10 µA

Low Level Input Current IIL 10 µA

Input Capacitance CIN 10 pF

LOGIC OUTPUTS

High Level Output Voltage, IOH = 2 mA VOH 2.2 V

Low Level Output Voltage, IOL = 2 mA VOL 0.5 V

CLI INPUT

High Level Input Voltage

(TCVDD/2 + 0.5 V) VIH–CLI 1.85 V

Low Level Input Voltage VIL–CLI 0.85 V

RG AND H-DRIVER OUTPUTS

High Level Output Voltage

(RGVDD – 0.5 V and HVDD – 0.5 V) VOH 2.2 V

Low Level Output Voltage VOL 0.5 V

Maximum Output Current (Programmable) 30 mA

Maximum Load Capacitance 100 pF

AD9949

Rev. B | Page 4 of 36

ANALOG SPECIFICATIONS

TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, unless otherwise noted.

Table 3.

Parameter Min Typ Max Unit Notes

CDS

Gain 0 dB

Allowable CCD Reset Transient1 500 mV

Maximum Input Range before Saturation1 1.0 V p-p

Maximum CCD Black Pixel Amplitude1 ±50 mV

PIXEL GAIN AMPLIFIER (P×GA)

Gain Control Resolution 256 Steps

Gain Monotonicity

Minimum Gain 0 dB

Maximum Gain 18 dB

VARIABLE GAIN AMPLIFIER (VGA)

Maximum Input Range 1.0 V p-p

Maximum Output Range 2.0 V p-p

Gain Control Resolution 1024 Steps

Gain Monotonicity Guaranteed

Gain Range

Minimum Gain (VGA Code 0) 6 dB

Maximum Gain (VGA Code 1023) 42 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps

Clamp Level Measured at ADC output

Minimum Clamp Level (0) 0 LSB

Maximum Clamp Level (255) 255 LSB

A/D CONVERTER

Resolution 12 Bits

Differential Nonlinearity (DNL) −1.0 ±0.5 +1.0 LSB

No Missing Codes Guaranteed

Integral Nonlinearity (INL) 8 LSB

Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (REFT) 2.0 V

Reference Bottom Voltage (REFB) 1.0 V

SYSTEM PERFORMANCE Specifications include entire signal chain

VGA Gain Accuracy

Minimum Gain (Code 0) 5.0 5.5 6.0 dB

Maximum Gain (Code 1023) 40.5 41.5 42.5 dB

Peak Nonlinearity, 500 mV Input Signal 0.15 0.6 % 12 dB gain applied

Total Output Noise 0.8 LSB rms AC grounded input, 6 dB gain applied

Power Supply Rejection (PSR) 50 dB Measured with step change on supply

1 Input signal characteristics defined as follows:

50mV MAX

OPTICAL BLACK PIXEL

500mV TYP

RESET TRANSIENT

1V MAX

INPUT SIGNAL RANGE

03751-002

AD9949

Rev. B | Page 5 of 36

TIMING SPECIFICATIONS

CL = 20 pF, fCLI = 36 MHz, unless otherwise noted.

Table 4.

Parameter Symbol Min Typ Max Unit

MASTER CLOCK (CLI) (See Figure 16)

CLI Clock Period tCLI 27.8 ns

CLI High/Low Pulse Width tADC 11.2 13.9 16.6 ns

Delay from CLI to Internal Pixel Period Position tCLIDLY 6 ns

CLPOB PULSE WIDTH (PROGRAMMABLE)1 t

COB 2 20 Pixels

SAMPLE CLOCKS (See Figure 18)

SHP Rising Edge to SHD Rising Edge tS1 12.5 13.9 ns

DATA OUTPUTS (See Figure 19 and Figure 20)

Output Delay From Programmed Edge tOD 6 ns

Pipeline Delay 11 Cycles

SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15)

Maximum SCK Frequency fSCLK 10 MHz

SL to SCK Setup Time tLS 10 ns

SCK to SL Hold Time tLH 10 ns

SDATA Valid to SCK Rising Edge Setup tDS 10 ns

SCK Falling Edge to SDATA Valid Hold tDH 10 ns

SCK Falling Edge to SDATA Valid Read tDV 10 ns

1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.

AD9949

Rev. B | Page 6 of 36

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

With

Respect to Rating

AVDD and TCVDD AVSS −0.3 V to +3.9 V

HVDD and RGVDD HVSS,

RGVSS

−0.3 V to +3.9 V

DVDD and DRVDD DVSS,

DRVSS

−0.3 V to +3.9 V

Any VSS Any VSS −0.3 V to +0.3 V

Digital Outputs DRVSS −0.3 V to DRVDD + 0.3 V

CLPOB/PBLK and HBLK DVSS −0.3 V to DVDD + 0.3 V

SCK, SL, and SDATA DVSS −0.3 V to DVDD + 0.3 V

RG RGVSS −0.3 V to RGVDD + 0.3 V

H1 to H4 HVSS −0.3 V to HVDD + 0.3 V

REFT, REFB, and CCDIN AVSS −0.3 V to AVDD + 0.3 V

Junction Temperature 150°C

Lead Temperature (10 s) 300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect device

reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

40-Lead LFCSP Package: θJA = 27°C/W1.

1 θJA is measured using a 4-layer PCB with the exposed paddle soldered to the

board.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-

trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation

or loss of functionality.

AD9949

Rev. B | Page 7 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

03751-003

AD9949

TOP VIEW

DRVDD

DRVSS

RGVSS

HVDD

HVSS

(MSB) D11

D10

REFB

RGVDD

TCVSS

TCVDD

CLI

AVDD

CCDIN

AVSS

REFT

D0 (LSB)

CLP/PBLK

HBLK

DVDD

DVSS

SCK

SDI

PIN 1

INDICATOR

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 to 4 D1 to D4 DO Data Outputs

5 DRVSS P Digital Driver Ground

6 DRVDD P Digital Driver Supply

7 to 13 D5 to D11 DO Data Outputs (D11 is MSB)

14 H1 DO CCD Horizontal Clock 1

15 H2 DO CCD Horizontal Clock 2

16 HVSS P H1 to H4 Driver Ground

17 HVDD P H1 to H4 Driver Supply

18 H3 DO CCD Horizontal Clock 3

19 H4 DO CCD Horizontal Clock 4

20 RGVSS P RG Driver Ground

21 RG DO CCD Reset Gate Clock

22 RGVDD P RG Driver Supply

23 TCVSS P Analog Ground for Timing Core

24 TCVDD P Analog Supply for Timing Core

25 CLI DI Master Clock Input

26 AVDD P Analog Supply for AFE

27 CCDIN AI Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)

28 AVSS P Analog Ground for AFE

29 REFT AO Reference Top Decoupling (Decouple with 1.0 µF to AVSS)

30 REFB AO Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)

31 SL DI 3-Wire Serial Load

32 SDI DI 3-Wire Serial Data Input

33 SCK DI 3-Wire Serial Clock

34 VD DI Vertical Sync Pulse

35 HD DI Horizontal Sync Pulse

36 DVSS P Digital Ground

37 DVDD P Digital Supply

38 HBLK DI Optional HBLK Input

39 CLP/PBLK DO CLPOB or PBLK Output

40 D0 DO Data Output LSB

1 Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

AD9949

Rev. B | Page 8 of 36

TERMINOLOGY

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus, every

code must have a finite width. No missing codes guaranteed to

12-bit resolution indicates that all 4096 codes, respectively, must

be present over all operating conditions.

Integral Nonlinearity (INL)

INL is the deviation of each individual code measured from a

true straight line from zero to full scale. The point used as zero

scale occurs 0.5 LSB before the first code transition. Positive full

scale is defined as a level 1 LSB and 0.5 LSB beyond the last

code transition. The deviation is measured from the middle of

each particular output code to the true straight line.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the output of the AD9949 from a straight line.

The point used as zero scale occurs 0.5 LSB before the first code

transition. Positive full scale is defined as a level 1 LSB and

0.5 LSB beyond the last code transition. The deviation is

measured from the middle of each particular output code to the

straight line reference. The error is then expressed as a

percentage of the 2 V ADC full-scale signal. The input signal is

appropriately gained up to fill the ADC’s full-scale range.

Total Output Noise

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

in LSB and represents the rms noise level of the total signal

chain at the specified gain setting. The output noise can be con-

verted to an equivalent voltage, using the relationship

1 LSB = (ADC full scale/2n codes)

where n is the bit resolution of the ADC. For the AD9949,

1 LSB is approximately 0.488 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply

pins. The PSR specification is calculated from the change in the

data outputs for a given step change in the supply voltage.

AD9949

Rev. B | Page 9 of 36

EQUIVALENT INPUT/OUTPUT CIRCUITS

AVDD

AVSS AVSS

03751-004

Figure 3. CCDIN (Pin 27)

AVDD

AVSS

330Ω

CLI 25kΩ

1.4V

03751-005

Figure 4. CLI (Pin 25)

DVSS DRVDD

DVSS DRVSS

DATA

THREE-STATE DOUT

03751-006

Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40)

03751-007

DVDD

DVSS

330Ω

Figure 6. Digital Inputs (Pins 31 to 35, 38)

03751-008

HVDD OR RGVDD

HVSS OR RGVSS

DATA

ENABLE DOUT

Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21)

AD9949

Rev. B | Page 10 of 36

TYPICAL PERFORMANCE CHARACTERISTICS

03751-009

ADC OUTPUT CODE 40000 500 1000 1500 2000 2500 3000 3500

DNL (LSB)

1.0

0.5

–0.5

–1.0

Figure 8. Typical DNL

03751-010

VGA GAIN CODE (LSB) 10000 200 400 600 800

OUTPUT NOISE (LSB)

Figure 9. Output Noise vs. VGA Gain

03751-011

SAMPLE RATE (MHz) 3618 24 30

POWER DISSIPATION (mW)

400

350

300

250

200

150

= 3.3V V

= 3.0V

= 2.7V

Figure 10. Power Curves

AD9949

Rev. B | Page 11 of 36

SYSTEM OVERVIEW

CCD

SERIAL

INTERFACE

DOUT

DIGITAL IMAGE

PROCESSING

ASIC

V-DRIVER

HD, VD

CLI

V1 TO Vx, VSG1 TO VSGx, SUBCK

H1 TO H4, RG

CCDIN

AD9949

INTEGRATED

AFE + TD

03751-012

Figure 11. Typical Application

Figure 11 shows the typical system application diagram for the

AD9949. The CCD output is processed by the AD9949’s AFE

circuitry, which consists of a CDS, a PxGA, a VGA, a black level

clamp, and an ADC. The digitized pixel information is sent to

the digital image processor chip where all postprocessing and

compression occurs. To operate the CCD, CCD timing

parameters are programmed into the AD9949 from the image

processor through the 3-wire serial interface. From the system

master clock, CLI, provided by the image processor, the

AD9949 generates the high speed CCD clocks and all internal

AFE clocks. All AD9949 clocks are synchronized with VD and

HD. The AD9949’s horizontal pulses (CLPOB, PBLK, and

HBLK) are programmed and generated internally.

The H-drivers for H1 to H4 and RG are included in the

AD9949, allowing these clocks to be directly connected to the

CCD. The H-drive voltage of 3 V is supported in the AD9949.

Figure 12 shows the horizontal and vertical counter dimensions

for the AD9949. All internal horizontal clocking is programmed

using these dimensions to specify line and pixel locations.

H-COUNTER BEHAVIOR

When the maximum horizontal count of 4096 pixels is

exceeded, the H-counter in the AD9949 rolls over to zero and

continues counting. It is, therefore, recommended that the

maximum counter value not be exceeded.

However, the newer AD9949A version behaves differently. In

the AD9949A, the internal H-counter holds at its maximum

count of 4095 instead of rolling over. This feature allows the

AD9949A to be used in applications containing a line length

greater than 4096 pixels. Although no programmable values for

the horizontal blanking or clamping are available beyond pixel

4095, the H, RG, and AFE clocking continues to operate,

sampling the remaining pixels on the line.

MAXIMUM FIELD DIMENSIONS

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

03751-013

Figure 12. Vertical and Horizontal Counters

CLI

MAX HD LENGTH IS 4095 PIXELS

03751-014

MAX VD LENGTH IS 4095 LINES

Figure 13. Maximum VD/HD Dimensions

AD9949

Rev. B | Page 12 of 36

SERIAL INTERFACE TIMING

The AD9949’s internal registers are accessed through a 3-wire

serial interface. Each register consists of an 8-bit address and a

24-bit data-word. Both the 8-bit address and 24-bit data-word

are written starting with the LSB. To write to each register, a

32-bit operation is required, as shown in Figure 14. Although

many registers are less than 24 bits wide, all 24 bits must be

written for each register. If the register is only 16 bits wide, then

the upper eight bits may be filled with zeros during the serial

write operation. If fewer than 24 bits are written, the register

will not be updated with new data.

Figure 15 shows a more efficient way to write to the registers by

using the AD9949’s address auto-increment capability. Using

this method, the lowest desired address is written first, followed

by multiple 24-bit data-words. Each new 24-bit data-word is

written automatically to the next highest register address. By

eliminating the need to write each 8-bit address, faster register

loading is achieved. Address auto-increment may be used start-

ing with any register location and may be used to write to as few

as two registers or as many as the entire register space.

SDAT

A0 A1 A2 A4 A5 A6 A7 D0 D1 D2 D3 D21 D22 D23

SCK

NOTES

1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.

2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.

3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.

4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.

5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.

SL UPDATED VD/HD UPDATED

...

8-BIT ADDRESS 24-BIT DATA

1 322 3 4 5 6 7 8 9 10 11 12 30 31

03751-015

Figure 14. Serial Write Operation

SDATA A0 A1 A2 A4 A5 A6 A7 D0 D1 D22 D23

SCK

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.

3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.

D0 D1 D22 D23 D0 ...

...

DATA FOR STARTING

D2D1

...

1 322345678910 31 3433 5655 58

57 59

03751-016

Figure 15. Continuous Serial Write Operation

AD9949

Rev. B | Page 13 of 36

COMPLETE REGISTER LISTING

1. All addresses and default values are expressed in

hexadecimal.

2. All registers are VD/HD updated as shown in Figure 14,

except for the registers indicated in Table 7, which are SL

updated.

Table 7. SL Updated Registers

OPRMODE AFE Operation Modes

CTLMODE AFE Control Modes

SW_RESET Software Reset Bit

TGCORE _RSTB Reset Bar Signal for Internal TG Core

PREVENTUPDATE Prevents Update of Registers

VDHDEDGE VD/HD Active Edge

FIELDVAL Resets Internal Field Pulse

HBLKRETIME Retimes the HBLK to Internal Clock

CLPBLKOUT CLP/BLK Output Pin Select

CLPBLKEN Enables CLP/BLK Output Pin

H1CONTROL H1/H2 Polarity/Edge Control

RGCONTROL RG Polarity/Edge Control

DRVCONTROL RG and H1 to H4 Drive Current

SAMPCONTROL SHP/SHD Sampling Edge Control

DOUTPHASE Data Output Phase Adjustment

AD9949

Rev. B | Page 14 of 36

Table 8. AFE Register Map

Address

Data Bit

Content Default Value Name Description

00 [11:0] 4 OPRMODE AFE Operation Modes. (See Table 14.)

01 [9:0] 0 VGAGAIN VGA Gain.

02 [7:0] 80 CLAMP LEVEL Optical Black Clamp Level.

03 [11:0] 4 CTLMODE AFE Control Modes. (See Table 15.)

04 [17:0] 0 PxGA GAIN01 PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].

05 [17:0] 0 PxGA GAIN23 PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].

Table 9. Miscellaneous Register Map

Address

Data Bit

Content Default Value Name Description

10 [0] 0 SW_RST Software Reset.

1 = Reset all registers to default, then self-clear back to 0.

11 [0] 0 OUT_CONTROL Output Control.

0 = Make all dc outputs inactive.

12 [0] 0 TGCORE_RSTB Timing Core Reset Bar.

0 = Reset TG core.

1 = Resume operation.

13 [11:0] 0 UPDATE Serial Update.

Sets the line (HD) within the field to update serial data.

14 [0] 0 PREVENTUPDATE Prevents the update of the VD updated registers.

1 = Prevent Update.

15 [0] 0 VDHDEDGE VD/HD Active Edge.

0 = Falling Edge Triggered.

1 = Rising Edge Triggered.

16 [1:0] 0 FIELDVAL Field Value Sync.

0 = Next Field 0.

1 = Next Field 1.

2/3 = Next Field 2.

17 [0] 0 HBLKRETIME Retime HBLK to Internal H1 Clock.

Preferred setting is 1. Setting to 1 adds one cycle delay to HBLK

toggle positions.

18 [1:0] 0 CLPBLKOUT CLP/BLK Pin Output Select.

0 = CLPOB.

1 = PBLK.

2 = HBLK.

3 = Low.

19 [0] 1 CLPBLKEN Enable CLP/BLK Output.

1 = Enable.

1A [0] 0 TEST MODE Internal Test Mode.

Should always be set high.

AD9949

Rev. B | Page 15 of 36

Table 10. CLPOB Register Map

Address

Data Bit

Content

Default Value

(Hex) Name Description

20 [3:0] F CLPOBPOL Start Polarities for CLPOB Sequences 0, 1, 2, and 3.

21 [23:0] FFFFFF CLPOBTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

22 [23:0] FFFFFF CLPOBTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

23 [23:0] FFFFFF CLPOBTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

24 [23:0] FFFFFF

CLPOBTOG_3

CLPOBSCP0

Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

CLPOB Sequence-Change Position 0 (Hard-Coded to 0).

25 [7:0] 0 CLPOBSPTR CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2[5:4], 3[7:6].

26 [11:0] FFF CLPOBSCP1 CLPOB Sequence-Change Position 1.

27 [11:0] FFF CLPOBSCP2 CLPOB Sequence-Change Position 2.

28 [11:0] FFF CLPOBSCP3 CLPOB Sequence-Change Position 3.

Table 11. PBLK Register Map

Address

Data Bit Con-

tent

Default Value

(Hex) Name Description

30 [3:0] F PBLKPOL Start Polarities for PBLK Sequences 0, 1, 2, and 3.

31 [23:0] FFFFFF PBLKTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

32 [23:0] FFFFFF PBLKTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

33 [23:0] FFFFFF PBLKTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

34 [23:0] FFFFFF

PBLKTOG_3

PBLKSCP0

Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

PBLK Sequence-Change Position 0 (Hard-Coded to 0).

35 [7:0] 0 PBLKSPTR PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].

36 [11:0] FFF PBLKSCP1 PBLK Sequence-Change Position 1.

37 [11:0] FFF PBLKSCP2 PBLK Sequence-Change Position 2.

38 [11:0] FFF PBLKSCP3 PBLK Sequence-Change Position 3.

AD9949

Rev. B | Page 16 of 36

Table 12. HBLK Register Map

Address

Data Bit

Content

Default Value

(Hex) Name Description

40 [0] 0 HBLKDIR HBLK Internal/External.

0 = Internal.

1 = External.

41 [0] 0 HBLKPOL HBLK External Active Polarity.

0 = Active Low.

1 = Active High.

42 [0] 1 HBLKEXTMASK HBLK External Masking Polarity.

0 = Mask H1 Low.

1 = Mask H1High.

43 [3:0] F HBLKMASK HBLK Internal Masking Polarity for Each Sequence 0 to 3.

0 = Mask H1 Low.

1 = Mask H1 High.

44 [23:0] FFFFFF HBLKTOG12_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

45 [23:0] FFFFFF HBLKTOG34_0 Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].

46 [23:0] FFFFFF HBLKTOG56_0 Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].

47 [23:0] FFFFFF HBLKTOG12_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

48 [23:0] FFFFFF HBLKTOG34_1 Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].

49 [23:0] FFFFFF HBLKTOG56_1 Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].

4A [23:0] FFFFFF HBLKTOG12_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

4B [23:0] FFFFFF HBLKTOG34_2 Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].

4C [23:0] FFFFFF HBLKTOG56_2 Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].

4D [23:0] FFFFFF HBLKTOG12_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].

4E [23:0] FFFFFF HBLKTOG34_3 Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].

4F [23:0] FFFFFF

HBLKTOG56_3

HBLKSCP0

Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6[23:12].

HBLK Sequence-Change Position 0 (Hard-coded to 0).

50 [7:0] 0 HBLKSPTR HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].

51 [11:0] FFF HBLKSCP1 HBLK Sequence-Change Position 1.

52 [11:0] FFF HBLKSCP2 HBLK Sequence-Change Position 2.

53 [11:0] FFF HBLKSCP3 HBLK Sequence-Change Position 3.

Table 13. H1 to H2, RG, SHP, SHD Register Map

Address

Data Bit

Content Default Value Name Description

60 [12:0] 01001 H1CONTROL H1 Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion).

H1 Positive Edge Location [6:1].

H1 Negative Edge Location [12:7].

61 [12:0] 00801 RGCONTROL RG Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion).

RG Positive Edge Location [6:1].

RG Negative Edge Location [12:7].

62 [14:0] 0 DRVCONTROL Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and RG

[14:12].

Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA,

3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.

63 [11:0] 00024 SAMPCONTROL SHP/SHD Sample Control. SHP Sampling Location [5:0]. SHD Sampling

Location [11:6].

64 [5:0] 0 DOUTPHASE DOUT Phase Control.

AD9949

Rev. B | Page 17 of 36

Table 14. AFE Operation Register Detail

Address

Data Bit

Content

Default

Value Name Description

00 [1:0] 0 PWRDOWN 0 = Normal Operation.

1 = Reference Standby.

2/3 = Total Power-Down

[2] 1 CLPENABLE 0 = Disable OB Clamp.

1 = Enable OB Clamp.

[3] 0 CLPSPEED 0 = Select Normal OB Clamp Settling.

1 = Select Fast OB Clamp Settling.

[4] 0 FASTUPDATE 0 = Ignore VGA Update.

1 = Very Fast Clamping when VGA Is Updated.

[5] 0 PBLK_LVL DOUT Value during PBLK.

0 = Blank to Zero.

1 = Blank to Clamp Level.

[7:6] 0 TEST MODE Test Operation Only. Set to zero.

[8] 0 DCBYP 0 = Enable DC restore circuit.

1 = Bypass DC Restore Circuit during PBLK.

[9] 0 TESTMODE Test Operation Only. Set to zero.

[11:10] 0 CDSGAIN Adjustment of CDS Gain.

0 = 0 dB.

01 = −2 dB.

10 = −4 dB.

11 = 0 dB.

Table 15. AFE Control Register Detail

Address

Data Bit

Content

Default

Value Name Description

03 [1:0] 0 COLORSTEER 0 = Off.

1 = Progressive.

2 = Interlaced.

3 = Three Field.

[2] 1 PxGAENABLE 0 = Disable PxGA.

1 = Enable PxGA.

[3] 0 DOUTDISABLE 0 = Data Outputs Are Driven.

1 = Data Outputs Are Three-Stated.

[4] 0 DOUTLATCH 0 = Latch Data Outputs with DOUT Phase.

1 = Output Latch Transparent.

[5] 0 GRAYENCODE 0 = Binary Encode Data Outputs.

1 = Gray Encode Data Outputs.

AD9949

Rev. B | Page 18 of 36

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9949 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for gener-

ating the timing used for both the CCD and the AFE: the reset

gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD

sample clocks. A unique architecture makes it routine for the

system designer to optimize image quality by providing precise

control over the horizontal CCD readout and the AFE corre-

lated double sampling.

TIMING RESOLUTION

The Precision Timing core uses a 1× master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 16 illustrates how the internal timing

core divides the master clock period into 48 steps or edge

positions. Therefore, the edge resolution of the Precision Timing

core is (tCLI/48). For more information on using the CLI input,

refer to the Applications Information section.

HIGH SPEED CLOCK PROGRAMMABILITY

Figure 17 shows how the high speed clocks, RG, H1 to H4,

SHP, and SHD, are generated. The RG pulse has programma-

ble rising

and falling edges and may be inverted using the

polarity control. The horizontal clocks H1 and H3 have

programmable r

ising and falling edges and polarity control.

H2 and H4 clocks are always inverses of H1 and H3, re-

spectively. Table 16 summarizes the high speed timing registers

and their parameters.

Each edge location setting is 6 bits wide, but only 48 valid edge

locations are available. Therefore, the register values are

mapped into four quadrants, with each quadrant containing

12 edge locations. Table 17 shows the correct register values for

the corresponding edge locations.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

CLIDLY

= 6 ns TYP).

P[0] P[48] = P[0]P[12] P[24] P[36]

1 PIXEL

PERIOD

... ...

CLI

CLIDLY

POSITION

03751-017

Figure 16. High Speed Clock Resolution from CLI Master Clock Input

H1/H3

H2/H4

CCD SIGNAL

PROGRAMMABLE CLOCK POSITIONS:

1. RG RISING EDGE.

2. RG FALLING EDGE.

3. SHP SAMPLE LOCATION.

4. SHD SAMPLE LOCATION.

5. H1/H3 RISING EDGE POSITION6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).

03751-018

Figure 17. High Speed Clock Programmable Locations

AD9949

Rev. B | Page 19 of 36

Table 16. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters

Parameter Length Range Description

Polarity 1b High/Low Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion).

Positive Edge 6b 0 to 47 Edge Location Positive Edge Location for H1/H3 and RG.

Negative Edge 6b 0 to 47 Edge Location Negative Edge Location for H1/H3 and RG.

Sample Location 6b 0 to 47 Sample Location Sampling Location for SHP and SHD.

Drive Control 3b 0 to 7 Current Steps Drive Current for H1 to H4 and RG Outputs, 0 to 7 Steps of 4.1 mA Each.

DOUT Phase 6b 0 to 47 Edge Location Phase Location of Data Outputs with Respect to Pixel Period.

Table 17. Precision Timing Edge Locations

Quadrant Edge Location (Decimal) Register Value (Decimal) Register Value (Binary)

I 0 to 11 0 to 11 000000 to 001011

II 12 to 23 16 to 27 010000 to 011011

III 24 to 35 32 to 43 100000 to 101011

IV 36 to 47 48 to 59 110000 to 111011

H-DRIVER AND RG OUTPUTS

In addition to the programmable timing positions, the AD9949 features on-chip output drivers for the RG and H1 to H4 outputs. These

drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG driver current can be adjusted for optimum rise/fall

time into a particular load by using the DRVCONTROL register (Address 0×62). The DRVCONTROL register is divided into five differ-

ent 3-bit values, each one being adjustable in 4.1 mA increments. The minimum setting of 0 is equal to OFF or three-state, and the maxi-

mum setting of 7 is equal to 30.1 mA.

As shown in Figure 18, the H2/H4 outputs are inverses of H1/H3. The internal propagation delay resulting from the signal inversion is

less than l ns, which is significantly less than the typical rise time driving the CCD load. This results in a H1/H2 crossover voltage at ap-

proximately 50% of the output swing. The crossover voltage is not programmable.

DIGITAL DATA OUTPUTS

The AD9949 data output phase is programmable using the DOUTPHASE register (Address 0×64). Any edge from 0 to 47 may be pro-

grammed, as shown in Figure 19. The pipeline delay for the digital data output is shown in Figure 20.

FIXED CROSSOVER VOLTAGE

H1/H3 H2/H4

tPD

H2/H4

H1/H3

tRISE

tPD

tRISE

03751-019

Figure 18. H-Clock Inverse Phase Relationship

AD9949

Rev. B | Page 20 of 36

NOTES

1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.

P[0] P[48] = P[0]

CLI

1 PIXEL PERIOD

P[12] P[24] P[36]

DOUT

03751-020

Figure 19. Digital Output Phase Adjustment

NOTES

1. DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

DOUT

CCDIN

CLI

SHD

(INTERNAL)

N N + 1 N + 2 N + 12N + 11N + 10N + 9N + 8N + 7N + 6N + 5N + 4N + 3 N + 13

N – 13 N– 3N– 4N– 5N– 6N– 7N– 8N– 9N – 10N – 11

N – 12 N– 2 N– 1 N + 1

SAMPLE PIXEL N

N– 1

03751-021

tCLIDLY

PIPELINE LATENCY = 11 CYCLES

Figure 20. Pipeline Delay for Digital Data Output

AD9949

Rev. B | Page 21 of 36

HORIZONTAL CLAMPING AND BLANKING

The AD9949’s horizontal clamping and blanking pulses are fully

programmable to suit a variety of applications. Individual

sequences are defined for each signal, which are then organized

into multiple regions during image readout. This allows the

dark pixel clamping and blanking patterns to be changed at

each stage of the readout to accommodate different image

transfer timing and high speed line shifts.

INDIVIDUAL CLPOB AND PBLK SEQUENCES

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 21. These two signals are independently

programmed using the parameters shown in Table 18. The start

polarity, first toggle position, and second toggle position are

fully programmable for each signal. The CLPOB and PBLK

signals are active low and should be programmed accordingly.

Up to four individual sequences can be created for each signal.

INDIVIDUAL HBLK SEQUENCES

The HBLK programmable timing shown in Figure 22 is similar

to CLPOB and PBLK. However, there is no start polarity

control.

Only the toggle positions are used to designate the

start and the stop positions of the blanking period. Additionally,

there is a polarity control, HBLKMASK, which designates the

polarity of the horizontal clock signals H1 to H4 during the

blanking period. Setting HBLKMASK high sets H1 = H3 = low

and H2 = H4 = high during the blanking,

as shown in Figure 23.

Up to four individual sequences are available for HBLK.

CLPOB

PBLK

PROGRAMMABLE SETTINGS:

1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).

2. FIRST TOGGLE POSITION.

3. SECOND TOGGLE POSITION.

ACTIVE ACTIVE

03751-022

...

Figure 21. Clamp and Preblank Pulse Placement

HBLK

PROGRAMMABLE SETTINGS:

1. FIRST TOGGLE POSITION = START OF BLANKING.

2. SECOND TOGGLE POSITION = END OF BLANKING.

BLANK BLANK

03751-023

...

Figure 22. Horizontal Blanking (HBLK) Pulse Placement

Table 18. CLPOB and PBLK Individual Sequence Parameters

Parameter Length Range Description

Polarity 1b High/Low Starting Polarity of Clamp and PBLK Pulses for Sequences 0 to 3.

Toggle Position 1 12b 0 to 4095 Pixel Location First Toggle Position within the Line for Sequences 0 to 3.

Toggle Position 2 12b 0 to 4095 Pixel Location Second Toggle Position within the Line for Sequences 0 to 3.

Table 19. HBLK Individual Sequence Parameters

Parameter Length Range Description

HBLKMASK 1b High/Low Masking Polarity for H1 for Sequences 0 to 3 (0 = H1 Low, 1 = H1 High).

Toggle Position 1 12b 0 to 4095 Pixel Location First Toggle Position within the Line for Sequences 0 to 3.

Toggle Position 2 12b 0 to 4095 Pixel Location Second Toggle Position within the Line for Sequences 0 to 3.

Toggle Position 3 12b 0 to 4095 Pixel Location Third Toggle Position within the Line for Sequences 0 to 3.

Toggle Position 4 12b 0 to 4095 Pixel Location Fourth Toggle Position within the Line for Sequences 0 to 3.

Toggle Position 5 12b 0 to 4095 Pixel Location Fifth Toggle Position within the Line for Sequences 0 to 3.

Toggle Position 6 12b 0 to 4095 Pixel Location Sixth Toggle Position within the Line for Sequences 0 to 3.

AD9949

Rev. B | Page 22 of 36

HBLK

THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).

H1/H3

H2/H4

...

03751-024

Figure 23. HBLK Masking Control

HBLK

SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.

H1/H3

H2/H4

TOG1 TOG2 TOG3 TOG4 TOG5 TOG6

03751-025

Figure 24. Generating Special HBLK Patterns

Table 20. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK

SCP 12b 0 to 4095 Line Number CLOB/PBLK/HBLK SCP to Define Horizontal Regions 0 to 3.

SPTR 2b 0 to 3 Sequence Number Sequence Pointer for Horizontal Regions 0 to 3.

AD9949

Rev. B | Page 23 of 36

GENERATING SPECIAL HBLK PATTERNS

Six toggle positions are available for HBLK. Normally, only two

of the toggle positions are used to generate the standard HBLK

interval. However, the additional toggle positions may be used

to generate special HBLK patterns, as shown in Figure 24. The

pattern in this example uses all six toggle positions to generate

two extra groups of pulses during the HBLK interval. By

changing the toggle positions, different patterns can be created.

HORIZONTAL SEQUENCE CONTROL

The AD9949 uses sequence change positions (SCP) and

sequence pointers (SPTR) to organize the individual horizontal

sequences. Up to four SCPs are available to divide the readout

into four separate regions, as shown in Figure 25. The SCP0 is

always hard-coded to Line 0, and SCP1 to SCP3 are register

programmable. During each region bounded by the SCP, the

SPTR registers designate which sequence is used by each signal.

CLPOB, PBLK, and HBLK each have a separate set of SCPs. For

example, CLPOBSCP1 defines Region 0 for CLPOB, and in that

region any of the four individual CLPOB sequences may be

selected with the CLPOBSPTR register. The next SCP defines a

new region and in that region, each signal can be assigned to a

different individual sequence. The sequence control registers

are summarized in Table 20.

EXTERNAL HBLK SIGNAL

The AD9949 can also be used with an external HBLK signal.

Setting the HBLKDIR register (Address 0×40) to high disables

the internal HBLK signal generation. The polarity of the exter-

nal signal is specified using the HBLKPOL register, and the

masking polarity of H1 is specified using the HBLKMASK

external HBLK signal.

UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE

PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.

SEQUENCE CHANGE OF POSITION 1

SEQUENCE CHANGE OF POSITION 2

SEQUENCE CHANGE OF POSITION 3

SINGLE FIELD (1 VD INTERVAL)

CLAMP AND PBLK SEQUENCE REGION 0

SEQUENCE CHANGE OF POSITION 0

(V-COUNTER = 0)

CLAMP AND PBLK SEQUENCE REGION 3

CLAMP AND PBLK SEQUENCE REGION 2

CLAMP AND PBLK SEQUENCE REGION 1

03751-026

Figure 25. Clamp and Blanking Sequence Flexibility

Table 21. External HBLK Register Parameters

HBLKDIR 1b High/Low Specifies HBLK Internally Generated or Externally Supplied.

1 = External.

HBLKPOL 1b High/Low External HBLK Active Polarity.

0 = Active Low.

1 = Active High.

HBLKEXTMASK 1b High/Low External HBLK Masking Polarity.

0 = Mask H1 Low.

1 = Mask H1 High.

AD9949

Rev. B | Page 24 of 36

H-COUNTER SYNCHRONIZATION

The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the

internal H-Counter (see Figure 26).

As mentioned in the H-Counter Behavior section, the AD9949 H-counter rolls over to zero and continues counting when the maximum

counter length is exceeded. The newer AD9949A product does not roll over but holds at its maximum value until the next HD rising edge

occurs.

000 1 12111 0 031100

012345678910111214150123

H-COUNTER

RESET

NOTES

1. INTERNAL H-COUNTER IS RESET 7 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).

2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.

3. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).

XXXXXXX

PxGA GAIN

CLI

XXXXXXX

H-COUNTER

(PIXEL COUNTER) X

03751-027

Figure 26. H-Counter Synchronization

AD9949

Rev. B | Page 25 of 36

POWER-UP PROCEDURE

RECOMMENDED POWER-UP SEQUENCE

When the AD9949 is powered up, the following sequence is

recommended (refer to Figure 27 for each step):

1. Turn on the power supplies for the AD9949.

2. Apply the master clock input, CLI, VD, and HD.

3. Although the AD9949 contains an on-chip, power-on reset,

a software reset of the internal registers is recommended.

Write a 1 to the SW_RST register (Address 0×10), which

resets the internal registers to their default values. This bit

is self-clearing and automatically resets back to 0.

4. The Precision Timing core must be reset by writing a 0 to

the TGCORE_RSTB register (Address 0×12) followed by

writing a l to the TGCORE_RSTB register. This starts the

internal timing core operation.

5. Write a 1 to the PREVENTUPDATE register (Address

0×14). This prevents the updating of the serial register

data.

6. Write to the desired registers to configure high speed

timing and horizontal timing.

7. Write a 1 to the OUT_CONTROL register (Address 0×11).

This allows the outputs to become active after the next

VD/HD rising edge.

8. Write a 0 to the PREVENTUPDATE register (Address

0×14). This allows the serial information to be updated at

next VD/HD falling edge.

9. The next VD/HD falling edge allows register updates to

occur, including OUT_CONTROL, which enables all clock

outputs.

VDD

(INPUT)

SERIAL

WRITES

(OUTPUT)

ODD FIELD EVEN FIELD

...

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS

UPDATED AT VD/HD EDGE

H1/H3, RG

H2/H4

PWR

CLI

(INPUT)

(OUTPUT)

...

03751-028

3 4 5 6 7 8

Figure 27. Recommended Power-Up Sequence

AD9949

Rev. B | Page 26 of 36

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9949 signal processing chain is shown in Figure 28.

Each processing step is essential in achieving a high quality

image from the raw CCD pixel data.

DC RESTORE

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to

approximately 1.5 V to be compatible with the 3 V supply

voltage of the AD9949.

CORRELATED DOUBLE SAMPLER

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

shown in Figure 17 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and the CCD signal level, respectively. The placement of

the SHP and SHD sampling edges is determined by the setting

of the SAMPCONTROL register located at Address 0×63.

Placement of these two clock signals is critical in achieving the

best performance from the CCD.

The gain in the CDS is fixed at 0 dB by default. Using Bits D10

and D11 in the AFE operation register, the gain may be reduced

to −2 dB or −4 dB. This allows the AD9949 to accept an input

signal of greater than 1 V p-p. See Table 14 for register details.

Table 22. Adjustable CDS Gain

Operation Register Bits

D11 D10 CDS Gain Max CDS Input

0 0 0 dB 1.0 V p-p

0 1 −2 dB 1.2 V p-p

1 0 −4 dB 1.6 V p-p

1 1 0 dB 1.0 V p-p

PxGA

The PxGA provides separate gain adjustment for the individual

color pixels. A programmable gain amplifier with four separate

values, the PxGA has the capability to multiplex its gain value

on a pixel-to-pixel basis (see Figure 29). This allows lower

output color pixels to be gained up to match higher output color

pixels. Also, the PxGA may be used to adjust the colors for

white balance, reducing the amount of digital processing that

needed. The four different gain values are switched according

to the color steering circuitry. Three different color steering

modes for different types of CCD color filter arrays are

programmable in the AFE CTLMODE register at Address 0×03

(see Figure 33 to Figure 35 for timing examples). For example,

progressive steering mode accommodates the popular Bayer

arrangement of red, green, and blue filters (see Figure 30).

6dB ~ 42dB

CCDIN

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

12-BIT

ADC

VGA

DAC

CDS

INTERNAL

VREF

2V FULL SCALE

0dB ~ 18dB

SHP SHD

PxGA

1.5V

OUTPUT

DATA

LATCH

REFTREFB

DOUT

PHASE

SHP SHD DOUT

PHASE CLPOB PBLK

PBLK

1.0V 2.0V

DOUT

AD9949

0dB, –2dB, –4dB

1.0µF 1.0µF

1.0µF

03751-029

PxGA GAIN

REGISTERS VGA GAIN

CLAMP LEVEL

V-H

TIMING

GENERATION

PRECISION

TIMING

GENERATION

Figure 28. Analog Front End Functional Block Diagram

AD9949

Rev. B | Page 27 of 36

COLOR

STEERING

CONTROL

4:1

MUX

GAIN0

GAIN1

GAIN2

GAIN3

PxGA

PxGA STEERING

MODE

SELECTION

PxGA GAIN

REGISTERS

CONTROL

BITS D0 TO D1

SHP/SHD

VGACDS

03751-030

4:1

MUX

Figure 29. PxGA Block Diagram

LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ...

RRGr

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3, ...

GAIN0, GAIN1, GAIN0, GAIN1, ...

COLOR STEERING MODE:

PROGRESSIVE

RRGrGr

Gb B

CCD: PROGRESSIVE BAYER

Gb B

Gb BGb B

03751-031

Figure 30. CCD Color Filter Example—Progressive Scan

The same Bayer pattern can also be interlaced, and the

interlaced mode should be used with this type of CCD (see

Figure 31). The color steering performs the proper multiplexing

of the R, G, and B gain values (loaded into the PxGA gain

registers) and is synchronized by the user with vertical (VD)

and horizontal (HD) sync pulses. For timing information,

see Figure 34.

LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ...

RRGrGr

LINE1

LINE2

GAIN0, GAIN1, GAIN0, GAIN1, ...

Gb GbBB

LINE0 GAIN2, GAIN3, GAIN2, GAIN3, ...

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3, ...

COLOR STEERING MODE:

INTERLACED

Gb GbBB

RRGrGr

EVEN FIELD

ODD FIELD

CCD: INTERLACED BAYER

03751-032

Figure 31. CCD Color Filter Example—Interlaced Readout

A third type of readout uses the Bayer pattern divided into three

different readout fields. The 3-field mode should be used with

this type of CCD (see Figure 32). The color steering performs

the proper multiplexing of the R, G, and B gain values (loaded

into the PxGA gain registers) and is synchronized by the user

with vertical (VD) and horizontal (HD) sync pulses. For timing

information, see Figure 35.

LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ...

RGr

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3, ...

GAIN0, GAIN1, GAIN0, GAIN1, ...

LINE0 GAIN2, GAIN3, GAIN2, GAIN3, ...

LINE1

LINE2

GAIN0, GAIN1, GAIN0, GAIN1, ...

GAIN2, GAIN3, GAIN2, GAIN3, ...

COLOR STEERING MODE:

THREE FIELD

GbB

RGr

FIRST FIELD

SECOND FIELD

CCD: 3-FIELD READOUT

LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ...

RGr

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3, ...

GAIN0, GAIN1, GAIN0, GAIN1, ...

RGr

THIRD FIELD

GbB

RGr

GbB

Gb GbB

03751-033

Figure 32. CCD Color Filter Example—Three-Field Readout

AD9949

Rev. B | Page 28 of 36

22033 11

NOTES

1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.

2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.

3. FIELDVAL IS ALWAYS RESET TO 0 ON VD FALLING EDGES.

110XX

PxGA GAIN

FIELDVAL

FIELDVAL = 0

022033 11110000

FIELDVAL = 0

03751-034

Figure 33. PxGA Color Steering—Progressive Mode

00 311 22

NOTES

1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.

2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.

3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER 0 (FIELDVAL = 0) OR 2 (FIELDVAL = 1).

4. FIELDVAL WILL TOGGLE BETWEEN 0 AND 1 ON EACH VD FALLING EDGE.

110XX

PxGA GAIN

FIELDVAL

FIELDVAL = 0

31100 0033221

FIELDVAL = 1 FIELDVAL = 0

03751-035

Figure 34. PxGA Color Steering—Interlaced Mode

22 333 22

NOTES

1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.

2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.

3. FIELDVAL = 2 (START OF THIRD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.

4. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.

5. FIELDVAL WILL INCREMENT AT EACH VD FALLING EDGE, REPEATING THE 0...1...2...0...1...2 PATTERN.

110XX

PxGA GAIN

FIELDVAL

FIELDVAL = 0

31100 2200113

FIELDVAL = 1 FIELDVAL = 2

03751-036

Figure 35. PxGA Color Steering—Three-Field Mode

AD9949

Rev. B | Page 29 of 36

The PxGA gain for each of the four channels is variable from

0 dB to 18 dB in 512 steps, specified using the PxGA GAIN01

and PxGA GAIN23 registers. The PxGA gain curve is shown in

Figure 36. The PxGA GAIN01 register contains nine bits each

for PxGA Gain0 and Gain1, and the PxGA GAIN23 register

contains nine bits each for PxGA Gain2 and Gain3.

PxGA GAIN REGISTER CODE

PxGA GAIN (dB)

64 128 192 256 320 384 448 511

03751-037

Figure 36. PxGA Gain Curve

VARIABLE GAIN AMPLIFIER

The VGA stage provides a gain range of 6 dB to 42 dB, pro-

grammable with 10-bit resolution through the serial digital

interface. The minimum gain of 6 dB is needed to match a 1 V

input signal with the ADC full-scale range of 2 V. When com-

pared to 1 V full-scale systems, the equivalent gain range is 0

dB to 36 dB.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain can be calculated for any gain register value by

using the equation

Gain (db) = (0.0351 × Code) + 6 dB

where the code range is 0 to 1023.

There is a restriction on the maximum amount of gain that can

be applied to the signal. The PxGA can add as much as 18 dB,

and the VGA is capable of providing up to 42 dB. However, the

maximum total gain from the PxGA and VGA is restricted to

42 dB. If the registers are programmed to specify a total gain

higher than 42 dB, the total gain is clipped at 42 dB.

ADC

The AD9949 uses a high performance ADC architecture,

optimized for high speed and low power. DNL performance is

typically better than 0.5 LSB. The ADC uses a 2 V input range.

See Figure 9 and Figure 10 for typical linearity and noise

performance plots for the AD9949.

03751-038

VGA GAIN REGISTER CODE 10230 127 255 383 511 639 767 895

VGA GAIN (dB)

Figure 37. VGA Gain Curve (PxGA Not Included)

OPTICAL BLACK CLAMP

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixe

l in-

terval

on each line, the ADC output is compared with a fixed

black level reference, selected by the user in the clamp level reg

is-

ter. The value can be programmed between 0 LSB and 255 LSB

in 256 steps. The resulting error signal is filtered to reduce noise,

and the correction value is applied to the ADC input through a

DAC. Normally, the optical black clamp loop is turned on once

per

horizontal line, but this loop can be updated more slowly to

suit a particular application. If external digital clamping is used

during the postprocessing, the AD9949 optical black clamping

may be disabled using Bit D2 in the OPRMODE register. When

the loop is disabled, the clamp level register may still be used to

provide programmable offset adjustment

The CLPOB pulse should be placed during the CCD’s optical

black pixels. It is recommended that the CLPOB pulse duration

be at least 20 pixels wide to minimize clamp noise. Shorter pulse

widths may be used, but clamp noise may increase and the

ability to track low frequency variations in the black level will

be reduced. See the Horizontal Clamping and Blanking and

Applications Information sections for timing examples.

DIGITAL DATA OUTPUTS

The AD9949 digital output data is latched using the DOUT

phase register value, as shown in Figure 28. Output data timing

is shown in Figure 19 and Figure 20. It is also possible to leave

the output latches transparent, so that the data outputs are valid

immediately from the ADC. Programming the AFE control

data outputs can also be disabled (three-stated) by setting the

AFE control register Bit D3 to a 1.

The data output coding is normally straight binary, but the

coding may be changed to gray coding by setting the AFE

control register Bit D5 to a 1.

AD9949

Rev. B | Page 30 of 36

APPLICATIONS INFORMATION

CIRCUIT CONFIGURATION

The AD9949 recommended circuit configuration is shown in

Figure 38. Achieving good image quality from the AD9949

requires careful attention to PCB layout. All signals should be

routed to maintain low noise performance. The CCD output

signal should be directly routed to Pin 27 through a 0.1 µF

capacitor. The master clock CLI should be carefully routed to

Pin 25 to minimize interference with the CCDIN, REFT, and

REFB signals.

The digital outputs and clock inputs are located on Pins 1 to 13

and Pins 31 to 40 and should be connected to the digital ASIC

away from the analog and CCD clock signals. Placing series

resistors close to the digital output pins may help to reduce

digital code transition noise. If the digital outputs must drive a

load larger than 20 pF, buffering is recommended to minimize

additional noise. If the digital ASIC can accept gray code, the

AD9949’s outputs can be selected to output data in gray code

format using the control register Bit D5. Gray coding helps reduce

potential digital transition noise compared with binary coding.

The H1–H4 and RG traces should have low inductance to avoid

excessive distortion of the signals. Heavier traces are recom-

mended because of the large transient current demand on

H1–H4 from the capacitive load of the CCD. If possible,

physically locating the AD9949 closer to the CCD will reduce

the inductance on these lines. As always, the routing path

should be as direct as possible from the AD9949 to the CCD.

GROUNDING AND DECOUPLING

RECOMMENDATIONS

As shown in Figure 38, a single ground plane is recommended

for the AD9949. This ground plane should be as continuous as

possible, particularly around Pins 23 to 30. This ensures that all

analog decoupling capacitors provide the lowest possible

impedance path between the power and bypass pins and their

respective ground pins. All high frequency decoupling

capacitors should be located as close as possible to the package

pins. It is recommended that the exposed paddle on the bottom

of the package be soldered to a large pad, with multiple vias

connecting the pad to the ground plane.

All the supply pins must be decoupled to ground with good

quality, high frequency chip capacitors. There should also be a

4.7 µF or larger bypass capacitor for each main supply—AVDD,

RGVDD, HVDD, and DRVDD—although this is not necessary

for each individual pin. In most applications, it is easier to share

the supply for RGVDD and HVDD, which may be done as long

as the individual supply pins are separately bypassed. A separate

3 V supply may be used for DRVDD, but this supply pin should

still be decoupled to the same ground plane as the rest of the

chip. A separate ground for DRVSS is not recommended.

The reference bypass pins (REFT, REFB) should be decoupled

to ground as close as possible to their respective pins. The

analog input (CCDIN) capacitor should also be located close to

the pin.

3V ANALOG SUPPLY

SERIAL

INTERFACE

CCD SIGNAL

VD/HD/HBLK INPUTS

CLP/BLK OUTPUT

DRIVER

UPPLY

RG DRIVER

SUPPLY

H DRIVER

SUPPLY

MASTER

CLOCK INPUT

3V ANALOG

SUPPLY

DATA

OUTPUTS

H1 TO H4

TOP VIEW

AD9949

PIN 1

IDENTIFIER

REFB

REFT

AVSS

CCDIN

AVDD

CLI

TCVDD

TCVSS

RGVDD

DRVDD

D0 (LSB)

CLP/PBLK

HBLK

DVDD

DVSS

SCK

SDI

D10

(MSB) D11

HVSS

HVDD

RGVSS

RG OUTPUT

DRVSS

4.7µF 0.1µF

0.1µF 4.7µF

4.7µF

0.1µF

0.1µF4.7µF

0.1µF

1µF

0.1µF

03751-039

Figure 38. Recommended Circuit Configuration

AD9949

Rev. B | Page 31 of 36

DRIVING THE CLI INPUT

The AD9949’s master clock input (CLI) may be used in two

different configurations, depending on the application.

Figure 41 shows a typical dc-coupled input from the master

clock source. When the dc-coupled technique is used, the

master clock signal should be at standard 3 V CMOS logic

levels. As shown in Figure 42, a 1000 pF ac-coupling capacitor

may be used between the clock source and the CLI input. In this

configuration, the CLI input is self-biased to the proper dc volt-

age level of approximately 1.4 V. When the ac-coupled tech-

nique is used, the master clock signal can be as low as ±500 mV

in amplitude.

CCD IMAGER

SIGNAL

OUT

H2 RGH3 H4 H1

H2H1 RG

AD9949

CCDIN

03751-040

18 19 14 15 21

Figure 39. CCD Connections (2 H-Clock)

03751-041

CCD IMAGER

SIGNAL

OUT

H4 RGH1 H2 H3

H2 H1

H3 RG

AD9949

CCDIN

14 15 18 19 21

Figure 40. CCD Connections (4 H-Clock)

03751-042

CLI

AD9949

ASIC

MASTER CLOCK

Figure 41. CLI Connection, DC-Coupled

LPF

1nF

03751-043

CLI

AD9949

ASIC

MASTER CLOCK

Figure 42. CLI Connection, AC-Coupled

HORIZONTAL TIMING SEQUENCE EXAMPLE

Figure 43 shows an example CCD layout. The horizontal

clocked from the CCD. In the vertical direction, there are

10 optical black (OB) lines at the front of the readout and two at

the back of the readout. The horizontal direction has four OB

pixels in the front and 48 in the back.

To configure the AD9949 horizontal signals for this CCD, three

sequences can be used. Figure 44 shows the first sequence that

should be used during vertical blanking. During this time, there

are no valid OB pixels from the sensor, so the CLPOB signal is

not used. PBLK may be enabled during this time, because no

valid data is available.

Figure 45 shows the recommended sequence for the vertical OB

interval. The clamp signals are used across the whole lines in

order to stabilize the clamp loop of the AD9949.

Figure 46 shows the recommended sequence for the effective

pixel readout. The 48 OB pixels at the end of each line are used

for the CLPOB signal.

AD9949

Rev. B | Page 32 of 36

USE SEQUENCE 2

USE SEQUENCE 3

SEQUENCE 2 (OPTIONAL)

HORIZONTAL CCD REGISTER

EFFECTIVE IMAGE AREA

8 DUMMY PIXELS

48 OB PIXELS

4 OB PIXELS

10 VERTICAL OB LINES

2 VERTICAL OB LINES

03751-044

Figure 43. Example CCD Configuration

VERTICAL SHIFT VERT SHIFT

SEQUENCE 1: VERTICAL BLANKING

CCDIN

SHP

SHD

H1/H3

H2/H4

HBLK

PBLK

CLPOB

DUMMY INVALID PIXELSINVALID PIX

03751-045

Figure 44. Horizontal Sequence During Vertical Blanking

VERTICAL SHIFT VERT SHIFT

SEQUENCE 2: VERTICAL OPTICAL BLACK LINES

CCDIN

SHP

SHD

H1/H3

H2/H4

HBLK

PBLK

CLPOB

OPTICAL

BLACK

DUMMY OPTICAL BLACK

03751-046

Figure 45. Horizontal Sequences During Vertical Optical Black Pixels

AD9949

Rev. B | Page 33 of 36

VERTICAL SHIFT VERT SHIFT

SEQUENCE 3: EFFECTIVE PIXEL LINES

CCDIN

SHP

SHD

H1/H3

H2/H4

HBLK

PBLK

LPOB

OPTICAL

BLACK

DUMMY EFFECTIVE PIXELS

OPTICAL BLACK

03751-047

Figure 46. Horizontal Sequences During Effective Pixels

AD9949

Rev. B | Page 34 of 36

OUTLINE DIMENSIONS

4.25

4.10 SQ

3.95

TOP

VIEW

6.00

BSC SQ

PIN 1

INDICATOR 5.75

BCS SQ

12° MAX

0.30

0.23

0.18 0.20 REF

SEATING

PLANE

1.00

0.85

0.80

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.80 MAX

0.65 TYP

4.50

REF

0.50

0.40

0.30

0.50

BSC

PIN 1

INDICATOR

0.60 MAX

0.25 MIN

EXPOSED

PAD

(BOTTOM VIEW)

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm Body

(CP-40)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9949KCP −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40

AD9949KCPRL −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40

AD9949KCPZ1 −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40

AD9949KCPZRL1 −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40

AD9949AKCPZ1, 2 −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40

AD9949AKCPZRL1, 2 −20°C to +85°C 40-Lead Lead Frame Chip Scale Package (LFCSP) CP-40

1 Z = PB-free part.

2 The AD9949A is recommended for new designs and supports CCD line lengths > 4096 pixels.

AD9949

Rev. B | Page 35 of 36

NOTES

AD9949

Rev. B | Page 36 of 36

NOTES

tered trademarks are the property of their respective owners.

D03751–0–11/04(B)