1
2
3
4
ENA
INA
GND
INB
8
7
6
5
ENB
OUTA
VDD
OUTB
UCC27524A-Q1
Dual Non-Inverting Inputs
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UCC27524A-Q1
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UCC27524A-Q1 Dual 5-A, High-Speed, Low-Side Gate Driver
With Negative Input Voltage Capability
1 Features 3 Description
The UCC27524A-Q1 device is a dual-channel, high-
1• Qualified for Automotive Applications speed, low-side, gate-driver device capable of
• AEC-Q100 Qualified With the Following Results effectively driving MOSFET and IGBT power
– Device Temperature Grade 1 switches. The UCC27524A-Q1 device is a variant of
the UCC2752x family. The UCC27524A-Q1 device
– Device HBM ESD Classification Level H2 adds the ability to handle –5 V directly at the input
– Device CDM ESD Classification Level C4B pins for increased robustness. The UCC27524A-Q1
• Industry-Standard Pin Out device is a dual, non-inverting driver. Using a design
that inherently minimizes shoot-through current, the
• Two Independent Gate-Drive Channels UCC27524A-Q1 device is capable of delivering high-
• 5-A Peak Source and Sink-Drive Current peak current pulses of up to 5-A source and 5-A sink
• Independent Enable Function for Each Output into capacitive loads along with rail-to-rail drive
• TTL and CMOS-Compatible Logic Threshold capability and extremely small propagation delay
(typically 13 ns). In addition, the drivers feature
Independent of Supply Voltage matched, internal-propagation delays between the
• Hysteretic-Logic Thresholds for High-Noise two channels which are very well suited for
Immunity applications requiring dual-gate drives with critical
• Ability to Handle Negative Voltages (–5 V) at timing, such as synchronous rectifiers. This also
Inputs enables connecting two channels in parallel to
effectively increase current-drive capability or driving
• Inputs and Enable Pin-Voltage Levels Not two switches in parallel with a single input signal. The
Restricted by VDD Pin Bias Supply Voltage input pin thresholds are based on TTL and CMOS
• 4.5-V to 18-V Single-Supply Range compatible low-voltage logic, which is fixed and
• Outputs Held Low During VDD-UVLO, (ensures independent of the VDD supply voltage. Wide
glitch-free operation at power-up and power- hysteresis between the high and low thresholds offers
down) excellent noise immunity.
• Fast Propagation Delays (13-ns typical) Device Information(1)
• Fast Rise and Fall Times (7-ns and 6-ns typical) PART NUMBER PACKAGE BODY SIZE (NOM)
• 1-ns Typical Delay Matching Between 2-Channels SOIC (8) 4.90 mm × 3.91 mm
UCC27524A-Q1
• Ability to Parallel Two Outputs for High-Drive MSOP-PowerPAD (8) 3.00 mm × 3.00 mm
Current (1) For all available packages, see the orderable addendum at
• Outputs Held in LOW When Inputs are Floating the end of the data sheet.
• SOIC-8 and MSOP-8 PowerPad™ Package Product Matrix
Options
• Operating Temperature Range of –40°C to 140°C
2 Applications
• Automotive
• Switch-Mode Power Supplies
• DC-to-DC Converters
• Motor Control, Solar Power
• Gate Drive for Emerging Wide Band-Gap Power
Devices such as GaN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27524A-Q1
SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................. 12
1 Features.................................................................. 18.4 Device Functional Modes........................................ 17
2 Applications ........................................................... 19 Application and Implementation ........................ 18
3 Description............................................................. 19.1 Application Information............................................ 18
4 Revision History..................................................... 29.2 Typical Application.................................................. 18
5 Description (continued)......................................... 310 Power Supply Recommendations ..................... 22
6 Pin Configuration and Functions......................... 411 Layout................................................................... 23
7 Specifications......................................................... 511.1 Layout Guidelines ................................................. 23
7.1 Absolute Maximum Ratings ...................................... 511.2 Layout Example .................................................... 24
7.2 ESD Ratings ............................................................ 511.3 Thermal Considerations........................................ 24
7.3 Recommended Operating Conditions....................... 512 Device and Documentation Support................. 25
7.4 Thermal Information.................................................. 512.1 Community Resources.......................................... 25
7.5 Electrical Characteristics........................................... 612.2 Trademarks........................................................... 25
7.6 Switching Characteristics.......................................... 612.3 Electrostatic Discharge Caution............................ 25
7.7 Typical Characteristics.............................................. 812.4 Glossary................................................................ 25
8 Detailed Description............................................ 11 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 11 Information........................................................... 25
8.2 Functional Block Diagram....................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2014) to Revision B Page
• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Original (November 2013) to Revision A Page
• Changed document status from Product Preview to Production Data................................................................................... 1
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5 Description (continued)
For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device
ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features
enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are
internally pulled up to VDD for active-high logic and are left open for standard operation.
The UCC27524A-Q1 devices is available in SOIC-8 (D) and MSOP-PowerPAD-8 with exposed pad (DGN)
packages.
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1
2
3
4
ENA
INA
GND
INB
8
7
6
5
ENB
OUTA
VDD
OUTB
UCC27524A-Q1
SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
www.ti.com
6 Pin Configuration and Functions
D and DGN Packages
8-Pin SOIC and MSOP-PowerPAD
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
Enable input for Channel A: ENA is biased LOW to disable the Channel A output regardless of the INA state.
ENA 1 I ENA is biased HIGH or left floating to enable the Channel A output. ENA is allowed to float; hence the pin-
to-pin compatibility with the UCC2732X N/C pin.
Enable input for Channel B: ENB is biased LOW to disables the Channel B output regardless of the INB
ENB 8 I state. ENB is biased HIGH or left floating to enable Channel B output. ENB is allowed to float hence; the pin-
to-pin compatibility with the UCC2752A N/C pin.
GND 3 - Ground: All signals are referenced to this pin.
Input to Channel A: INA is the non-inverting input in the UCC27524A-Q1 device. OUTA is held LOW if INA is
INA 2 I unbiased or floating.
Input to Channel B: INB is the non-inverting input in the UCC27524A-Q1 device. OUTB is held LOW if INB is
INB 4 I unbiased or floating.
OUTA 7 O Output of Channel A
OUTB 5 O Output of Channel B
VDD 6 I Bias supply input
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VDD –0.3 20 V
DC –0.3 VDD + 0.3 V
OUTA, OUTB voltage Repetitive pulse < 200 ns(2) –2 VDD + 0.3 V
Output continuous source/sink current IOUT_DC 0.3 A
Output pulsed source/sink current (0.5 µs) IOUT_pulsed 5 A
INA, INB, ENA, ENB voltage(3) –5 20 V
Operating virtual junction temperature, TJ–40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Values are verified by characterization on bench.
(3) The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Supply voltage, VDD 4.5 12 18 V
Operating junction temperature –40 140 °C
Input voltage, INA, INB –2 18 V
Enable voltage, ENA and ENB –2 18 V
7.4 Thermal Information UCC27524A-Q1 UCC27524A-Q1
THERMAL METRIC(1) SOIC (D) HVSSOP (DGN) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 130.9 71.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 80 65.6 °C/W
RθJB Junction-to-board thermal resistance 71.4 7.4 °C/W
ψJT Junction-to-top characterization parameter 21.9 7.4 °C/W
ψJB Junction-to-board characterization parameter 70.9 31.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 19.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VDD = 12 V, TA= TJ= –40 °C to 140 °C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal (unless otherwise noted,)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
Startup current, VDD = 3.4 V, INA = VDD, INB = VDD 55 110 175
IDD(off) (based on UCC27524 Input μA
VDD = 3.4 V, INA = GND, INB = GND 25 75 145
configuration)
UNDER VOLTAGE LOCKOUT (UVLO)
TJ= 25 °C 3.91 4.2 4.5
VON Supply start threshold V
TJ= –40 °C to 140 °C 3.7 4.2 4.65
Minimum operating voltage
VOFF 3.4 3.9 4.4 V
after supply start
VDD_H Supply voltage hysteresis 0.2 0.3 0.5 V
INPUTS (INA, INB, INA+, INA–, INB+, INB–), UCC27524A-Q1 (D, DGN)
Output high for non-inverting input pins
VIN_H Input signal high threshold 1.9 2.1 2.3 V
Output low for inverting input pins
Output low for non-inverting input pins
VIN_L Input signal low threshold 1 1.2 1.4 V
Output high for inverting input pins
VIN_HYS Input hysteresis 0.7 0.9 1.1 V
OUTPUTS (OUTA, OUTB)
ISNK/SRC Sink/source peak current(1) CLOAD = 0.22 µF, FSW = 1 kHz ±5 A
VDD-VOH High output voltage IOUT = –10 mA 0.075 V
VOL Low output voltage IOUT = 10 mA 0.01 V
ROH Output pullup resistance(2) IOUT = –10 mA 2.5 5 7.5 Ω
ROL Output pulldown resistance IOUT = 10 mA 0.15 0.5 1 Ω
(1) Ensured by design.
(2) ROH represents on-resistance of only the P-Channel MOSFET device in the pullup structure of the UCC27524A-Q1 output stage.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRRise time(1) CLOAD = 1.8 nF 7 18 ns
tFFall time(1) CLOAD = 1.8 nF 6 10 ns
INA = INB, OUTA and OUTB at 50%
tMDelay matching between 2 channels 1 4 ns
transition point
Minimum input pulse width that
tPW 15 25 ns
changes the output state
tD1, tD2 Input to output propagation delay(1) CLOAD = 1.8 nF, 5-V input pulse 6 13 23 ns
tD3, tD4 EN to output propagation delay(1) CLOAD = 1.8 nF, 5-V enable pulse 6 13 23 ns
(1) See the timing diagrams in Figure 1 and Figure 2
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10%
90%
Enable
Output
Low
High
Low
High
Input
tD1 tD2 UDG-11219
10%
90%
Enable
Output
Low
High
Low
High
Input
tD3 tD4 UDG-11217
UCC27524A-Q1
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
Figure 1. Enable Function
Figure 2. Input-Output Operation
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0.5
1
1.5
2
2.5
−50 0 50 100 150
Temperature (°C)
Input Threshold (V)
Input High Threshold
Input Low Threshold
VDD = 12 V
G004
0.5
1
1.5
2
2.5
−50 0 50 100 150
Temperature (°C)
Enable Threshold (V)
Enable High Threshold
Enable Low Threshold
VDD = 12 V
G005
0.2
0.3
0.4
0.5
0.6
−50 0 50 100 150
Temperature (°C)
Supply Current (mA)
Input=GND
Input=VDD
Enable=12 V
VDD = 12 V
G012
3
3.5
4
4.5
5
−50 0 50 100 150
Temperature (°C)
UVLO Threshold (V)
UVLO Rising
UVLO Falling
G003
0.06
0.08
0.1
0.12
0.14
−50 0 50 100 150
Temperature (°C)
Startup Current (mA)
Input=VDD
Input=GND
VDD=3.4V
G001
2.5
3
3.5
4
−50 0 50 100 150
Temperature (°C)
Operating Supply Current (mA)
VDD = 12 V
fSW = 500 kHz
CL = 500 pF
G002
UCC27524A-Q1
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7.7 Typical Characteristics
Figure 3. Start-Up Current vs Temperature Figure 4. Operating Supply Current vs Temperature
(Outputs Switching)
Figure 5. Supply Current vs Temperature (Outputs In DC Figure 6. UVLO Threshold vs Temperature
On/Off Condition)
Figure 7. Input Threshold vs Temperature Figure 8. Enable Threshold vs Temperature
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8
10
12
14
16
18
−50 0 50 100 150
Temperature (°C)
Input to Output Propagation Delay (ns)
Turn−on
Turn−off
VDD = 12 V
CLOAD = 1.8 nF
G010
8
10
12
14
16
18
−50 0 50 100 150
Temperature (°C)
EN to Output Propagation Delay (ns)
EN to Output High
EN to Output Low
VDD = 12 V
CLOAD = 1.8 nF
G011
5
6
7
8
9
10
−50 0 50 100 150
Temperature (°C)
Rise Time (ns)
VDD = 12 V
CLOAD = 1.8 nF
G008
5
6
7
8
9
−50 0 50 100 150
Temperature (°C)
Fall Time (ns)
VDD = 12 V
CLOAD = 1.8 nF
G009
3
4
5
6
7
−50 0 50 100 150
Temperature (°C)
Output Pull−up Resistance (Ω)
VDD = 12 V
IOUT = −10 mA
G006
0.2
0.4
0.6
0.8
1
−50 0 50 100 150
Temperature (°C)
Output Pull−down Resistance (Ω)
VDD = 12 V
IOUT = 10 mA
G007
UCC27524A-Q1
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Figure 9. Output Pullup Resistance vs Temperature Figure 10. Output Pulldown Resistance vs Temperature
Figure 11. Rise Time vs Temperature Figure 12. Fall Time vs Temperature
Figure 13. Input to Output Propagation Delay vs Figure 14. En to Output Propagation Delay vs Temperature
Temperature
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0.5
1
1.5
2
2.5
−50 0 50 100 150
Temperature (°C)
Enable Threshold (V)
Enable High Threshold
Enable Low Threshold VDD = 4.5 V
G017
6
10
14
18
4 8 12 16 20
Supply Voltage (V)
Rise Time (ns)
CLOAD = 1.8 nF
G015
4
6
8
10
4 8 12 16 20
Supply Voltage (V)
Fall Time (ns)
CLOAD = 1.8 nF
G016
0
10
20
30
40
50
60
0 100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
Operating Supply Current (mA)
VDD = 4.5 V
VDD = 12 V
VDD = 15 V
CLOAD = 1.8 nF
Both channels switching
G013
6
10
14
18
22
4 8 12 16 20
Supply Voltage (V)
Propagation Delays (ns)
Input to Output On delay
Input to Ouptut Off Delay
EN to Output On Delay
EN to Output Off Delay
CLOAD = 1.8 nF
G014
UCC27524A-Q1
SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
Figure 15. Operating Supply Current vs Frequency Figure 16. Propagation Delays vs Supply Voltage
Figure 17. Rise Time vs Supply Voltage Figure 18. Fall Time vs Supply Voltage
Figure 19. Enable Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The UCC27524A-Q1 device represents Texas Instruments’ latest generation of dual-channel, low-side, high-
speed, gate-driver devices featuring a 5-A source and sink current capability, industry best-in-class switching
characteristics, and a host of other features listed in Table 1 all of which combine to ensure efficient, robust and
reliable operation in high-frequency switching power circuits.
Table 1. UCC27524A-Q1 Features and Benefits
FEATURE BENEFIT
Best-in-class 13-ns (typ) propagation delay Extremely low-pulse transmission distortion
Ease of paralleling outputs for higher (2 times) current capability,
1-ns (typ) delay matching between channels ease of driving parallel-power switches
Expanded VDD Operating range of 4.5 to 18 V Flexibility in system design
Expanded operating temperature range of –40 °C to +140 °C Flexibility in system design
(See Electrical Characteristics table) Outputs are held Low in UVLO condition, which ensures predictable,
VDD UVLO Protection glitch-free operation at power-up and power-down
Protection feature, especially useful in passing abnormal condition
Outputs held Low when input pins (INx) in floating condition tests during safety certification
Pin-to-pin compatibility with the UCC27324 device from Texas
Outputs enable when enable pins (ENx) in floating condition Instruments, in designs where Pin 1 and Pin 8 are in floating
condition
Enhanced noise immunity, while retaining compatibility with
CMOS/TTL compatible input and enable threshold with wide microcontroller logic-level input signals (3.3 V, 5 V) optimized for
hysteresis digital power
Ability of input and enable pins to handle voltage levels not restricted System simplification, especially related to auxiliary bias supply
by VDD pin bias voltage architecture
Ability to handle –5 VDC (max) at input pins Increased robustness in noisy environments
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1ENA
200 kW
VDD
2
INA
400 kW
3GND
4
INB
400 kW
UVLO
VDD
VDD
VDD
8
7
6
5
ENB
OUTA
VDD
OUTB
200 kW
VDD
VDD
UCC27524A-Q1
SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
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8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Operating Supply Current
The UCC27524A-Q1 devices feature very low quiescent IDD currents. The typical operating-supply current in
UVLO state and fully-on state (under static and switching conditions) are summarized in Figure 3,Figure 4 and
Figure 5. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, see
Figure 4) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully
operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current because of
switching, and finally any current related to pullup resistors on the enable pins (see Functional Block Diagram).
Knowing the operating frequency (fSW) and the MOSFET gate (QG) charge at the drive voltage being used, the
average IOUT current can be calculated as product of QGand fSW.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages
under 1.8-nF switching load in both channels is provided in Figure 15. The strikingly linear variation and close
correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device
attesting to its high-speed characteristics.
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Feature Description (continued)
8.3.2 Input Stage
The input pins of the UCC27524A-Q1 gate-driver devices are based on a TTL and CMOS compatible input-
threshold logic that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically
low threshold = 1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from
3.3-V and 5-V digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity
compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V.
UCC27524A-Q1 devices also feature tight control of the input pin threshold voltage levels which eases system
design considerations and ensures stable operation across temperature (refer to Figure 7). The very low input
capacitance on these pins reduces loading and increases switching speed.
The UCC27524A-Q1 device features an important protection feature that holds the output of a channel when the
respective pin is in a floating condition. This is achieved using GND pulldown resistors on all of the non-inverting
input pins (INA, INB), as shown in the device block diagrams.
The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in
typical power supply applications, where the input signals are provided by a PWM controller or logic gates with
fast transition times (<200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly
at a high frequency. While the wide hysteresis offered in UCC27524A-Q1 definitely alleviates this concern over
most other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or
fall times to the power device is the primary goal, then an external resistance is highly recommended between
the output of the driver and the power device. This external resistor has the additional benefit of reducing part of
the gate-charge related power dissipation in the gate driver device package and transferring it into the external
resistor itself.
8.3.3 Enable Function
The enable function is an extremely beneficial feature in gate-driver devices, especially for certain applications
such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative
current circulation and to improve light-load efficiency.
The UCC27524A-Q1 device is equipped with independent enable pins (ENx) for exclusive control of each driver-
channel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus
when ENx pins are driven high, the drivers are enabled and when ENx pins are driven low, the drivers are
disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible, input-threshold
logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5-
V microcontrollers. The UCC27524A-Q1 devices also feature tight control of the enable-function threshold-
voltage levels which eases system design considerations and ensures stable operation across temperature (refer
to Figure 8). The ENx pins are internally pulled up to VDD using pullup resistors as a result of which the outputs
of the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for
standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27524A-Q1
device to be pin-to-pin compatible with TI’s previous generation of drivers (UCC27323, UCC27324, and
UCC27325 respectively), where Pin 1 and Pin 8 are N/C pins. If the channel A and Channel B inputs and outputs
are connected in parallel to increase the driver current capacity, ENA and ENB are connected and driven
together.
8.3.4 Output Stage
The UCC27524A-Q1 device output stage features a unique architecture on the pullup structure which delivers
the highest peak-source current when it is most needed during the Miller plateau region of the power-switch
turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup
structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the
N-Channel MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is
accomplished by briefly turning-on the N-Channel MOSFET during a narrow instant when the output is changing
state from Low to High.
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VCC
ROH
ROL
Gate
Voltage
Boost
Narrow Pulse at
each Turn On
Anti Shoot-
Through
Circuitry
Input Signal
RNMOS, Pull Up
OUT
UCC27524A-Q1
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Feature Description (continued)
Figure 20. UCC27524A-Q1 Gate Driver Output Structure
The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the on-
resistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC
condition and is turned-on only for a narrow instant when output changes state from low to high. Note that
effective resistance of the UCC27524A-Q1 pullup stage during the turnon instant is much lower than what is
represented by ROH parameter.
The pulldown structure in the UCC27524A-Q1 device is simply composed of a N-Channel MOSFET. The ROL
parameter (see Electrical Characteristics), which is also a DC measurement, is representative of the impedance
of the pulldown stage in the device. In the UCC27524A-Q1 device, the effective resistance of the hybrid pullup
structure during turnon is estimated to be approximately 1.5 × ROL, estimated based on design considerations.
Each output stage in the UCC27524A-Q1 device is capable of supplying 5-A peak source and 5-A peak sink
current pulses. The output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the
MOS-output stage which delivers very low drop-out. The presence of the MOSFET-body diodes also offers low
impedance to switching overshoots and undershoots which means that in many cases, external Schottky-diode
clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current
without either damage to the device or logic malfunction.
The UCC27524A-Q1 device is particularly suited for dual-polarity, symmetrical drive-gate transformer
applications where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being
driven complementary to each other. This situation is because of the extremely low drop-out offered by the MOS
output stage of these devices, both during high (VOH) and low (VOL) states along with the low impedance of the
driver output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux
imbalance. The low propagation delays also ensure accurate reset for high-frequency applications.
For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often
occurs in synchronous rectifier applications because the body diode is generally conducting before power
MOSFET is switched on.
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Product Folder Links: UCC27524A-Q1
1ENA
200 kW
VDD
2
INA
400 kW
3GND
4
INB
400 kW
UVLO
VDD
VDD
VDD
8
7
6
5
ENB
OUTA
VDD
OUTB
200 kW
VDD
VDD
ISHOOT-THROUGH
VIN_H
(Channel B)
VIN_H
(Channel A)
Slow Input Signal
UCC27524A-Q1
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
Feature Description (continued)
8.3.5 Low Propagation Delays And Tightly Matched Outputs
The UCC27524A-Q1 driver device features a best in class, 13-ns (typical) propagation delay between input and
output which goes to offer the lowest level of pulse-transmission distortion available in the industry for high
frequency switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven
with very low distortion when a single driver device is used to drive both the SR MOSFETs. Further, the driver
devices also feature an extremely accurate, 1-ns (typical) matched internal-propagation delays between the two
channels which is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC
application, a pair of paralleled MOSFETs can be driven independently using each output channel, which the
inputs of both channels are driven by a common control signal from the PFC controller device. In this case the 1-
ns delay matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum
of turnon delay difference. Yet another benefit of the tight matching between the two channels is that the two
channels are connected together to effectively increase current drive capability, for example A and B channels
may be combined into a single driver by connecting the INA and INB inputs together and the OUTA and OUTB
outputs together. Then, a single signal controls the paralleled combination.
Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the
possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current
conduction as shown in Figure 21. While the two channels are inherently very well matched (4-ns Max
propagation delay), note that there may be differences in the input threshold voltage level between the two
channels which causes the delay between the two outputs especially when slow dV/dt input signals are
employed. The following guidelines are recommended whenever the two driver channels are paralleled using
direct connections between OUTA and OUTB along with INA and INB:
• Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences
in input thresholds causing delays between the channels.
• INA and INB connections must be made as close to the device pins as possible.
Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with
OUTA and OUTB. This allows the option to use 0-Ωresistors for paralleling outputs directly or to add appropriate
series resistances to limit shoot-through current, should it become necessary.
Figure 21. Slow Input Signal Can Cause Shoot-Through Between Channels During Paralleling
(Recommended DV/DT is 20 V/Μs or Higher)
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
www.ti.com
Feature Description (continued)
Figure 22. Turnon Propagation Delay Figure 23. Turnon Rise Time
(CL= 1.8 nF, VDD = 12 V) (CL= 1.8 nF, VDD = 12 V)
Figure 24. . Turnoff Propagation Delay Figure 25. Turnoff Fall Time
(CL= 1.8 nF, VDD = 12 V) (CL= 1.8 nF, VDD = 12 V)
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UCC27524A-Q1
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
8.4 Device Functional Modes
Table 2. Device Logic Table
UCC27524A-Q1
ENA ENB INA INB OUTA OUTB
H H L L L L
H H L H L H
H H H L H L
HHHHHH
L L Any Any L L
Any Any x(1) x(1) L L
x(1) x(1) LLLL
x(1) x(1) L H L H
x(1) x(1) H L H L
x(1) x(1) HHHH
(1) Floating condition.
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Product Folder Links: UCC27524A-Q1
1
2
3
4
ENA
INA
GND
INB
8
7
6
5
ENB
OUTA
VDD
OUTB
GND
GND
GND
V+
INB
INA
ENA
ENB
UCC27524A-Q1
UCC27524A-Q1
SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to
effect the fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver
device employs between the PWM output of control devices and the gates of the power semiconductor devices.
Further, gate-driver devices are indispensable when it is not feasible for the PWM controller device to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which is not capable of effectively
turning on a power switch. A level-shifting circuitry is required to boost the 3.3-V signal to the gate-drive voltage
(such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer-drive
circuits based on NPN/PNP bipolar transistors in a totem-pole arrangement, as emitter-follower configurations,
prove inadequate with digital power because the traditional buffer-drive circuits lack level-shifting capability.
Gate-driver devices effectively combine both the level-shifting and buffer-drive functions. Gate-driver devices also
find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current
driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device
gates, reducing power dissipation and thermal stress in controller devices by moving gate-charge power losses
into the controller. Finally, emerging wide band-gap power-device technologies such as GaN based switches,
which are capable of supporting very high switching frequency operation, are driving special requirements in
terms of gate-drive capability. These requirements include operation at low VDD voltages (5 V or lower), low
propagation delays, tight delay matching and availability in compact, low-inductance packages with good thermal
capability. In summary, gate-driver devices are an extremely important component in switching power combining
benefits of high-performance, low-cost, component-count, board-space reduction, and simplified system design.
9.2 Typical Application
Figure 26. UCC27524A-Q1 Typical Application Diagram
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VDD
EN
IN
OUT
VDD Threshold
UDG-11228
UCC27524A-Q1
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
Typical Application (continued)
9.2.1 Design Requirements
When selecting the proper gate driver device for an end application, some desiring considerations must be
evaluated first in order to make the most appropriate selection. Among these considerations are VDD, UVLO,
Drive current and power dissipation.
9.2.2 Detailed Design Procedure
9.2.2.1 VDD and Undervoltage Lockout
The UCC27524A-Q1 device has an internal undervoltage-lockout (UVLO) protection feature on the VDD pin
supply circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output
low, regardless of the status of the inputs. The UVLO is typically 4.25 V with 350-mV typical hysteresis. This
hysteresis prevents chatter when low VDD supply voltages have noise from the power supply and also when
there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase
in IDD. The capability to operate at low voltage levels such as below 5 V, along with best in class switching
characteristics, is especially suited for driving emerging GaN power semiconductor devices.
For example, at power up, the UCC27524A-Q1 driver-device output remains low until the VDD voltage reaches
the UVLO threshold if enable pin is active or floating. The magnitude of the OUT signal rises with VDD until
steady-state VDD is reached. The operation in Figure 27 shows that the output remains low until the UVLO
threshold is reached, and then the output is in-phase with the input.
Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface
mount components is highly recommended. A 0.1-μF ceramic capacitor must be located as close as possible to
the VDD to GND pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low
ESR must be connected in parallel and close proximity, in order to help deliver the high-current peaks required
by the load. The parallel combination of capacitors presents a low impedance characteristic for the expected
current levels and switching frequencies in the application.
Figure 27. Power-Up Non-Inverting Driver
9.2.2.2 Drive Current and Power Dissipation
The UCC27524A-Q1 driver is capable of delivering 5-A of current to a MOSFET gate for a period of several-
hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON quickly. Then, to turn
the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the
operating frequency of the power device. The power dissipated in the gate driver device package depends on the
following factors:
• Gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close
to input bias supply voltage VDD due to low VOH drop-out)
• Switching frequency
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2
G LOAD DD
1
E C V
2
=
UCC27524A-Q1
SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
• Use of external gate resistors
Because UCC27524A-Q1 features very low quiescent currents and internal logic to eliminate any shoot-through
in the output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be
negligible.
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias
supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given
by Equation 1.
where
• CLOAD is the load capacitor
• VDD2is the bias voltage feeding the driver (1)
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G
DD
DD
P0.432 W
I ~ 0.036 A
V 12 V
= =
Q
P 0.6 mA 12 V 7.2mW= ´ =
Q DD DD
P I V=
OFF ON
SW G SW
OFF GATE ON GATE
R R
P 0.5 Q VDD f
R R R R
æ ö
= ´ ´ ´ ´ +
ç ÷
+ +
è ø
G
P 2 x 60 nC 12 V 300kHz 0.432 W= ´ ´ =
2
G LOAD DD SW g DD SW
P C V f Q V f= =
2
G
P 10nF 12 V 300kHz 0.432 W= ´ ´ =
2
G LOAD DD SW
P C V f=
UCC27524A-Q1
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SLVSCC1B –NOVEMBER 2013–REVISED SEPTEMBER 2015
Typical Application (continued)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by Equation 2.
where
• fSW is the switching frequency (2)
With VDD = 12 V, CLOAD = 10 nF and fSW = 300 kHz the power loss is calculated with Equation 3.
(3)
The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to
switch the device under specified conditions. Using the gate charge Qg, the power that must be dissipated when
charging a capacitor is determined which by using the equivalence Qg= CLOADVDD to provide Equation 4 for
power:
(4)
Assuming that the UCC27524A-Q1 device is driving power MOSFET with 60 nC of gate charge (Qg= 60 nC at
VDD = 12 V) on each output, the gate charge related power loss is calculated with Equation 5.
(5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half
of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated
when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the
driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external
gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate
resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component).
Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see
Equation 6):
where
• ROFF = ROL
• RON (effective resistance of pullup structure) = 1.5 x ROL (6)
In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the
power associated with the quiescent bias current consumed by the device to bias all internal circuits such as
input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in Figure 4, the quiescent
current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated easily with
Equation 7.
(7)
Assuming , IDD = 6 mA, the power loss is:
(8)
Clearly, this power loss is insignificant compared to gate charge related power dissipation calculated earlier.
With a 12-V supply, the bias current<