© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 8 1Publication Order Number:
MC74VHC541/D
MC74VHC541
Octal Bus Buffer
The MC74VHC541 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC541 is a noninverting type. When either OE1 or
OE2 are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
•High Speed: tPD = 3.7ns (Typ) at VCC = 5.0 V
•Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
•High Noise Immunity: VNIH = VNIL = 28% VCC
•Power Down Protection Provided on Inputs
•Balanced Propagation Delays
•Designed for 2.0 V to 5.5 V Operating Range
•Low Noise: VOLP = 1.2 V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Latchup Performance Exceeds 300mA
•ESD Performance: HBM > 2000 V; Machine Model > 200 V
•Chip Complexity: 134 FETs or 33.5 Equivalent Gates
•These Devices are Pb−Free and are RoHS Compliant
18 Y1
2
A1
17 Y2
3
A2
16 Y3
4
A3
15 Y4
5
A4
14 Y5
6
A5
13 Y6
7
A6
12 Y7
8
A7
11 Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
NONINVERTING
OUTPUTS
Figure 1. Logic Diagram
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See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs Output Y
OE1 OE2 A
L
H
Z
Z
PIN ASSIGNMENT
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
VCC
Y8
Y7
Y6
Y5
Y4
TSSOP−20
SUFFIX DT
CASE 948E
SOIC−20WB
SUFFIX DW
CASE 751D
1
1
20
20
See general marking information in the device marking
section on page 4 of this data sheet.
DEVICE MARKING INFORMATION
MC74VHC541
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage – 0.5 to + 7.0 V
Vin DC Input Voltage – 0.5 to + 7.0 V
Vout DC Output Voltage – 0.5 to VCC + 0.5 V
IIK Input Diode Current − 20 mA
IOK Output Diode Current ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, SOIC Package†
TSSOP Package† 500
450 mW
Tstg Storage Temperature – 65 to + 150 _C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
Vin DC Input Voltage 0 5.5 V
Vout DC Output Voltage 0 VCC V
TAOperating Temperature, All Package Types −55 +125 _C
tr, tfInput Rise and Fall Time VCC = 3.3V ±0.3V
VCC = 5.0V ±0.5V 0
0100
20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions VCC
V
TA = 25°C TA = − 55 to 125°C
Uni
t
Min Typ Max Min Max
VIH Minimum High−Level Input
Voltage 2.0
3.0 to 5.5 1.50
VCC x 0.7 1.50
VCC x 0.7 V
VIL Maximum Low−Level Input
Voltage 2.0
3.0 to 5.5 0.50
VCC x 0.3 0.50
VCC x 0.3 V
VOH Minimum High−Level Output
Voltage Vin = VIH or VIL
IOH = − 50mA2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
Vin = VIH or VIL
IOH = − 4mA
IOH = − 8mA 3.0
4.5 2.58
3.94 2.48
3.80
VOL Maximum Low−Level Output
Voltage Vin = VIH or VIL
IOL = 50mA2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA 3.0
4.5 0.36
0.36 0.44
0.44
Iin Maximum Input Leakage
Current Vin = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 mA
IOZ Maximum 3−State Leakage
Current Vin = VIL or VIH
Vout = VCC or GND 5.5 ±0.25 ±2.5 mA
ICC Maximum Quiescent Supply
Current Vin = VCC or GND 5.5 4.0 40.0 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbo
l
Parameter Test Conditions
TA = 25°C TA = − 55 to 125°C
Uni
t
Min Typ Max Min Max
tPLH,
tPHL Maximum Propagation Delay,
A to Y VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF 5.0
7.5 7.0
10.5 1.0
1.0 8.5
12.0 ns
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF 3.5
5.0 5.0
7.0 1.0
1.0 6.0
8.0
tPZL,
tPZH Output Enable TIme,
OE to Y VCC = 3.3 ± 0.3V CL = 15pF
RL = 1kWCL = 50pF 6.8
9.3 10.5
14.0 1.0
1.0 12.5
16.0 ns
VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kWCL = 50pF 4.7
6.2 7.2
9.2 1.0
1.0 8.5
10.5
tPLZ,
tPHZ Output Disable Time,
OE to Y VCC = 3.3 ± 0.3V CL = 50pF
RL = 1kW
11.2 15.4 1.0 17.5 ns
VCC = 5.0 ± 0.5V CL = 50pF
RL = 1kW
6.0 8.8 1.0 10.0
tOSLH,
tOSHL Output to Output Skew VCC = 3.3 ± 0.3V CL = 50pF
(Note 1) 1.5 1.5 ns
VCC = 5.0 ± 0.5V CL = 50pF
(Note 1) 1.0 1.0 ns
Cin Maximum Input Capacitance 4 10 10 pF
Cout Maximum Three−State Output
Capacitance (Output in High
Impedance State)
6 pF
CPD Power Dissipation Capacitance (Note 2)
Typical @ 25°C, VCC = 5.0V
pF
18
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
Symbo
l
Parameter
TA = 25°C
Uni
t
Typ Max
VOLP Quiet Output Maximum Dynamic VOL 0.9 1.2 V
VOLV Quiet Output Minimum Dynamic VOL − 0.9 − 1.2 V
VIHD Minimum High Level Dynamic Input Voltage 3.5 V
VILD Maximum Low Level Dynamic Input Voltage 1.5 V
VCC
GND
A
Y
tPLH
OE1 or OE2 50%
VCC
GND
Y
tPZL
Y
tPZH
HIGH
IMPEDANCE
VOL +0.3V
VOH -0.3V
HIGH
IMPEDANCE
tPLZ
tPHZ
50% VCC
50% VCC
tPHL
50%
SWITCHING WAVEFORMS
50% VCC
50%
Figure 2. Figure 3.
MC74VHC541
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4
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 4.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT 1kWCONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
Figure 5.
Figure 6. Input Equivalent Circuit
INPUT
ORDERING INFORMATION
Device Package Shipping†
MC74VHC541DWR2G SOIC−20WB
(Pb−Free) 1000 / Tape & Reel
MC74VHC541DTG TSSOP−20
(Pb−Free) 75 Units / Rail
MC74VHC541DTR2G TSSOP−20
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
TSSOP−20SOIC−20WB
20
1
VHC541
AWLYYWWG
20
1
VHC
541
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
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5
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MC74VHC541
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6
PACKAGE DIMENSIONS
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC541/D
P
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