CDCLVC 1112
1
1G 2
GND
3
CLKIN
4
5
6
7
8
9
10
16
17
18
19
20
21
22
23
24 Y 1
Y 2
VDD
VDD
Y 3
Y4
VDD
GND
Y0
Y11
Y 5
GND
Y6 Y 7
Y9
VDD Y 8
GND
11
12 13
14
15
GND Y 10
VDD
CDCLVC 1106
CDCLVC 1110
CDCLVC 1102
CDCLVC 1103
CDCLVC 1104
CDCLVC 1108
Y0
Y1
Y2
Y3
Yn
CLKIN LV
CMOS
1G
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
•
•
•
CDCLVC11xx
www.ti.com
SCAS895 –MAY 2010
3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family
Check for Samples: CDCLVC11xx
1FEATURES • Operating Temperature Range: –40°C to 85°C
• High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, • Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP
1:12 LVCMOS Clock Buffer Family Package (all pin compatible)
• Very Low Pin-to-Pin Skew < 50 ps APPLICATIONS
• Very Low Additive Jitter < 100 fs • General Purpose Communication, Industrial
• Supply Voltage: 3.3 V or 2.5 V and Consumer Applications
• fmax = 250 MHz for 3.3 V
fmax = 180 MHz for 2.5 V
DESCRIPTION
The CDCLVC11xx is a modular, high-performance, low-skew, general purpose clock buffer family from Texas
Instruments.
The whole family is designed with a modular approach in mind. It is intended to round up TI's series of LVCMOS
clock generators.
There are 7 different fan-out variations, 1:2 to 1:12, available. All of the devices are pin compatible to each other
for easy handling.
All family members share the same high performing characteristics like low additive jitter, low skew, and wide
operating temperature range.
The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low
state when 1G is low. Also, versions with synchronized enable control for glitch free switching and three-state
outputs are planned in future device options.
The CDCLVC11xx operate in a 2.5 V and 3.3 V environment and are characterized for operation from –40°C to
85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCLVC1106
1
1 G 2
GND
3
CLKIN
4
5
6
7 8
9
10
11
12
13
14 Y 1
Y 2
VDD
VDD
Y 3
Y 4
VDD
GND
Y 0
Y 5
GND
CDCLVC1108
1
1 G 2
GND
3
CLKIN
4
5
6
7
8 9
10
11
12
13
14
15
16 Y 1
Y 2
VDD
VDD
Y 3
Y 4
VDD
GND
Y 0
Y 5
GND
Y 6 Y 7
CDCLVC 1110
1
1 G 2
GND
3
CLKIN
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20 Y 1
Y 2
VDD
VDD
Y 3
Y 4
VDD
GND
Y 0
Y 5
GND
Y 6 Y 7
Y 9
VDD Y 8
GND11
CDCLVC1102
1
1 G 2
GND
3
CLKIN
4 5
6
7
8 Y 1
NC
VDD
NC
Y 0
CDCLVC1104
1
1 G 2
GND
3
CLKIN
4 5
6
7
8 Y 1
Y 2
VDD
Y 3
Y 0
Y 1
Y 2
VDD
NC
CDCLVC1103
1
1 G 2
GND
3
CLKIN
4 5
6
7
8
Y 0
CDCLVC 1112
1
1 G 2
GND
3
CLKIN
4
5
6
7
8
9
10
16
17
18
19
20
21
22
23
24 Y 1
Y 2
VDD
VDD
Y 3
Y 4
VDD
GND
Y 0
Y 11
Y 5
GND
Y 6 Y 7
Y 9
VDD Y 8
GND
11
12 13
14
15
GND Y 10
VDD
CDCLVC11xx
SCAS895 –MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE OPTIONS
PIN FUNCTIONS
LVCMOS CLOCK OUTPUT SUPPLY
LVCMOS CLOCK OUTPUT GROUND
CLOCK INPUT ENABLE VOLTAGE
DEVICES CLKIN 1G Y0, Y1, … Y11 VDD GND
CDCLVC1102 1 2 3, 8 6 4
CDCLVC1103 1 2 3, 8, 5 6 4
CDCLVC1104 1 2 3, 8, 5, 7 6 4
CDCLVC1106 1 2 3, 14, 11, 13, 6, 9 5, 8, 12 4, 7, 10
CDCLVC1108 1 2 3, 16, 13, 15, 6, 11, 8, 9 5, 10, 14 4, 7, 12
CDCLVC1110 1 2 3, 20, 17, 19, 6, 15, 8, 13, 10 5, 9, 14, 18 4, 7, 11, 16
CDCLVC1112 1 2 3, 24, 21, 23, 6, 19, 8, 17, 16, 10, 14, 12 5, 9, 13, 18, 22 4, 7, 11, 15, 20
OUTPUT LOGIC TABLE
INPUTS OUTPUTS
CLKIN 1G Yn
X L L
L H L
HHH
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Product Folder Link(s): CDCLVC11xx
CDCLVC11xx
www.ti.com
SCAS895 –MAY 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE / UNIT
VDD Supply voltage range –0.5 V to 4.6 V
VIN Input voltage range (2) –0.5 V to VDD + 0.5 V
VOOutput voltage range (2) –0.5 V to VDD + 0.5 V
IIN Input current ±20 mA
IOContinuous output current ±50 mA
TJMaximum junction temperature 125°C
TST Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.
THERMAL INFORMATION DCDLVC1102/03/04 CDCLVC1106 CDCLVC1108 CDCLVC11010 CDCLVC1112
THERMAL METRIC(1) PW PW PW PW PW UNITS
8 PINS 14 PINS 16 PINS 20 PINS 24 PINS
qJA Junction-to-ambient thermal resistance(2) 149.4 112.6 108.4 83.0 87.9 °C/W
qJC(top) Junction-to-case(top) thermal resistance (3) 69.4 48.0 33.6 32.3 26.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
3.3 V supply 3.0 3.3 3.6
VDD Supply voltage range V
2.5 V supply 2.3 2.5 2.7
VDD = 3.0 V to 3.6 V VDD/2 – 600
VIL Low-level input voltage mV
VDD = 2.3 V to 2.7 V VDD/2 – 400
VDD = 3.0 V to 3.6 V VDD/2 + 600
VIH High-level input voltage mV
VDD = 2.3 V to 2.7 V VDD/2 + 400
Vth Input threshold voltage VDD = 2.3 V to 3.6 V VDD/2 mV
tr/ tfInput slew rate 1 4 V/ns
VDD = 3.0 V to 3.6 V 1.8
Minimum pulse width at
twns
CLKIN VDD = 2.3 V to 2.7 V 2.75
VDD = 3.0 V to 3.6 V DC 250
LVCMOS clock Input
fCLK MHz
Frequency VDD = 2.3 V to 2.7 V DC 180
TAOperating free-air temperature –40 85 °C
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): CDCLVC11xx
CDCLVC11xx
SCAS895 –MAY 2010
www.ti.com
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITION MIN TYP(1) MAX UNIT
OVERALL PARAMETERS FOR ALL VERSIONS
1G = VDD; CLKIN = 0 V or VDD; IO= 0 mA; VDD = 3.6 V 6 10 mA
IDD Static device current(2) 1G = VDD; CLKIN = 0 V or VDD; IO= 0 mA; VDD = 2.7 V 3 6 mA
IPD Power down current 1G = 0 V; CLKIN = 0 V or VDD; IO= 0 mA; VDD = 3.6 V or 2.7 V 60 µA
VDD = 3.3 V; f = 10 MHz 6 pF
Power dissipation capacitance
CPD per output(3) VDD = 2.5 V; f = 10 MHz 4.5 pF
Input leakage current at 1G ± 8
IIVI= 0 V or VDD, VDD = 3.6 V or 2.7 V µA
Input leakage current at CLKIN ± 25
VDD = 3.3 V 45 Ω
ROUT Output impedance VDD = 2.5 V 60 Ω
VDD = 3.0 V to 3.6 V DC 250 MHz
fOUT Output frequency VDD = 2.3 V to 2.7 V DC 180 MHz
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
VDD = 3 V, IOH = –0.1 mA 2.9
VOH High-level output voltage VDD = 3 V, IOH = –8 mA 2.5 V
VDD = 3 V, IOH = –12 mA 2.2
VDD = 3 V, IOL = 0.1 mA 0.1
VOL Low-level output voltage VDD = 3 V, IOL = 8 mA 0.5 V
VDD = 3 V, IOL = 12 mA 0.8
tPLH,Propagation delay CLKIN to Yn 0.8 2.0 ns
tPHL
tsk(o) Output skew Equal load of each output 50 ps
tr/tfRise and fall time 20%–80% (VOH - VOL) 0.3 0.8 ns
tDIS Output disable time 1G to Yn 6 ns
tEN Output enable time 1G to Yn 6 ns
Pulse skew ;
tsk(p) To be measured with input duty cycle of 50% 180 ps
tPLH(Yn) – tPHL(Yn) (4)
tsk(pp) Part-to-part skew Under equal operating conditions for two parts 0.5 ns
tjitter Additive jitter rms 12kHz…20 MHz, fOUT = 250 MHz 100 fs
(1) All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ωto VDD/2 (see Figure 1).
(2) For dynamic IDD over frequency see Figure 8 and Figure 9.
(3) This is the formula for the power dissipation calculation (see Figure 8 and the Power Consideration section).
Ptot = Pstat + Pdyn + PCload [W]
Pstat = VDD × IDD [W]
Pdyn = CPD × VDD2 × ƒ [W]
PCload = Cload × VDD2 × ƒ × n [W]
n = Number of switching output pins
(4) tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT.
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Product Folder Link(s): CDCLVC11xx
CDCLVC11xx
www.ti.com
SCAS895 –MAY 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITION MIN TYP(1) MAX UNIT
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V
VDD = 2.3 V, IOH = –0.1 mA 2.2
VOH High-level output voltage V
VDD = 2.3 V, IOH = –8 mA 1.7
VDD = 2.3 V, IOL = 0.1 mA 0.1
VOL Low-level output voltage V
VDD = 2.3 V, IOL = 8 mA 0.5
tPLH,Propagation delay CLKIN to Yn 1.0 2.6 ns
tPHL
tsk(o) Output skew Equal load of each output 50 ps
tr/tfRise and fall time 20%–80% reference point 0.3 1.2 ns
tDIS Output disable time 1G to Yn 10 ns
tEN Output enable time 1G to Yn 10 ns
Pulse skew ;
tsk(p) To be measured with input duty cycle of 50% 220 ps
tPLH(Yn) – tPHL(Yn) (5)
tsk(pp) Part-to-part skew Under equal operating conditions for two parts 1.2 ns
tjitter Additive jitter rms 12kHz…20 MHz, fOUT = 180 MHz 350 fs
(5) tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CDCLVC11xx
Z =50
OW
R = 50 W
fromMeasurementEquipment
V /2
DD
LVCMOS
Output
V =3.3Vor2.5V
DD
C = 2 pF
parasiticcapasitance
LVCMOS
Output
VDD
R= 100 W
R= 100 W
Z =50
OW
parasiticinputcapacitance
V =3.3Vor2.5V
DD
LVCMOS
Output Z =50
OW
RS=10 (V =3.3V)
RS=0 (V =2.5V)
W
W
DD
DD
parasiticinputcapacitance
V =3.3Vor2.5V
DD
tDIS tEN
VIN / 2
1 G
Yn
VIN / 2
tsk(o)
VDD / 2
Yn+1
VDD / 2
Yn
tsk(o)
CDCLVC11xx
SCAS895 –MAY 2010
www.ti.com
PARAMETERS MEASUREMENT INFORMATION
Figure 1. Test Load Circuit
Figure 2. Application Load With 50 ΩLine Termination
Figure 3. Application Load With Series Line Termination
Figure 4. tDIS and tEN for Disable Low Figure 5. Output Skew tsk(o)
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Product Folder Link(s): CDCLVC11xx
tr
Yn
80 % V OH -V OL
CLKIN
tf
20 % V OH -V OL
VOH
VOL
CDCLVC11xx
www.ti.com
SCAS895 –MAY 2010
PARAMETERS MEASUREMENT INFORMATION (continued)
Figure 6. Pulse Skew tsk(p) and Propagation Delay Figure 7. Rise/Fall Times tr/tf
tPLH/tPHL
TYPICAL CHARACTERISTICS
Power Consideration
The following power consideration refers to the device-consumed power consumption only. The device power
consumption is the sum of static power and dynamic power. The dynamic power usage consists of two
components:
1. Power used by the device as it switches states.
2. Power required to charge any output load.
The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in
Figure 8 and Figure 9 can be used to obtain the power consumption of the device:
Pdev = Pstat + n (Pdyn + PCload)
Pstat = VDD x IDD
Pdyn + PCload = see Figure 8 and Figure 9
where:
VDD = Supply voltage (3.3 V or 2.5 V)
IDD = Static device current (typ 6 mA for VDD = 3.3 V; typ 3 mA for VDD = 2.5 V)
n = Number of switching output pins
Example for Device Power Consumption for CDCLVC1104: 4 outputs are switching, f = 120 MHz, VDD = 3.3 V
and Cload = 2 pF per output:
Pdev = Pstat + n (Pdyn + PCload) = 19.8 mW + 40 mW = 59.8 mW
Pstat = VDD x IDD = 6 mA x 3.3 V = 19.8 mW
n (Pdyn + PCload)=4x10mW=40mW
NOTE
For dimensioning the power supply, the total power consumption needs to be considered.
The total power consumption is the sum of the device power consumption and the power
consumption of the load.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CDCLVC11xx
0
5
10
15
0 20 40 60 80 100 120 140 160 180
V = 2.5 V
DD P + P
dyn Cload8pF
P + P
dyn Cload50/2
P + P
dyn Cload2pF
f - Clock Frequency - MHz
Device Power Consumption - mW
0
10
20
30
40
0 20 40 60 80 100 120 140 160 180 200 220 240
f - Clock Frequency - MHz
V = 3.3 V
DD
P + P
dyn Cload8pF
P + P
dyn Cload50/2
P + P
dyn Cload2pF
Device Power Consumption - mW
0
1
2
3
0 20 40 60 80 100 120 140 160 180
I = C * V * f
dyn PD DD
V = 2.5 V
DD
f - Clock Frequency - MHz
I - Dynamic Supply Current - mA
dyn
0
1
2
3
4
5
0 20 40 60 80 100 120 140 160 180 200 220 240
f - Clock Frequency - MHz
I - Dynamic Supply Current - mA
dyn
I = C * V * f
dyn PD DD
V = 3.3 V
DD
CDCLVC11xx
SCAS895 –MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 8. Device Power Consumption vs Clock Frequency Figure 9. Device Power Consumption vs Clock Frequency
(Load 50Ωinto VDD/2. 2pF, 8pF; Per Output) (Load 50Ωinto VDD/2. 2pF, 8pF; Per Output)
Figure 10. Dynamic Supply Current vs Clock Frequency Figure 11. Dynamic Supply Current vs Clock Frequency
(CPD = 6pF, No Load; Per Output) (CPD = 4.5pF, No Load; Per Output)
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Product Folder Link(s): CDCLVC11xx
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CDCLVC1102PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1102PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1103PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1103PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
CDCLVC1104PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1104PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
CDCLVC1106PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1106PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
CDCLVC1108PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1108PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
CDCLVC1110PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1110PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
CDCLVC1112PW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CDCLVC1112PWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2010
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCLVC1102PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
CDCLVC1103PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
CDCLVC1104PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
CDCLVC1106PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CDCLVC1108PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CDCLVC1110PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
CDCLVC1112PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-May-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCLVC1102PWR TSSOP PW 8 2000 346.0 346.0 29.0
CDCLVC1103PWR TSSOP PW 8 2000 346.0 346.0 29.0
CDCLVC1104PWR TSSOP PW 8 2000 346.0 346.0 29.0
CDCLVC1106PWR TSSOP PW 14 2000 346.0 346.0 29.0
CDCLVC1108PWR TSSOP PW 16 2000 346.0 346.0 29.0
CDCLVC1110PWR TSSOP PW 20 2000 346.0 346.0 33.0
CDCLVC1112PWR TSSOP PW 24 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-May-2011
Pack Materials-Page 2