0 Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-3 (v2.0) November 28, 2001 0 0 Advance Product Specification VirtexTM-II Electrical Characteristics Virtex-II devices are provided in -4, -5, and -6 speed grades, with -6 having the highest performance. Virtex-II DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -4 speed grade industrial device are the same as for a -4 speed grade com- mercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Contact Xilinx for design considerations requiring more detailed information. All specifications are subject to change without notice. Virtex-II DC Characteristics Table 1: Absolute Maximum Ratings Symbol Description Units VCCINT Internal Supply voltage relative to GND -0.5 to 1.65 V VCCAUX Auxiliary supply voltage relative to GND -0.5 to 4.0 V VCCO Output drivers supply voltage relative to GND -0.5 to 4.0 V VBATT Key memory battery backup supply -0.5 to 4.0 V VREF Input Reference Voltage -0.5 to 4.0 V VIN Input voltage relative to GND (user and dedicated I/Os) -0.5 to 4.0 V VTS Voltage applied to 3-state output (user and dedicated I/Os) -0.5 to 4.0 V TSTG Storage temperature (ambient) TSOL TJ -65 to +150 C Maximum soldering temp. +220 Operating junction temperature +125 C C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Table 2: Recommended Operating Conditions Symbol VCCINT VCCAUX VCCO VBATT Description Internal Supply voltage relative to GND, TJ = 0 C to +85C Internal Supply voltage relative to GND, TJ = -40C to +100C Auxiliary supply voltage relative to GND, TJ = 0 C to +85C Auxiliary supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Battery voltage relative to GND, TJ = 0 C to +85C Battery voltage relative to GND, TJ = -40C to +100C Min Max Units Commercial 1.425 1.575 V Industrial 1.425 1.575 V Commercial 3.0 3.6 V Industrial 3.0 3.6 V Commercial 1.2 3.6 V Industrial 1.2 3.6 V Commercial 1.0 3.6 V Industrial 1.0 3.6 V Notes: 1. If VCCAUX and VCCO are both at 3.3 V, they must use a common supply voltage. 2. If battery is not used, do not connect VBATT. 3. For LVDS operation, VCCAUX min is 3.13 V and max is 3.47 V. (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 1 R Virtex-II 1.5V Field-Programmable Gate Arrays Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Device Min Max Units VDRINT Data Retention VCCINT Voltage All 1.2 V VDRI Data Retention VCCAUX Voltage All 2.5 V IREF VREF current per bank All -10 +10 m IL Input leakage current All -10 +10 m CIN Input capacitance All IRPU Pad pull-up (when selected) @ VIN = 0 V, VCCO = 3.3 V (sample tested) All Note 1 250 m IRPD Pad pull-down (when selected) @ VIN = 3.6 V (sample tested) All Note 1 250 m IBATT Battery supply current All 100 nA 10 A A pF A A Notes: 1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. Table 4: Quiescent Supply Current Symbol Description Quiescent VCCINT supply current ICCINTQ Quiescent VCCO supply current(1,2) ICCOQ Quiescent VCCAUX supply current(1,2) ICCAUXQ Device Min Typical Max Units XC2v40 XC2v80 XC2v250 XC2v500 XC2v1000 XC2v1500 XC2v2000 XC2v3000 XC2v4000 XC2v6000 XC2v8000 75 75 75 100 100 150 200 200 250 250 TBD TBD TBD TBD TBD 250 TBD TBD TBD TBD 1000 TBD mA XC2v40 XC2v80 XC2v250 XC2v500 XC2v1000 XC2v1500 XC2v2000 XC2v3000 XC2v4000 XC2v6000 XC2v8000 1 1 1 1 1 2 2 2 2 2 TBD TBD TBD TBD TBD 2 TBD TBD TBD TBD 4 TBD mA XC2v40 XC2v80 XC2v250 XC2v500 XC2v1000 XC2v1500 XC2v2000 XC2v3000 XC2v4000 XC2v6000 XC2v8000 10 10 10 10 10 20 20 20 25 25 TBD TBD TBD TBD TBD 25 TBD TBD TBD TBD 100 TBD mA Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 2. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWERTM. 3. Data are retained even if VCCO drops to 0 V. 4. Values specified for quiescent supply current parameters are Commercial Grade only. Module 3 of 4 2 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. The VCCINT, VCCAUX, and VCCO power supplies shall ramp on no faster than 1 ms and no slower than 50 ms. Ramp on is defined as: 0 VDC to minimum supply voltages. VCCAUX and VCCO for bank 4 must be connected together (3.3 VDC) to meet the following specification. Table 5 shows the minimum current required by Virtex-II devices for proper power on and configuration. Power supplies can be turned on in any sequence, as long as VCCAUX and VCCO are connected together for bank 4. If any VCCO bank powers up before VCCAUX, then each bank draws up to 600 mA, worst case, until the VCCAUX powers on(1). This does not harm the device. If the current is limited to the minimum value above, or larger, the device powers on properly after all three supplies have passed through their power on reset threshold voltages. Once initialized and configured, use the power calculator to estimate current drain on these supplies. Notes: 1. The 600 mA is transient current (peak); it eventually dissipates even if VCCAUX does not power up. Table 5: Power On Current for Virtex-II Devices Device (mA) 2v40 2v80 2v250 2v500 2v1000 2v1500 2v2000 2v3000 2v4000 2v6000 2v8000 ICCINTMIN 250 250 250 250 500 500 500 500 750 1000 TBD ICCAUXMIN 100 100 100 100 100 100 100 100 100 100 TBD ICCOMIN 50 50 50 50 50 100 100 100 100 100 TBD Notes: 1. Values specified for power on current parameters are Commercial Grade only. DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are cho- sen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 6: DC Input and Output Levels VIL Input/Output VIH VOL VOH IOL IOH Standard V, min V, max V, min V, max V, Max V, Min mA mA LVTTL(1) - 0.5 0.8 2.0 VCCO + 0.5 0.4 2.4 24 - 24 LVCMOS33 - 0.5 0.8 2.0 VCCO + 0.5 0.4 VCCO - 0.4 24 - 24 LVCMOS25 - 0.5 0.7 1.7 VCCO + 0.5 0.4 VCCO - 0.4 24 - 24 LVCMOS18 - 0.5 20% VCCO 70% VCCO VCCO + 0.5 0.4 VCCO - 0.45 16 - 16 LVCMOS15 - 0.5 20% VCCO 70% VCCO VCCO + 0.5 0.4 VCCO - 0.45 16 - 16 PCI33_3 - 0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2 PCI66_3 - 0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2 PCI-X - 0.5 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 GTLP - 0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.5 0.6 n/a 36 n/a GTL - 0.5 VREF - 0.05 VREF + 0.05 VCCO + 0.5 0.4 n/a 40 n/a HSTL I - 0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO - 0.4 8 -8 HSTL II - 0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO - 0.4 16 - 16 DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 3 R Virtex-II 1.5V Field-Programmable Gate Arrays Table 6: DC Input and Output Levels (Continued) VIH VIL Input/Output VOL VOH IOL IOH Standard V, min V, max V, min V, max V, Max V, Min mA mA HSTL III - 0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO - 0.4 24 -8 HSTL IV - 0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO - 0.4 48 -8 SSTL3 I - 0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.5 VREF - 0.6 VREF + 0.6 8 -8 SSTL3 II - 0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.5 VREF - 0.8 VREF + 0.8 16 - 16 SSTL2 I - 0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.5 VREF - 0.65 VREF + 0.65 7.6 - 7.6 SSTL2 II - 0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.5 VREF - 0.80 VREF + 0.80 15.2 - 15.2 AGP - 0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2 Notes: 1. VOL and VOH for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA. 2. Tested according to the relevant specifications. LDT Differential Signal DC Specifications (LDT_25) Table 7: LDT DC Specifications DC Parameter Symbol Conditions Min Typ Max Units Differential Output Voltage VOD RT = 100 ohm across Q and Q signals 500 600 700 mV 15 mV 640 mV 15 mV 1000 mV 15 mV 700 mV 15 mV Max Units Change in VOD Magnitude Output Common Mode Voltage Change in VOS Magnitude VOCM D Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude VOD D -15 RT = 100 ohm across Q and Q signals 560 VOCM -15 VID 200 VID -15 VICM 500 D D VICM 600 600 600 -15 LVDS DC Specifications (LVDS_33 & LVDS_25) Table 8: LVDS DC Specifications DC Parameter Symbol Supply Voltage VCCO Output High Voltage for Q and Q VOH RT = 100 W across Q and Q signals Output Low Voltage for Q and Q VOL RT = 100 W across Q and Q signals 0.925 VODIFF RT = 100 W across Q and Q signals 250 350 400 mV VOCM RT = 100 W across Q and Q signals 1.125 1.2 1.275 V VIDIFF Common-mode input voltage = 1.25 V 100 350 N/A mV VICM Differential input voltage = 350 mV 0.2 1.25 2.2 V Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage Module 3 of 4 4 Conditions Min Typ 3.3 or 2.5 www.xilinx.com 1-800-255-7778 V 1.475 V V DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Extended LVDS DC Specifications (LVDSEXT_33 & LVDSEXT_25) Table 9: Extended LVDS DC Specifications DC Parameter Symbol Supply Voltage VCCO Output High Voltage for Q and Q VOH RT = 100 W across Q and Q signals Output Low Voltage for Q and Q VOL RT = 100 W across Q and Q signals 0.705 VODIFF RT = 100 W across Q and Q signals 440 VOCM RT = 100 W across Q and Q signals 1.125 VIDIFF Common-mode input voltage = 1.25 V VICM Differential input voltage = 350 mV Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage Conditions Min Typ Max Units 3.3 or 2.5 V 1.70 V V 820 mV 1.200 1.275 V 100 350 N/A mV 0.2 1.25 2.2 V LVPECL DC Specifications These values are valid when driving a 100 W differential load only, i.e., a 100 W resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 10 summarizes the DC output specifications of LVPECL. Table 10: LVPECL DC Specifications DC Parameter Min VCCO Max Min 3.0 Max Min 3.3 Max 3.6 Units V VOH 1.8 2.11 1.92 2.28 2.13 2.41 V VOL 0.96 1.27 1.06 1.43 1.30 1.57 V VIH 1.49 2.72 1.49 2.72 1.49 2.72 V VIL 0.86 2.125 0.86 2.125 0.86 2.125 V Differential Input Voltage 0.3 - 0.3 - 0.3 - V DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 5 R Virtex-II 1.5V Field-Programmable Gate Arrays Virtex-II Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-II devices. The numbers reported here are worst-case values; they have all been fully characterized. Note that these values are subject to the same guidelines as Virtex-II Switching Characteristics, page 8 (speed files). Table 11 provides pin-to-pin values (in nanoseconds) including IOB delays; that is, delay through the device from input pin to output pin. In the case of multiple inputs and outputs, the worst delay is reported. Table 11: Pin-to-Pin Performance Description Pin-to-Pin (w/ I/O delays) Device Used & Speed Grade 16-bit Address Decoder 6.3 XC2V1000 -5 32-bit Address Decoder 7.7 XC2V1000 -5 64-bit Address Decoder 9.3 XC2V1000 -5 4:1 MUX 5.7 XC2V1000 -5 8:1 MUX 6.5 XC2V1000 -5 16:1 MUX 6.7 XC2V1000 -5 32:1 MUX 8.7 XC2V1000 -5 Combinatorial (pad to LUT to pad) 5.0 XC2V1000 -5 Basic Functions Memory Block RAM Pad to setup 1.6 Clock to Pad 9.5 Distributed RAM Pad to setup 2.7 XC2V1000 -5 Clock to Pad 5.1 (no clk skew) XC2V1000 -5 Table 12 shows internal (register-to-register) performance. Values are reported in MHz. Table 12: Register-to-Register Performance Description Register-to-Register Performance Device Used & Speed Grade 16-bit Address Decoder 398 XC2V1000 -5 32-bit Address Decoder 291 XC2V1000 -5 64-bit Address Decoder 275 XC2V1000 -5 4:1 MUX 563 XC2V1000 -5 8:1 MUX 454 XC2V1000 -5 16:1 MUX 414 XC2V1000 -5 32:1 MUX 323 XC2V1000 -5 Register to LUT to Register 613 XC2V1000 -5 8-bit Adder 292 XC2V1000 -5 16-bit Adder 239 XC2V1000 -5 64-bit Adder 114 XC2V1000 -5 64-bit Counter 114 XC2V1000 -5 64-bit Accumulator 110 XC2V1000 -5 Basic Functions Module 3 of 4 6 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Table 12: Register-to-Register Performance (Continued) Description Register-to-Register Performance Device Used & Speed Grade Multiplier 18x18 (with Block RAM inputs) 88 XC2V1000 -5 Multiplier 18x18 (with Register inputs) 105 XC2V1000 -5 Memory Block RAM Single-Port 4096 x 4 bits 265 Single-Port 2048 x 9 bits N/A Single-Port 1024 x 18 bits N/A Single-Port 512 x 36 bits N/A Dual-Port A:4096 x 4 bits & B:1024 x 18 bits N/A Dual-Port A:1024 x 18 bits & B:1024 x 18 bits N/A Dual-Port A:2048 x 9 bits & B: 512 x 36 bits N/A Distributed RAM Single-Port 32 x 8-bit 385 XC2V1000 -5 Single-Port 64 x 8-bit 335 XC2V1000 -5 Single-Port 128 x 8-bit 266 XC2V1000 -5 Dual-Port 16 x 8 400 XC2V1000 -5 Dual-Port 32 x 8 300 XC2V1000 -5 Dual-Port 64 x 8 294 XC2V1000 -5 Shift Registers 128-bit SRL N/A 256-bit SRL N/A FIFOs (Async. in Block RAM) 1024 x 18-bit N/A 1024 x 18-bit N/A FIFOs (Sync. in SRL) 128 x 8-bit N/A 128 x 16-bit N/A CAMs in Block RAM 32 x 9-bit N/A 64 x 9-bit N/A 128 x 9-bit N/A 256 x 9-bit N/A CAMs in SRL 32 x 16-bit N/A 64 x 32-bit N/A 128 x 40-bit N/A 256 x 48-bit N/A 1024 x 16-bit N/A 1024 x 72-bit N/A DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 7 R Virtex-II 1.5V Field-Programmable Gate Arrays Virtex-II Switching Characteristics Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Note that Virtex-II Performance Characteristics, page 6 are subject to these guidelines, as well. Each designation is defined as follows: Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Virtex-II device with a corresponding speed file designation. Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Table 13: Virtex-II Device Speed Grade Designations Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Speed Grade Designations Device Advance XC2V40 -6, -5, -4 XC2V80 -6, -5, -4 XC2V250 -6, -5, -4 XC2V500 -6, -5, -4 XC2V1000 -6 XC2V1500 -6, -5, -4 XC2V2000 -6, -5, -4 XC2V3000 -6, -5, -4 XC2V4000 -6, -5, -4 XC2V6000 -6, -5, -4 XC2V8000 -5, -4 Preliminary Production -5, -4 All specifications are always representative of worst-case supply voltage and junction temperature conditions. Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the Xilinx static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-II devices. IOB Input Switching Characteristics Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in IOB Input Switching Characteristics Standard Adjustments, page 10. Table 14: IOB Input Switching Characteristics Speed Grade Description Symbol Device -6 -5 -4 Units Pad to I output, no delay TIOPI All 0.69 0.76 0.88 ns, max Pad to I output, with delay TIOPID 2v40 3.15 3.46 3.98 ns, max 2v80 3.15 3.46 3.98 ns, max 2v250 3.15 3.46 3.98 ns, max Propagation Delays Module 3 of 4 8 2v500 3.15 3.46 3.98 ns, max 2v1000 3.15 3.46 3.98 ns, max 2v1500 3.15 3.46 3.98 ns, max 2v2000 3.15 3.46 3.98 ns, max 2v3000 3.24 3.56 4.10 ns, max 2v4000 3.24 3.56 4.10 ns, max 2v6000 3.51 3.86 4.44 ns, max 2v8000 TBD TBD TBD ns, max www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Table 14: IOB Input Switching Characteristics (Continued) Speed Grade Description Symbol Device -6 -5 -4 Units TIOPLI All 0.99 1.08 1.24 ns, max TIOPLID 2v40 3.44 3.78 4.35 ns, max 2v80 3.44 3.78 4.35 ns, max 2v250 3.44 3.78 4.35 ns, max 2v500 3.44 3.78 4.35 ns, max 2v1000 3.44 3.78 4.35 ns, max 2v1500 3.44 3.78 4.35 ns, max 2v2000 3.44 3.78 4.35 ns, max 2v3000 3.53 3.88 4.46 ns, max 2v4000 3.53 3.88 4.46 ns, max 2v6000 3.80 4.18 4.81 ns, max 2v8000 TBD TBD TBD ns, max All 0.63 0.69 0.80 ns, max TIOPICK/TIOICKP All 0.88/-0.36 0.96/-0.39 1.11/-0.45 ns, min TIOPICKD/TIOICKPD 2v40 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v80 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v250 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v500 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v1000 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v1500 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v2000 3.33/-2.07 3.66/-2.28 4.21/-2.63 ns, min 2v3000 3.42/-2.14 3.76/-2.35 4.33/-2.71 ns, min 2v4000 3.42/-2.14 3.76/-2.35 4.33/-2.71 ns, min 2v6000 3.69/-2.33 4.06/-2.56 4.67/-2.95 ns, min 2v8000 TBD TBD TBD ns, min TIOICECK/TIOCKICE All 0.19/ 0.03 0.21/ 0.04 0.24/ 0.04 ns, min TIOSRCKI All 0.27 0.30 0.34 ns, min SR input to IQ (asynchronous) TIOSRIQ All 1.11 1.22 1.40 ns, max GSR to output IQ TGSRQ All 7.27 7.99 9.19 ns, max Propagation Delays Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay Clock CLK to output IQ TIOCKIQ Setup and Hold Times With Respect to Clock at IOB Input Register Pad, no delay Pad, with delay ICE input SR input (IFF, synchronous) Set/Reset Delays Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 9 R Virtex-II 1.5V Field-Programmable Gate Arrays IOB Input Switching Characteristics Standard Adjustments Table 15: IOB Input Switching Characteristics Standard Adjustments Speed Grade Description Symbol Standard -6 -5 -4 Units TILVTTL LVTTL 0.00 0.00 0.00 ns TILVCMOS33 LVCMOS33 0.00 0.00 0.00 ns TILVCMOS25 LVCMOS25 0.10 0.11 0.12 ns TILVCMOS18 LVCMOS18 0.39 0.43 0.49 ns TILVCMOS15 LVCMOS15 0.91 1.00 1.15 ns TILVDS_25 LVDS_25 0.55 0.60 0.69 ns TILVDS_33 LVDS_33 0.55 0.60 0.69 ns TILVPECL_33 LVPECL 0.55 0.60 0.69 ns TIPCI33_3 PCI, 33 MHz, 3.3 V 0.00 0.00 0.00 ns TIPCI66_3 PCI, 66 MHz, 3.3 V 0.00 0.00 0.00 ns TIPCIX PCI-X, 133 MHz, 3.3 V 0.00 0.00 0.00 ns TIGTL GTL 0.38 0.42 0.48 ns TIGTLP GTLP 0.38 0.42 0.48 ns TIHSTL_I HSTL I 0.38 0.42 0.48 ns TIHSTL_II HSTL II 0.38 0.42 0.48 ns TIHSTL_III HSTL III 0.38 0.42 0.48 ns TIHSTL_IV HSTL IV 0.38 0.42 0.48 ns TIHSTL_I_18 HSTL I_18 0.38 0.42 0.48 ns TIHSTL_II_18 HSTL II_18 0.38 0.42 0.48 ns TIHSTL_III_18 HSTL III_18 0.38 0.42 0.48 ns TIHSTL_IV_18 HSTL IV_18 0.38 0.42 0.48 ns TISSTL2_I SSTL2 I 0.38 0.42 0.48 ns TISSTL2_II SSTL2 II 0.38 0.42 0.48 ns TISSTL3_I SSTL3 I 0.32 0.35 0.40 ns TISSTL3_II SSTL3 II 0.32 0.35 0.40 ns TIAGP AGP 0.32 0.35 0.40 ns TILVDCI_33 LVDCI_33 0.00 0.00 0.00 ns TILVDCI_25 LVDCI_25 0.10 0.11 0.12 ns TILVDCI_18 LVDCI_18 0.39 0.43 0.49 ns Data Input Delay Adjustments Standard-specific data input delay adjustments Module 3 of 4 10 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Symbol Standard -6 -5 -4 Units TILVDCI_15 LVDCI_15 0.91 1.00 1.14 ns TILVDCI_DV2_33 LVDCI_DV2_33 0.00 0.00 0.00 ns TILVDCI_DV2_25 LVDCI_DV2_25 0.10 0.11 0.12 ns TILVDCI_DV2_18 LVDCI_DV2_18 0.39 0.43 0.49 ns TILVDCI_DV2_15 LVDCI_DV2_15 0.91 1.00 1.14 ns TIGTL_DCI GTL_DCI 0.38 0.42 0.48 ns TIGTLP_DCI GTLP_DCI 0.38 0.42 0.48 ns TIHSTL_I_DCI HSTL_I_DCI 0.38 0.42 0.48 ns TIHSTL_II_DCI HSTL_II_DCI 0.38 0.42 0.48 ns TIHSTL_III_DCI HSTL_III_DCI 0.38 0.42 0.48 ns TIHSTL_IV_DCI HSTL_IV_DCI 0.38 0.42 0.48 ns TIHSTL_I_DCI_18 HSTL_I_DCI_18 0.38 0.42 0.48 ns TIHSTL_II_DCI_18 HSTL_II_DCI_18 0.38 0.42 0.48 ns TIHSTL_III_DCI_18 HSTL_III_DCI_18 0.38 0.42 0.48 ns TIHSTL_IV_DCI_18 HSTL_IV_DCI_18 0.38 0.42 0.48 ns TISSTL2_I_DCI SSTL2_I_DCI 0.38 0.42 0.48 ns TISSTL2_II_DCI SSTL2_II_DCI 0.38 0.42 0.48 ns TISSTL3_I_DCI SSTL3_I_DCI 0.32 0.35 0.40 ns TISSTL3_II_DCI SSTL3_II_DCI 0.32 0.35 0.40 ns TILDT_25 LDT_25 0.45 0.49 0.56 ns TIULVDS_25 ULVDS_25 0.45 0.49 0.56 ns Notes: 1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 11 R Virtex-II 1.5V Field-Programmable Gate Arrays IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 13. Table 16: IOB Output Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units O input to Pad TIOOP 2.39 2.63 3.03 ns, max O input to Pad via transparent latch TIOOLP 2.69 2.95 3.40 ns, max T input to Pad high-impedance(1) TIOTHZ 0.51 0.56 0.64 ns, max T input to valid data on Pad TIOTON 2.34 2.57 2.96 ns, max T input to Pad high-impedance via transparent latch(1) TIOTLPHZ 0.80 0.88 1.01 ns, max T input to valid data on Pad via transparent latch TIOTLPON 2.63 2.89 3.33 ns, max TGTS 6.56 7.22 8.30 ns, max Clock CLK to Pad TIOCKP 2.72 2.99 3.44 ns, max Clock CLK to Pad high-impedance (synchronous)(1) TIOCKHZ 0.95 1.04 1.20 ns, max Clock CLK to valid data on Pad (synchronous) TIOCKON 2.78 3.06 3.51 ns, max TIOOCK/TIOCKO 0.31/-0.08 0.34/-0.09 0.39/-0.11 ns, min OCE input TIOOCECK/TIOCKOCE 0.19/-0.06 0.21/-0.07 0.24/-0.08 ns, min SR input (OFF) TIOSRCKO/TIOCKOSR 0.27/-0.05 0.30/-0.06 0.34/-0.07 ns, min TIOTCK/TIOCKT 0.28/-0.06 0.31/-0.07 0.35/-0.08 ns, min 3-State Setup Times, TCE input TIOTCECK/TIOCKTCE 0.19/-0.06 0.21/-0.07 0.24/-0.08 ns, min 3-State Setup Times, SR input (TFF) TIOSRCKT/TIOCKTSR 0.27/-0.05 0.30/-0.06 0.34/-0.07 ns, min SR input to Pad (asynchronous) TIOSRP 3.37 3.71 4.26 ns, max SR input to Pad high-impedance (asynchronous)(1) TIOSRHZ 1.52 1.67 1.92 ns, max SR input to valid data on Pad (asynchronous) TIOSRON 3.35 3.68 4.23 ns, max GSR to Pad TIOGSRQ 5.44 5.98 6.88 ns, max Propagation Delays 3-State Delays GTS to Pad high impedance(1) Sequential Delays Setup and Hold Times Before/After Clock CLK O input 3-State Setup Times, T input Set/Reset Delays Notes: 1. The 3-state turn-off delays should not be adjusted. Module 3 of 4 12 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Table 17: IOB Output Switching Characteristics Standard Adjustments Speed Grade Description Symbol Standard -6 -5 -4 Units TOLVTTL_S2 LVTTL, Slow, 2 mA 8.53 9.38 10.79 ns TOLVTTL_S4 4 mA 5.15 5.67 6.52 ns TOLVTTL_S6 6 mA 3.75 4.12 4.74 ns TOLVTTL_S8 8 mA 2.57 2.83 3.25 ns TOLVTTL_S12 12 mA 2.00 2.19 2.52 ns TOLVTTL_S16 16 mA 1.17 1.28 1.48 ns TOLVTTL_S24 24 mA 0.85 0.94 1.08 ns TOLVTTL_F2 LVTTL, Fast, 2 mA 5.37 5.90 6.79 ns TOLVTTL_F4 4 mA 2.19 2.41 2.77 ns TOLVTTL_F6 6 mA 0.94 1.03 1.18 ns TOLVTTL_F8 8 mA 0.06 0.07 0.08 ns TOLVTTL_F12 12 mA 0.00 0.00 0.00 ns TOLVTTL_F16 16 mA -0.30 -0.33 -0.38 ns TOLVTTL_F24 24 mA -0.44 -0.48 -0.55 ns TOLVDS_25 LVDS -1.02 -1.12 -1.29 ns TOLVDS_33 LVDS -1.07 -1.18 -1.36 ns TOLVDSEXT_25 LVDS -0.94 -1.03 -1.19 ns TOLVDSEXT_33 LVDS -0.95 -1.05 -1.21 ns TOLDT_25 LDT -1.01 -1.11 -1.28 ns TOBLVDS_25 BLVDS 0.63 0.69 0.79 ns TOULVDS_25 ULVDS -1.01 -1.11 -1.28 ns TOLVPECL_33 LVPECL 0.74 0.81 0.93 ns TOPCI33_3 PCI, 33 MHz, 3.3 V 1.06 1.17 1.34 ns TOPCI66_3 PCI, 66 MHz, 3.3 V -0.14 -0.15 -0.18 ns TOPCIX PCI-X, 133 MHz, 3.3 V -0.14 -0.16 -0.18 ns TOGTL GTL 1.13 1.24 1.43 ns TOGTLP GTLP 0.43 0.47 0.54 ns TOHSTL_I HSTL I 0.19 0.21 0.24 ns TOHSTL_II HSTL II 0.01 0.01 0.01 ns TOHSTL_III HSTL III -0.17 -0.18 -0.21 ns TOHSTL_IV HSTL IV -0.22 -0.24 -0.28 ns TOHSTL_I_18 HSTL I_18 0.22 0.25 0.28 ns TOHSTL_II_18 HSTL II_18 0.13 0.14 0.16 ns TOHSTL_III_18 HSTL III_18 0.11 0.12 0.14 ns TOHSTL_IV_18 HSTL IV_18 0.15 0.17 0.19 ns Output Delay Adjustments Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 13 R Virtex-II 1.5V Field-Programmable Gate Arrays Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Module 3 of 4 14 Symbol Standard -6 -5 -4 Units TOSSTL2_I SSTL2 I 0.20 0.22 0.25 ns TOSSTL2_II SSTL2 II -0.36 -0.39 -0.45 ns TOSSTL3_I SSTL3 I 0.29 0.32 0.36 ns TOSSTL3_II SSTL3 II -0.14 -0.16 -0.18 ns TOAGP AGP -0.44 -0.48 -0.56 ns TOLVCMOS33_S2 LVCMOS33, Slow, 2 mA 7.03 7.74 8.90 ns TOLVCMOS33_S4 4 mA 3.83 4.22 4.85 ns TOLVCMOS33_S6 6 mA 2.73 3.00 3.45 ns TOLVCMOS33_S8 8 mA 1.97 2.17 2.50 ns TOLVCMOS33_S12 12 mA 1.46 1.60 1.84 ns TOLVCMOS33_S16 16 mA 0.87 0.96 1.10 ns TOLVCMOS33_S24 24 mA 0.82 0.91 1.04 ns TOLVCMOS33_F2 LVCMOS33, Fast, 2 mA 5.46 6.01 6.91 ns TOLVCMOS33_F4 4 mA 2.12 2.33 2.68 ns TOLVCMOS33_F6 6 mA 0.62 0.68 0.79 ns TOLVCMOS33_F8 8 mA -0.08 -0.09 -0.11 ns TOLVCMOS33_F12 12 mA -0.22 -0.24 -0.28 ns TOLVCMOS33_F16 16 mA -0.42 -0.46 -0.53 ns TOLVCMOS33_F24 24 mA -0.51 -0.56 -0.65 ns TOLVCMOS25_S2 LVCMOS25, Slow, 2 mA 8.34 9.17 10.55 ns TOLVCMOS25_S4 4 mA 4.69 5.16 5.93 ns TOLVCMOS25_S6 6 mA 4.14 4.56 5.24 ns TOLVCMOS25_S8 8 mA 3.61 3.97 4.57 ns TOLVCMOS25_S12 12 mA 2.51 2.76 3.18 ns TOLVCMOS25_S16 16 mA 1.98 2.18 2.51 ns TOLVCMOS25_S24 24 mA 1.62 1.78 2.05 ns TOLVCMOS25_F2 LVCMOS25, Fast, 2 mA 3.90 4.29 4.94 ns TOLVCMOS25_F4 4 mA 0.92 1.01 1.17 ns TOLVCMOS25_F6 6 mA 0.41 0.45 0.51 ns TOLVCMOS25_F8 8 mA 0.23 0.25 0.29 ns TOLVCMOS25_F12 12 mA -0.13 -0.14 -0.17 ns TOLVCMOS25_F16 16 mA -0.22 -0.24 -0.28 ns TOLVCMOS25_F24 24 mA -0.38 -0.42 -0.48 ns TOLVCMOS18_S2 LVCMOS18, Slow, 2 mA 15.71 17.28 19.87 ns TOLVCMOS18_S4 4 mA 10.38 11.42 13.13 ns TOLVCMOS18_S6 6 mA 7.46 8.21 9.44 ns TOLVCMOS18_S8 8 mA 6.92 7.61 8.75 ns TOLVCMOS18_S12 12 mA 5.31 5.84 6.71 ns TOLVCMOS18_S16 16 mA 5.05 5.56 6.39 ns TOLVCMOS18_F2 LVCMOS18, Fast, 2 mA 4.64 5.10 5.87 ns www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description DS031-3 (v2.0) November 28, 2001 Advance Product Specification Symbol Standard -6 -5 -4 Units TOLVCMOS18_F4 4 mA 1.48 1.63 1.87 ns TOLVCMOS18_F6 6 mA 0.66 0.73 0.83 ns TOLVCMOS18_F8 8 mA 0.59 0.65 0.75 ns TOLVCMOS18_F12 12 mA 0.12 0.14 0.16 ns TOLVCMOS18_F16 16 mA 0.13 0.14 0.16 ns TOLVCMOS15_S2 LVCMOS15, Slow, 2 mA 19.67 21.63 24.88 ns TOLVCMOS15_S4 4 mA 13.13 14.44 16.61 ns TOLVCMOS15_S6 6 mA 12.55 13.80 15.87 ns TOLVCMOS15_S8 8 mA 9.54 10.49 12.06 ns TOLVCMOS15_S12 12 mA 9.46 10.41 11.97 ns TOLVCMOS15_S16 16 mA 8.56 9.41 10.83 ns TOLVCMOS15_F2 LVCMOS15, Fast, 2 mA 4.32 4.75 5.46 ns TOLVCMOS15_F4 4 mA 1.59 1.75 2.02 ns TOLVCMOS15_F6 6 mA 1.21 1.33 1.53 ns TOLVCMOS15_F8 8 mA 0.79 0.87 1.00 ns TOLVCMOS15_F12 12 mA 0.63 0.69 0.79 ns TOLVCMOS15_F16 16 mA 0.59 0.65 0.75 ns TOLVDCI_33 LVDCI_33 0.66 0.73 0.83 ns TOLVDCI_25 LVDCI_25 0.57 0.62 0.71 ns TOLVDCI_18 LVDCI_18 1.40 1.54 1.77 ns TOLVDCI_15 LVDCI_15 2.96 3.26 3.75 ns TOLVDCI_DV2_33 LVDCI_DV2_33 0.15 0.17 0.19 ns TOLVDCI_DV2_25 LVDCI_DV2_25 0.31 0.34 0.39 ns TOLVDCI_DV2_18 LVDCI_DV2_18 1.07 1.18 1.35 ns TOLVDCI_DV2_15 LVDCI_DV2_15 2.05 2.25 2.59 ns TOGTL_DCI GTL_DCI 2.82 3.10 3.56 ns TOGTLP_DCI GTLP_DCI 2.03 2.23 2.56 ns TOHSTL_I_DCI HSTL_I_DCI 0.50 0.55 0.63 ns TOHSTL_II_DCI HSTL_II_DCI 0.39 0.43 0.50 ns TOHSTL_III_DCI HSTL_III_DCI 0.15 0.17 0.19 ns TOHSTL_IV_DCI HSTL_IV_DCI -0.01 -0.01 -0.02 ns TOHSTL_I_DCI_18 HSTL_I_DCI_18 0.21 0.23 0.26 ns TOHSTL_II_DCI_18 HSTL_II_DCI_18 0.94 1.03 1.19 ns TOHSTL_III_DCI_18 HSTL_III_DCI_18 0.18 0.20 0.23 ns TOHSTL_IV_DCI_18 HSTL_IV_DCI_18 -0.14 -0.16 -0.18 ns TOSSTL2_I_DCI SSTL2_I_DCI 0.25 0.28 0.32 ns TOSSTL2_II_DCI SSTL2_II_DCI 0.05 0.06 0.07 ns TOSSTL3_I_DCI SSTL3_I_DCI 0.30 0.33 0.38 ns TOSSTL3_II_DCI SSTL3_II_DCI 0.16 0.18 0.20 ns www.xilinx.com 1-800-255-7778 Module 3 of 4 15 R Virtex-II 1.5V Field-Programmable Gate Arrays Table 18: Delay Measurement Methodology VL(1) VH(1) Meas. Point VREF (Typ)(2) LVTTL 0 3 1.4 - LVCMOS33 0 3.3 1.65 - LVCMOS25 0 2.5 1.25 - LVCMOS18 0 1.8 0.9 - LVCMOS15 0 1.5 0.75 - Standard PCI33_3 Per PCI Specification - PCI66_3 Per PCI Specification - Per PCI-X Specification - PCIX33_3 GTL VREF - 0.2 VREF + 0.2 VREF 0.80 GTLP VREF - 0.2 VREF + 0.2 VREF 1.0 HSTL Class I VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class II VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class III VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL Class IV VREF - 0.5 VREF + 0.5 VREF 0.90 SSTL3 I & II VREF - 1.0 VREF + 1.0 VREF 1.5 SSTL2 I & II VREF - 0.75 VREF + 0.75 VREF 1.25 VREF - (0.2xVCCO) VREF + (0.2xVCCO) VREF Per AGP Spec LVDS_25 1.2 - 0.125 1.2 + 0.125 1.2 LVDS_33 1.2 - 0.125 1.2 + 0.125 1.2 LVDSEXT_25 1.2 - 0.125 1.2 + 0.125 1.2 LVDSEXT_33 1.2 - 0.125 1.2 + 0.125 1.2 ULVDS_25 0.6 - 0.125 0.6 + 0.125 0.6 LDT_25 0.6 - 0.125 0.6 + 0.125 0.6 LVPECL 1.6 -0.3 1.6 + 0.3 1.6 AGP Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported. Module 3 of 4 16 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Table 19: Standard Capacitive Loads Standard Csl (pF) LVTTL Fast Slew Rate, 2mA drive 35 LVTTL Fast Slew Rate, 4mA drive 35 LVTTL Fast Slew Rate, 6mA drive 35 LVTTL Fast Slew Rate, 8mA drive 35 LVTTL Fast Slew Rate, 12mA drive 35 LVTTL Fast Slew Rate, 16mA drive 35 LVTTL Fast Slew Rate, 24mA drive 35 LVTTL Slow Slew Rate, 2mA drive 35 LVTTL Slow Slew Rate, 4mA drive 35 LVTTL Slow Slew Rate, 6mA drive 35 LVTTL Slow Slew Rate, 8mA drive 35 LVTTL Slow Slew Rate, 12mA drive 35 LVTTL Slow Slew Rate, 16mA drive 35 LVTTL Slow Slew Rate, 24mA drive 35 LVCMOS33 35 LVCMOS25 35 LVCMOS18 35 LVCMOS15 35 PCI 33MHZ 3.3 V 10 PCI 66 MHz 3.3 V 10 PCI-X 133 MHz 3.3 V 10 GTL 0 GTLP 0 HSTL Class I 20 HSTL Class II 20 HSTL Class III 20 HSTL Class IV 20 SSTL2 Class I 30 SSTL2 Class II 30 SSTL3 Class I 30 SSTL3 Class II 30 AGP 10 Notes: 1. I/O parameter measurements are made with the capacitance values shown above. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. 3. Use of IBIS models results in a more accurate prediction of the propagation delay: a. Model the output in an IBIS simulation into the standard capacitive load. b. Record the relative time to the VOH or VOL transition of interest. c. Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS models for driven devices. d. Record the results from the new simulation. e. Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should be added or subtracted from the value above to predict the actual delay. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 17 R Virtex-II 1.5V Field-Programmable Gate Arrays Clock Distribution Switching Characteristics Table 20: Clock Distribution Switching Characteristics Speed Grade Description Global Clock Buffer I input to O output Symbol -6 -5 -4 Units TGIO 0.17 0.19 0.21 ns, max CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used (see Figure 15). The values listed below are worst-case. Precise values are provided by the timing analyzer. Table 21: CLB Switching Characteristics Speed Grade Symbol -6 -5 -4 Units 4-input function: F/G inputs to X/Y outputs TILO 0.35 0.39 0.44 ns, max 5-input function: F/G inputs to F5 output TIF5 0.57 0.63 0.72 ns, max 5-input function: F/G inputs to X output TIF5X 0.76 0.83 0.95 ns, max FXINA or FXINB inputs to Y output via MUXFX TIFXY 0.36 0.39 0.45 ns, max FXINA input to FX output via MUXFX TINAFX 0.26 0.28 0.32 ns, max FXINB input to FX output via MUXFX TINBFX 0.26 0.28 0.32 ns, max SOPIN input to SOPOUT output via ORCY TSOPSOP 0.35 0.38 0.44 ns, max Incremental delay routing through transparent latch to XQ/YQ outputs TIFNCTL 0.41 0.45 0.51 ns, max FF Clock CLK to XQ/YQ outputs TCKO 0.45 0.50 0.57 ns, max Latch Clock CLK to XQ/YQ outputs TCKLO 0.54 0.59 0.68 ns, max BX/BY inputs TDICK/TCKDI 0.30/-0.07 0.33/-0.08 0.37/-0.09 ns, min DY inputs TDYCK/TCKDY 0.30/-0.07 0.33/-0.08 0.37/-0.09 ns, min DX inputs TDXCK/TCKDX 0.30/-0.07 0.33/-0.08 0.37/-0.09 ns, min CE input TCECK/TCKCE 0.19/-0.06 0.21/-0.07 0.24/-0.08 ns, min TRCK/TCKR 0.21/-0.02 0.23/-0.03 0.26/-0.03 ns, min Minimum Pulse Width, High TCH 0.61 0.67 0.77 ns, min Minimum Pulse Width, Low TCL 0.61 0.67 0.77 ns, min TRPW 0.61 0.67 0.77 ns, min Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) TRQ 1.06 1.17 1.34 ns, max Toggle Frequency (MHz) (for export control) FTOG 826.45 751.31 653.59 MHz Description Combinatorial Delays Sequential Delays Setup and Hold Times Before/After Clock CLK SR/BY inputs (synchronous) Clock CLK Set/Reset Minimum Pulse Width, SR/BY inputs Module 3 of 4 18 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays CLB Distributed RAM Switching Characteristics Table 22: CLB Distributed RAM Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Clock CLK to X/Y outputs (WE active) in 16 x 1 mode TSHCKO16 1.63 1.79 2.05 ns, max Clock CLK to X/Y outputs (WE active) in 32 x 1 mode TSHCKO32 1.97 2.17 2.49 ns, max Clock CLK to F5 output TSHCKOF5 1.77 1.94 2.23 ns, max BX/BY data inputs (DIN) TDS/TDH 0.53/-0.09 0.58/-0.10 0.67/-0.11 ns, min F/G address inputs TAS/TAH 0.40/ 0.00 0.44/ 0.00 0.50/ 0.00 ns, min TWES/TWEH 0.42/-0.01 0.46/-0.01 0.53/-0.01 ns, min Minimum Pulse Width, High TWPH 0.57 0.63 0.72 ns, min Minimum Pulse Width, Low TWPL 0.57 0.63 0.72 ns, min Minimum clock period to meet address write cycle time TWC 1.14 1.25 1.44 ns, min Sequential Delays Setup and Hold Times Before/After Clock CLK CE input (WE) Clock CLK CLB Shift Register Switching Characteristics Table 23: CLB Shift Register Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units Clock CLK to X/Y outputs TREG 2.31 2.54 2.92 ns, max Clock CLK to X/Y outputs TREG32 2.65 2.92 3.35 ns, max Clock CLK to XB output via MC15 LUT output TREGXB 2.23 2.46 2.82 ns, max Clock CLK to YB output via MC15 LUT output TREGYB 2.18 2.40 2.75 ns, max Clock CLK to Shiftout TCKSH 1.92 2.11 2.43 ns, max Clock CLK to F5 output TREGF5 2.45 2.69 3.09 ns, max TSRLDS/TSRLDH 0.53/-0.07 0.58/-0.08 0.67/-0.09 ns, min TWSS/TWSH 0.19/-0.06 0.21/-0.07 0.24/-0.08 ns, min Minimum Pulse Width, High TSRPH 0.57 0.63 0.72 ns, min Minimum Pulse Width, Low TSRPL 0.57 0.63 0.72 ns, min Sequential Delays Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) CE input (WS) Clock CLK DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 19 R Virtex-II 1.5V Field-Programmable Gate Arrays Multiplier Switching Characteristics Table 24: Multiplier Switching Characteristics Speed Grade Symbol -6 -5 -4 Units Input to Pin35 TMULT_P35 6.49 8.50 10.36 ns, max Input to Pin34 TMULT_P34 6.36 8.33 10.14 ns, max Input to Pin33 TMULT_P33 6.23 8.16 9.92 ns, max Input to Pin32 TMULT_P32 6.10 7.99 9.70 ns, max Input to Pin31 TMULT_P31 5.97 7.82 9.48 ns, max Input to Pin30 TMULT_P30 5.84 7.65 9.26 ns, max Input to Pin29 TMULT_P29 5.71 7.48 9.04 ns, max Input to Pin28 TMULT_P28 5.58 7.31 8.82 ns, max Input to Pin27 TMULT_P27 5.45 7.14 8.60 ns, max Input to Pin26 TMULT_P26 5.32 6.97 8.38 ns, max Input to Pin25 TMULT_P25 5.19 6.80 8.16 ns, max Input to Pin24 TMULT_P24 5.06 6.63 7.94 ns, max Input to Pin23 TMULT_P23 4.93 6.46 7.72 ns, max Input to Pin22 TMULT_P22 4.80 6.29 7.50 ns, max Input to Pin21 TMULT_P21 4.67 6.12 7.28 ns, max Input to Pin20 TMULT_P20 4.54 5.95 7.06 ns, max Input to Pin19 TMULT_P19 4.41 5.78 6.84 ns, max Input to Pin18 TMULT_P18 4.28 5.61 6.62 ns, max Input to Pin17 TMULT_P17 4.15 5.44 6.40 ns, max Input to Pin16 TMULT_P16 4.02 5.27 6.18 ns, max Input to Pin15 TMULT_P15 3.89 5.10 5.96 ns, max Input to Pin14 TMULT_P14 3.76 4.93 5.74 ns, max Input to Pin13 TMULT_P13 3.63 4.76 5.52 ns, max Input to Pin12 TMULT_P12 3.50 4.59 5.30 ns, max Input to Pin11 TMULT_P11 3.37 4.42 5.08 ns, max Input to Pin10 TMULT_P10 3.24 4.25 4.86 ns, max Input to Pin9 TMULT_P9 3.11 4.08 4.64 ns, max Input to Pin8 TMULT_P8 2.98 3.91 4.42 ns, max Input to Pin7 TMULT_P7 2.85 3.74 4.20 ns, max Input to Pin6 TMULT_P6 2.72 3.57 3.98 ns, max Input to Pin5 TMULT_P5 2.59 3.40 3.76 ns, max Input to Pin4 TMULT_P4 2.46 3.23 3.54 ns, max Input to Pin3 TMULT_P3 2.33 3.06 3.32 ns, max Input to Pin2 TMULT_P2 2.20 2.89 3.10 ns, max Input to Pin1 TMULT_P1 2.07 2.72 2.88 ns, max Input to Pin0 TMULT_P0 1.94 2.55 2.66 ns, max Description Propagation Delay to Output Pin Module 3 of 4 20 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Table 25: Pipelined Multiplier Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units TMULIDCK/TMULCKID 3.00/0.000 3.45/0.000 3.89/0.000 ns, max TMULIDCK_CE/TMULCKID_CE 0.72/0.000 0.80/0.000 0.86/0.000 ns, max TMULIDCK_RST/TMULCKID_RST 0.72/0.000 0.80/0.000 0.86/0.000 ns, max Clock to Pin35 TMULTCK_P35 4.11 6.91 8.11 ns, max Clock to Pin34 TMULTCK_P34 3.98 6.75 7.92 ns, max Clock to Pin33 TMULTCK_P33 3.86 6.59 7.74 ns, max Clock to Pin32 TMULTCK_P32 3.73 6.43 7.55 ns, max Clock to Pin31 TMULTCK_P31 3.60 6.27 7.37 ns, max Clock to Pin30 TMULTCK_P30 3.47 6.11 7.18 ns, max Clock to Pin29 TMULTCK_P29 3.34 5.95 6.99 ns, max Clock to Pin28 TMULTCK_P28 3.22 5.79 6.81 ns, max Clock to Pin27 TMULTCK_P27 3.09 5.63 6.62 ns, max Clock to Pin26 TMULTCK_P26 2.96 5.47 6.44 ns, max Clock to Pin25 TMULTCK_P25 2.83 5.31 6.25 ns, max Clock to Pin24 TMULTCK_P24 2.70 5.15 6.06 ns, max Clock to Pin23 TMULTCK_P23 2.58 4.99 5.88 ns, max Clock to Pin22 TMULTCK_P22 2.45 4.83 5.69 ns, max Clock to Pin21 TMULTCK_P21 2.32 4.67 5.51 ns, max Clock to Pin20 TMULTCK_P20 2.19 4.51 5.32 ns, max Clock to Pin19 TMULTCK_P19 2.06 4.35 5.13 ns, max Clock to Pin18 TMULTCK_P18 1.94 4.19 4.95 ns, max Clock to Pin17 TMULTCK_P17 1.81 4.03 4.76 ns, max Clock to Pin16 TMULTCK_P16 1.68 3.87 4.58 ns, max Clock to Pin15 TMULTCK_P15 1.68 3.71 4.39 ns, max Clock to Pin14 TMULTCK_P14 1.68 3.55 4.20 ns, max Clock to Pin13 TMULTCK_P13 1.68 3.39 4.02 ns, max Clock to Pin12 TMULTCK_P12 1.68 3.23 3.83 ns, max Clock to Pin11 TMULTCK_P11 1.68 3.07 3.65 ns, max Clock to Pin10 TMULTCK_P10 1.68 2.91 3.46 ns, max Clock to Pin9 TMULTCK_P9 1.68 2.75 3.27 ns, max Clock to Pin8 TMULTCK_P8 1.68 2.59 3.09 ns, max Clock to Pin7 TMULTCK_P7 1.68 2.43 2.90 ns, max Clock to Pin6 TMULTCK_P6 1.68 2.27 2.72 ns, max Clock to Pin5 TMULTCK_P5 1.68 2.11 2.53 ns, max Clock to Pin4 TMULTCK_P4 1.68 1.95 2.34 ns, max Clock to Pin3 TMULTCK_P3 1.68 1.79 2.16 ns, max Clock to Pin2 TMULTCK_P2 1.68 1.63 1.97 ns, max Clock to Pin1 TMULTCK_P1 1.68 1.47 1.79 ns, max Clock to Pin0 TMULTCK_P0 1.68 1.31 1.60 ns, max Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 21 R Virtex-II 1.5V Field-Programmable Gate Arrays Block SelectRAM Switching Characteristics Table 26: Block SelectRAM Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units TBCKO 2.10 2.31 2.65 ns, max ADDR inputs TBACK/TBCKA 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, min DIN inputs TBDCK/TBCKD 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, min EN input TBECK/TBCKE 0.95/-0.46 1.04/-0.50 1.20/-0.58 ns, min RST input TBRCK/TBCKR 1.31/-0.71 1.44/-0.78 1.65/-0.90 ns, min WEN input TBWCK/TBCKW 0.57/-0.19 0.63/-0.21 0.72/-0.25 ns, min Minimum Pulse Width, High TBPWH 1.17 1.29 1.48 ns, min Minimum Pulse Width, Low TBPWL 1.17 1.29 1.48 ns, min Sequential Delays Clock CLK to DOUT output Setup and Hold Times Before Clock CLK Clock CLK TBUF Switching Characteristics Table 27: TBUF Switching Characteristics Speed Grade Description Symbol -6 -5 -4 Units TIO 0.23 0.25 0.29 ns, max TRI input to OUT output high-impedance TOFF 0.44 0.48 0.55 ns, max TRI input to valid data on OUT output TON 0.44 0.48 0.55 ns, max Combinatorial Delays IN input to OUT output JTAG Test Access Port Switching Characteristics Table 28: JTAG Test Access Port Switching Characteristics Description Symbol Units TMS and TDI Setup times before TCK TTAPTK 5.5 ns, min TMS and TDI Hold times after TCK TTCKTAP 0.0 ns, min Output delay from clock TCK to output TDO TTCKTDO 10.0 ns, max FTCK 33 MHz, max Maximum TCK clock frequency Module 3 of 4 22 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Virtex-II Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM Table 29: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM Speed Grade Description Symbol Device -6 -5 -4 Units TICKOFDCM 2v40 2.19 2.40 2.76 ns 2v80 2.19 2.40 2.76 ns 2v250 2.19 2.40 2.76 ns 2v500 2.19 2.40 2.76 ns 2v1000 2.19 2.40 2.76 ns 2v1500 2.19 2.40 2.76 ns 2v2000 2.19 2.40 2.76 ns 2v3000 2.28 2.50 2.88 ns 2v4000 2.28 2.50 2.88 ns 2v6000 2.73 3.00 3.45 ns 2v8000 TBD TBD TBD ns LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 13. Global Clock and OFF with DCM Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 18. 3. DCM output jitter is already included in the timing calculation. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 23 R Virtex-II 1.5V Field-Programmable Gate Arrays Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM Table 30: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM Speed Grade Description Symbol Device -6 -5 -4 Units TICKOF 2v40 4.28 4.70 4.98 ns 2v80 4.28 4.70 4.98 ns 2v250 4.50 5.00 5.75 ns 2v500 4.50 5.00 5.75 ns 2v1000 5.10 5.40 5.90 ns 2v1500 5.10 5.40 5.90 ns 2v2000 5.20 5.55 6.10 ns 2v3000 5.20 5.70 6.55 ns 2v4000 5.50 6.00 6.90 ns 2v6000 5.73 6.30 7.22 ns 2v8000 TBD TBD TBD ns LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 13. Global Clock and OFF without DCM Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 18. Module 3 of 4 24 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Virtex-II Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Setup and Hold for LVTTL Standard, With DCM Table 31: Global Clock Setup and Hold for LVTTL Standard, With DCM Speed Grade Description Symbol Device -6 -5 -4 Units TPSDCM/TPHDCM 2v40 1.60/-0.90 1.60/-0.90 1.84/-0.76 ns 2v80 1.60/-0.90 1.60/-0.90 1.84/-0.76 ns 2v250 1.60/-0.90 1.60/-0.90 1.84/-0.76 ns 2v500 1.60/-0.90 1.60/-0.90 1.84/-0.76 ns 2v1000 1.60/-0.90 1.60/-0.90 1.84/-0.76 ns 2v1500 1.60/-0.90 1.60/-0.90 1.84/-0.76 ns 2v2000 1.70/-0.90 1.70/-0.90 1.96/-0.76 ns 2v3000 1.70/-0.90 1.70/-0.90 1.96/-0.76 ns 2v4000 1.70/-0.90 1.70/-0.90 1.96/-0.76 ns 2v6000 1.70/-0.90 1.70/-0.90 1.96/-0.76 ns 2v8000 TBD TBD TBD ns Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 10. No Delay Global Clock and IFF with DCM Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DCM output jitter is already included in the timing calculation. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 25 R Virtex-II 1.5V Field-Programmable Gate Arrays Global Clock Setup and Hold for LVTTL Standard, Without DCM , Table 32: Global Clock Setup and Hold for LVTTL Standard, Without DCM Speed Grade Description Symbol Device -6 -5 -4 Units TPSFD/TPHFD 2v40 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v80 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v250 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v1000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v1500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v2000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v3000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v4000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns 2v6000 1.92/ 0.46 1.92/ 0.50 2.21/ 0.50 ns 2v8000 TBD TBD TBD ns Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 10. Full Delay Global Clock and IFF without DCM Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. Module 3 of 4 26 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays DCM Timing Parameters Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605; all devices are 100% functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The fol- lowing guidelines reflect worst-case values across the recommended operating conditions. All output jitter and phase specifications are determined through statistical measurement at the package pins. Operating Frequency Ranges e Table 33: Operating Frequency Ranges Speed Grade -6 -5 -4 CLKOUT_FREQ_1X_LF_Min 24.00 24.00 24.00 MHz CLKOUT_FREQ_1X_LF_Max 230.00 210.00 180.00 MHz CLKOUT_FREQ_2X_LF_Min 48.00 48.00 48.00 MHz CLKOUT_FREQ_2X_LF_Max 450.00 420.00 360.00 MHz CLKOUT_FREQ_DV_LF_Min 1.50 1.50 1.50 MHz CLKOUT_FREQ_DV_LF_Max 150.00 140.00 120.00 MHz CLKOUT_FREQ_FX_LF_Min 24.00 24.00 24.00 MHz CLKOUT_FREQ_FX_LF_Max 260.00 240.00 210.00 MHz CLKIN_FREQ_DLL_LF_Min 24.00 24.00 24.00 MHz CLKIN_FREQ_DLL_LF_Max 230.00 210.00 180.00 MHz CLKIN_FREQ_FX_LF_Min 1.00 1.00 1.00 MHz CLKIN_FREQ_FX_LF_Max 260.00 240.00 210.00 MHz PSCLK_FREQ_LF_Min 0.01 0.01 0.01 MHz PSCLK_FREQ_LF_Max 450.00 420.00 360.00 MHz CLKOUT_FREQ_1X_HF_Min 48.00 48.00 48.00 MHz CLKOUT_FREQ_1X_HF_Max 450.00 420.00 360.00 MHz CLKOUT_FREQ_DV_HF_Min 3.00 3.00 3.00 MHz CLKOUT_FREQ_DV_HF_Max 300.00 280.00 240.00 MHz CLKOUT_FREQ_FX_HF_Min 210.00 210.00 210.00 MHz CLKOUT_FREQ_FX_HF_Max 350.00 320.00 270.00 MHz CLKIN_FREQ_DLL_HF_Min 48.00 48.00 48.00 MHz CLKIN_FREQ_DLL_HF_Max 450.00 420.00 360.00 MHz CLKIN_FRQ_FX_HF_Min 50.00 50.00 50.00 MHz CLKIN_FRQ_FX_HF_Max 350.00 320.00 270.00 MHz PSCLK_FREQ_HF_Min 0.01 0.01 0.01 MHz PSCLK_FREQ_HF_Max 450.00 420.00 360.00 MHz Description Symbol Constraints Units Output Clocks (Low Frequency Mode) CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180 Input Clocks (Low Frequency Mode) CLKIN (using DLL outputs1) CLKIN (using CLKFX outputs) PSCLK Output Clocks (High Frequency Mode) CLK0, CLK180 CLKDV CLKFX, CLKFX180 Input Clocks (High Frequency Mode) CLKIN (using DLL outputs1) CLKIN (using CLKFX outputs) PSCLK Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 27 R Virtex-II 1.5V Field-Programmable Gate Arrays Input Clock Tolerances Table 34: Input Clock Tolerances Speed Grade -6 Constraints Description Symbol FCLKIN Min -5 Max Min -4 Max Min Max Units Input Clock Low/high Pulse Width PSCLK PSCLK_PULSE < 1MHz 25.00 25.00 25.00 ns CLKIN(2) CLKIN_PULSE 1 - 10 MHz 25.00 25.00 25.00 ns 10 - 25 MHz 10.00 10.00 10.00 ns 25 - 50 MHz 5.00 5.00 5.00 ns 50 - 100 MHz 3.00 3.00 3.00 ns 100 - 150 MHz 2.40 2.40 2.40 ns 150 - 200 MHz 2.00 2.00 2.00 ns 200 - 250 MHz 1.80 1.80 1.80 ns 250 - 300 MHz 1.50 1.50 1.50 ns 300 - 350 MHz 1.30 1.30 1.30 ns 350 - 400 MHz 1.15 1.15 1.15 ns > 400 MHz 1.05 1.05 1.05 ns Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN (using DLL outputs1) CLKIN_CYC_JITT_DLL_LF 300 300 300 ps CLKIN (using CLKFX outputs) CLKIN_CYC_JITT_FX_LF 300 300 300 ps Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN (using DLL outputs1) CLKIN_CYC_JITT_DLL_HF 150 150 150 ps CLKIN (using CLKFX outputs) CLKIN_CYC_JITT_FX_HF 150 150 150 ps Input Clock Period Jitter (Low Frequency Mode) CLKIN (using DLL outputs1) CLKIN_PER_JITT_DLL_LF 1 1 1 ns CLKIN (using CLKFX outputs) CLKIN_PER_JITT_FX_LF 1 1 1 ns Input Clock Period Jitter (High Frequency Mode) CLKIN (using DLL outputs1) CLKIN_PER_JITT_DLL_HF 1 1 1 ns CLKIN (using CLKFX outputs) CLKIN_PER_JITT_FX_HF 1 1 1 ns 1 1 1 ns Feedback Clock Path Delay Variation CLKFB off-chip feedback CLKFB_DELAY_VAR_EXT Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. Specification also applies to PSCLK. Module 3 of 4 28 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Output Clock Jitter Table 35: Output Clock Jitter Speed Grade Description Symbol Constraints -6 -5 -4 Units Clock Synthesis Period Jitter CLK0 CLKOUT_PER_JITT_0 100 100 100 ps CLK90 CLKOUT_PER_JITT_90 150 150 150 ps CLK180 CLKOUT_PER_JITT_180 150 150 150 ps CLK270 CLKOUT_PER_JITT_270 150 150 150 ps CLK2X, CLK2X180 CLKOUT_PER_JITT_2X 200 200 200 ps CLKDV (integer division) CLKOUT_PER_JITT_DV1 150 150 150 ps CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 300 300 300 ps CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note 1 Note 1 Note 1 ps Notes: 1. Values for this parameter are available on www.xilinx.com. Output Clock Phase Alignment Table 36: Output Clock Phase Alignment Speed Grade -6 -5 -4 50 50 50 ps CLKOUT_PHASE 140 140 140 ps DLL outputs(1) CLKOUT_DUTY_CYCLE_DLL 150 150 150 ps CLKFX outputs CLKOUT_DUTY_CYCLE_FX 100 100 100 ps Description Symbol Constraints Units Phase Offset Between CLKIN and CLKFB CLKIN/CLKFB CLKIN_CLKFB_PHASE Phase Offset Between Any DCM Outputs All CLK* outputs Duty Cycle Precision Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. Specification also applies to PSCLK. DS031-3 (v2.0) November 28, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 29 R Virtex-II 1.5V Field-Programmable Gate Arrays Miscellaneous Timing Parameters Table 37: Miscellaneous Timing Parameters Constraints Description Symbol FCLKIN Speed Grade Units -6 -5 -4 Time Required to Achieve LOCK Using DLL outputs(1) LOCK_DLL LOCK_DLL_60 > 60MHz 20.0 20.0 20.0 ms LOCK_DLL_50_60 50 - 60 MHz 25.0 25.0 25.0 ms LOCK_DLL_40_50 40 - 50 MHz 50.0 50.0 50.0 ms LOCK_DLL_30_40 30 - 40 MHz 90.0 90.0 90.0 ms LOCK_DLL_24_30 24 - 30 MHz 120.0 120.0 120.0 ms LOCK_FX_MIN 10.0 10.0 10.0 ms LOCK_FX_MAX 10.0 10.0 10.0 ms LOCK_DLL_FINE_SHIFT 50.0 50.0 50.0 ms FINE_SHIFT_RANGE 10.0 10.0 10.0 ns DCM_TAP_MIN 30.0 30.0 30.0 ps DCM_TAP_MAX 60.0 60.0 60.0 ps Using CLKFX outputs Additional lock time with fine-phase shifting Fine-Phase Shifting Absolute shifting range Delay Lines Tap delay resolution Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. Specification also applies to PSCLK. Frequency Synthesis Table 38: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 32 CLKFX_DIVIDE 1 32 Parameter Cross Reference Table 39: Parameter Cross Reference Libraries Guide Data Sheet DLL_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_{1X|2X|DV}_LF DFS_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_FX_LF DLL_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_DLL_LF DFS_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_FX_LF DLL_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_{1X|DV}_HF DFS_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_FX_HF DLL_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_DLL_HF DFS_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_FX_HF Module 3 of 4 30 www.xilinx.com 1-800-255-7778 DS031-3 (v2.0) November 28, 2001 Advance Product Specification R Virtex-II 1.5V Field-Programmable Gate Arrays Revision History This section records the change history for this module of the data sheet. Date Version 11/07/00 1.0 Early access draft. 12/06/00 1.1 Initial release. 01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics sections. 01/25/01 1.3 04/23/01 1.5 Revision * * * * * 07/30/01 1.6 * * * 10/02/01 1.7 * * * 10/05/01 1.8 * 10/12/01 1.9 * 11/28/01 2.0 * The data sheet was divided into four modules (per the current style standard). Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Table 18, "Delay Measurement Methodology," on page 16 Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Added TREG32 symbol to Table 23. Skipped v1.4 to sync with other modules. Reverted to traditional double-column format. Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Added values to the Virtex-II Pin-to-Pin Output Parameter Guidelines and Virtex-II Pin-to-Pin Input Parameter Guidelines tables. Added Frequency Synthesis table. Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Updated the speed grade designations used in data sheets, and added Table 13, which shows the current speed grade designation for each device. Corrected the speed grade designation for the XC2V1000 device in Table 13. Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching Characteristics tables. Updated values in Table 3, Table 4, Table 5, Virtex-II Performance Characteristics, and Virtex-II Switching Characteristics tables. Virtex-II Data Sheet The Virtex-II Data Sheet contains the following modules: * * DS031-1, Virtex-II 1.5V FPGAs: Introduction and Ordering Information (Module 1) * DS031-2, Virtex-II 1.5V FPGAs: Functional Description (Module 2) DS031-3 (v2.0) November 28, 2001 Advance Product Specification * DS031-3, Virtex-II 1.5V FPGAs: DC and Switching Characteristics (Module 3) DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables (Module 4) www.xilinx.com 1-800-255-7778 Module 3 of 4 31