INTEGRATED CIRCUITS Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical or sales information, please see: www.xilinx.com XCR5128C 128 macrocell CPLD with enhanced clocking Product specification Supersedes data of 1998 Apr 30 IC27 Data Handbook 1998 Jul 23 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking XCR5128C Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical or sales information, please see: www.xilinx.com FEATURES DESCRIPTION * Industry's first TotalCMOS PLD - both CMOS design and The PZ5128C/PZ5128N CPLD (Complex Programmable Logic Device) is a member of the Fast Zero Power (FZP) family of CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique, the PZ5128C/PZ5128N offers true pin-to-pin speeds of 7.5ns, while simultaneously delivering power that is less than 100A at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD - 70% lower at 50MHz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. process technologies * Fast Zero Power (FZP) design technique provides ultra-low power and very high speed * 5 Volt, In-System Programmable (ISP) using a JTAG interface - - - - - On-chip supervoltage generation ISP commands include: Enable, Erase, Program, Verify Supported by multiple ISP programming platforms 4 pin JTAG interface (TCK, TMS, TDI, TDO) JTAG commands include: Bypass, Idcode * High speed pin-to-pin delays of 7.5ns * Ultra-low static power of less than 100A * Dynamic power that is 70% lower at 50MHz than competing The Philips FZP CPLDs introduce the new patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5ns PAL path with 5 dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. devices * 100% routable with 100% utilization while all pins and all macrocells are fixed * Deterministic timing model that is extremely simple to use * Up to 20 clocks available * Support for complex asynchronous clocking * Innovative XPLA architecture combines high speed with extreme flexibility * 1000 erase/program cycles guaranteed * 20 years data retention guaranteed * Logic expandable to 37 product terms * PCI compliant * Advanced 0.5 E2CMOS process * Security bit prevents unauthorized access * Design entry and verification using industry standard and Philips The PZ5128C/PZ5128N CPLDs are supported by industry standard CAE tools (Cadence, Exemplar Logic, Mentor, OrCAD, Synopsys, Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either MINC or Philips Semiconductors-developed tools. CAE tools * Reprogrammable using industry standard device programmers * Innovative Control Term structure provides either sum terms or product terms in each logic block for: - Programmable 3-State buffer - Asynchronous macrocell register preset/reset - up to 2 asynchronous clocks The PZ5128C/PZ5128N CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The PZ5128C/PZ5128N also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported. * Programmable global 3-State pin facilitates `bed of nails' testing without using logic resources * Available in TQFP and LQFP packages * Available in both Commercial and Industrial grades Table 1. PZ5128C/PZ5128N Features PZ5128C/PZ5128N Usable gates 4000 Maximum inputs 100 Maximum I/Os 96 Number of macrocells 128 Propagation delay (ns) 7.5 Packages 100-pin TQFP 128-pin LQFP PAL is a registered trademark of Advanced Micro Devices, Inc. 1998 Jul 23 2 853-2061 19770 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N ORDERING INFORMATION ORDER CODE DESCRIPTION I/O COUNT DRAWING NUMBER PZ5128CS7BP 100-pin TQFP, 7.5ns tPD, Commercial temp range, 5 volt power supply, 5% 80 SOT386-1 PZ5128CS10BP 100-pin TQFP, 10ns tPD, Commercial temp range, 5 volt power supply, 5% 80 SOT386-1 PZ5128CS12BP 100-pin TQFP, 12ns tPD, Commercial temp range, 5 volt power supply, 5% 80 SOT386-1 PZ5128NS10BP 100-pin TQFP, 10ns tPD, Industrial temp range, 5 volt power supply, 10% 80 SOT386-1 PZ5128NS15BP 100-pin TQFP, 15ns tPD, Industrial temp range, 5 volt power supply, 10% 80 SOT386-1 PZ5128CS7BE 128-pin LQFP, 7.5ns tPD, Commercial temp range, 5 volt power supply, 5% 96 SOT425-1 PZ5128CS10BE 128-pin LQFP, 10ns tPD, Commercial temp range, 5 volt power supply, 5% 96 SOT425-1 PZ5128CS12BE 128-pin LQFP, 12ns tPD, Commercial temp range, 5 volt power supply, 5% 96 SOT425-1 PZ5128NS10BE 128-pin LQFP, 10ns tPD, Industrial temp range, 5 volt power supply, 10% 96 SOT425-1 PZ5128NS15BE 128-pin LQFP, 15ns tPD, Industrial temp range, 5 volt power supply, 10% 96 SOT425-1 From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next. XPLA ARCHITECTURE Figure 1 shows a high level block diagram of a 128 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. MC0 MC1 I/O MC0 LOGIC BLOCK 36 36 16 16 16 16 36 36 LOGIC BLOCK MC15 I/O MC0 LOGIC BLOCK LOGIC BLOCK MC15 I/O 16 16 16 16 ZIA LOGIC BLOCK 36 LOGIC BLOCK MC1 I/O MC15 16 16 16 16 36 36 16 16 16 16 MC0 MC0 I/O I/O MC0 36 MC15 MC1 MC1 MC15 MC0 MC1 I/O MC15 MC0 MC1 MC1 LOGIC BLOCK LOGIC BLOCK MC15 MC1 I/O MC15 SP00464 Figure 1. Philips XPLA CPLD Architecture 1998 Jul 23 3 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N Each macrocell has 5 dedicated product terms from the PAL array. The pin-to-pin tPD of the PZ5128C/PZ5128N device through the PAL array is 7.5ns. If a macrocell needs more than 5 product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2ns. So the total pin-to-pin tPD for the PZ5128C/PZ5128N using 6 to 37 product terms is 9.5ns (7.5ns for the PAL + 2ns for the PLA). Logic Block Architecture Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. The 6 control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. In addition, two of the control terms can be used as clock signals (see Macrocell Architecture section for details). The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. 36 ZIA INPUTS 6 CONTROL TO 16 MACROCELLS 5 PAL ARRAY PLA ARRAY (32) SP00435A Figure 2. Philips XPLA Logic Block Architecture 1998 Jul 23 4 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N are used to control the asynchronous Preset/Reset of the macrocell's flip-flop. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied, and that the Preset/Reset feature for each macrocell can also be disabled. Control terms CT2 and CT3 can be used as a clock signal to the flip-flops of the macrocells, and as the Output Enable of the macrocell's output buffer. Control terms CT4 and CT5 can be used to control the Output Enable of the macrocell's output buffer. Having four dedicated Output Enable control terms ensures that the CoolRunner devices are PCI compliant. The output buffers can also be always enabled or always disabled. All CoolRunner devices also provide a Global Tri-State (GTS) pin, which, when enabled and pulled Low, will 3-State all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails Testing". Macrocell Architecture Figure 3 shows the architecture of the macrocell used in the CoolRunner PZ5128C/PZ5128N. The macrocell can be configured as either a D or T type flip-flop or a combinatorial logic function. A D-type flip-flop is generally more useful for implementing state machines and data buffering while a T-type flip-flop is generally more useful in implementing counters. Each of these flip-flops can be clocked from any one of six sources. Four of the clock sources (CLK0, CLK1, CLK2, CLK3) are connected to low-skew, device-wide clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. Clock 0 (CLK0) is designated as a "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can be used as "synchronous" clocks that are driven by an external source, or as "asynchronous" clocks that are driven by a macrocell equation. CLK0, CLK1, CLK2 and CLK3 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. The other clock sources are two of the six control terms (CT2 and CT3) provided in each logic block. These clocks can be individually configured as either a PRODUCT term or SUM term equation created from the 36 signals available inside the logic block. The timing for asynchronous and control term clocks is different in that the tCO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tSU time is reduced. Please see the application note titled "Understanding CoolRunner Clocking Options" for more detail. There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin feedback path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-Stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated (see the section on Terminations in this data sheet and the Application Note Terminating Unused CoolRunner I/O Pins). The six control terms of each logic block are used to control the asynchronous Preset/Reset of the flip-flops and the enable/disable of the output buffers in each macrocell. Control terms CT0 and CT1 TO ZIA PAL D/T INIT (P or R) GTS GND CT0 CT1 GND CT2 CT3 CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3 Q CT4 CT5 V CC GND PLA SP00558 Figure 3. PZ5128C/PZ5128N Macrocell Architecture 1998 Jul 23 5 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking Simple Timing Model TotalCMOS Design Technique for Fast Zero Power Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and tCO. In other competing architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. Philips is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer CPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 2 showing the IDD vs. Frequency of our PZ5128C/PZ5128N TotalCMOS CPLD (data taken w/eight up/down, loadable 16 bit counters@5V, 25C). tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA INPUT PIN INPUT PIN PZ5128C/PZ5128N REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA D Q OUTPUT PIN REGISTERED tCO OUTPUT PIN GLOBAL CLOCK PIN SP00553 Figure 4. CoolRunner Timing Model 140 120 100 80 IDD (mA) 60 40 20 0 0 20 40 60 80 100 120 FREQUENCY (MHz) SP00617 Figure 5. IDD vs. Frequency @ VDD = 5.0V, 25C Table 2. IDD vs. Frequency VDD = 5.00V FREQUENCY (MHz) 0 1 20 40 60 80 100 120 Typical IDD (mA) 0.048 1.281 23.55 46.93 70.05 92.45 114.4 136.2 1998 Jul 23 6 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N come from the factory with these I/O pins set to perform JTAG functions, but through the software, the final function of these pins can be controlled. If the end application will require the device to be reprogrammed at some future time with ISP, then the pins can be left as dedicated JTAG functions, which means they are not available for use as general purpose I/O pins. However, unlike competing CPLDs, the Philips PZ5128C/PZ5128N allow the macrocells associated with these pins to be used as buried logic when the JTAG/ISP function is enabled. This is the default state for the software, and no action is required to leave these pins enabled for the JTAG/ISP functions. If, however, JTAG/ISP is not required in the end application, the software can specify that this function be turned off and that these pins be used as general purpose I/O. Because the devices initially have the JTAG/ISP functions enabled, the JEDEC file can be downloaded into the device once, after which the JTAG/ISP pins will become general purpose I/O. This feature is good for manufacturing because the devices can be programmed during test and assembly of the end product and yet still use all of the I/O pins after the programming is done. It eliminates the need for a costly, separate programming step in the manufacturing process. Of course, if the JTAG/ISP function is never required, this feature can be turned off in the software and the device can be programmed with an industry-standard programmer, leaving the pins available for I/O functions. Table 4 defines the dedicated pins used by the four mandatory JTAG signals for each of the PZ5128C/PZ5128N package types. JTAG Testing Capability JTAG is the commonly-used acronym for the Boundary Scan Test (BST) feature defined for integrated circuits by IEEE Standard 1149.1. This standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. The Philips PZ5128C/PZ5128N devices use the JTAG Interface for In-System Programming/Reprogramming. Although only a subset of the full JTAG command set is implemented (see Table 5), the devices are fully capable of sitting in a JTAG scan chain. The Philips PZ5128C/PZ5128N's JTAG interface includes a TAP Port defined by the IEEE 1149.1 JTAG Specification. As implemented in the Philips PZ5128C/PZ5128N, the TAP Port includes four of the five pins (refer to Table 3) described in the JTAG specification: TCK, TMS, TDI, and TDO. The fifth signal defined by the JTAG specification is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Philips PZ5128C/PZ5128N saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG interface. Instead, the Philips PZ5128C/PZ5128N supports the test reset functionality through the use of its power up reset circuit, which is included in all Philips CPLDs. The pins associated with the TAP Port should connect to an external pull-up resistor to keep the JTAG signals from floating when they are not being used. In the Philips PZ5128C/PZ5128N, the four mandatory JTAG pins each require a unique, dedicated pin on the device. The devices Table 3. JTAG Pin Description PIN NAME DESCRIPTION TCK Test Clock Output Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively. TMS Test Mode Select Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode operation. TDI Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK. TDO Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is tri-stated if data is not being shifted out of the device. Table 4. PZ5128C/PZ5128N JTAG Pinout by Package Type (PIN NUMBER / MACROCELL #) DEVICE PZ5128C/PZ5128N 100-pin TQFP 128-pin LQFP TCK TMS TDI TDO 62/F15 82/F15 15/C15 21/C15 4/B15 8/B15 73/G15 95/G15 Table 5. PZ5128C/PZ5128N Low-Level JTAG Boundary-Scan Commands INSTRUCTION (Instruction Code) Register Used DESCRIPTION Bypass (1111) Bypass Register Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. The Bypass instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle. Idcode (0001) Boundary-Scan Register Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed circuit board. Thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product. 1998 Jul 23 7 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N 5-Volt, In-System Programming (ISP) Terminations ISP is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment to the end customer. ISP provides substantial benefits in each of the following areas: The CoolRunner PZ5128C/PZ5128N CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS input structures, which can increase the power consumption of the device. The PZ5128C/PZ5128N CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automatically activated by the fitter software for all unused I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the PZ5128C/PZ5128N device be left unconnected. * Design - Faster time-to-market - Debug partitioning and simplified prototyping - Printed circuit board reconfiguration during debug - Better device and board level testing * Manufacturing - Multi-Functional hardware - Reconfigurability for Test - Eliminates handling of "fine lead-pitch" components for programming There are no on-chip pull-down structures associated with the dedicated input pins. Philips recommends that any unused dedicated inputs be terminated with external 10k pull-up resistors. These pins can be directly connected to VCC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. - Reduced Inventory and manufacturing costs - Improved quality and reliability * Field Support - Easy remote upgrades and repair - Support for field configuration, re-configuration, and customization When using the JTAG/ISP functions, it is also recommended that 10k pull-up resistors be used on each of the pins associated with the four mandatory JTAG signals. Letting these signals float can cause the voltage on TMS to come close to ground, which could cause the device to enter JTAG/ISP mode at unspecified times. See the application notes JTAG and ISP in Philips Devices and Terminating CoolRunner I/O Pins for more information. The Philips PZ5128C/PZ5128N allows for 5-Volt, in-system programming/reprogramming of its EEPROM cells via its JTAG interface. An on-chip charge pump eliminates the need for externally-provided supervoltages, so that the PZ5128C/PZ5128N may be easily programmed on the circuit board using only the 5-volt supply required by the device for normal operation. A set of low-level ISP basic commands implemented in the PZ5128C/PZ5128N enable this feature. The ISP commands implemented in the Philips PZ5128C/PZ5128N are specified in Table 6. Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has already been given for a preceding ISP command. Table 6. Low Level ISP Commands INSTRUCTION (Register Used) INSTRUCTION CODE Enable (ISP Shift Register) 1001 Enables the Erase, Program, and Verify commands. Using the ENABLE instruction before the Erase, Program, and Verify instructions allows the user to specify the outputs the device using the JTAG Boundary-Scan SAMPLE/PRELOAD command. Erase (ISP Shift Register) 1010 Erases the entire EEPROM array. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. Program (ISP Shift Register) 1011 Programs the data in the ISP Shift Register into the addressed EEPROM row. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. Verify (ISP Shift Register) 1100 Transfers the data from the addressed row to the ISP Shift Register. The data can then be shifted out and compared with the JEDEC file. The outputs during this operation can be defined by the user. 1998 Jul 23 DESCRIPTION 8 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N * Automated Test Equipment * Third party Programmers * High-End ISP Tools JTAG and ISP Interfacing A number of industry-established methods exist for JTAG/ISP interfacing with CPLD's and other integrated circuits. The Philips PZ5128C/PZ5128N supports the following methods: * PC Parallel Port * Workstation or PC Serial Port * Embedded Processor For more details on JTAG and ISP for the PZ5128C/PZ5128N, refer to the related application note: JTAG and ISP in Philips CPLDs. Table 7. Programming Specifications SYMBOL PARAMETER MIN. MAX. UNIT DC Parameters VCCP VCC supply program/verify ICCP ICC limit program/verify 4.5 5.5 V 200 mA VIH Input voltage (High) VIL Input voltage (Low) 0.8 V VSOL Output voltage (Low) 0.5 V VSOH Output voltage (High) 2.4 V TDO_IOL Output current (Low) 12 mA TDO_IOH Output current (High) -12 mA 2.0 V AC Parameters fMAX TCK maximum frequency 10 MHz PWE Pulse width erase 100 ms PWP Pulse width program 10 ms PWV Pulse width verify 10 s INIT Initialization time 100 s TMS_SU TMS setup time before TCK 10 ns TDI_SU TDI setup time before TCK 10 ns TMS_H TMS hold time after TCK 20 ns TDI_H TDI hold time after TCK 20 ns TDO_CO TDO valid after TCK 30 ns ABSOLUTE MAXIMUM RATINGS1 SYMBOL MIN. MAX. UNIT VDD Supply voltage2 PARAMETER -0.5 7.0 V VI Input voltage -1.2 VDD+0.5 V VOUT Output voltage -0.5 VDD+0.5 V IIN Input current -30 30 mA IOUT Output current -100 100 mA TJ Maximum junction temperature -40 150 C Tstr Storage temperature -65 150 C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage must rise monotonically. OPERATING RANGE PRODUCT GRADE 1998 Jul 23 TEMPERATURE VOLTAGE Commercial 0 to +70C 5.0 5% V Industrial -40 to +85C 5.0 10% V 9 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0C Tamb +70C; 4.75V VDD 5.25V PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT 0.8 V VIL Input voltage low VDD = 4.75V VIH Input voltage high VDD = 5.25V VI Input clamp voltage VDD = 4.75V, IIN = -18mA -1.2 V VOL Output voltage low VDD = 4.75V, IOL = 12mA 0.5 V VOH Output voltage high VDD = 4.75V, IOH = -12mA 2.4 II Input leakage current VIN = 0 to VDD -10 10 A IOZ 3-Stated output leakage current VIN = 0 to VDD -10 10 A IDDQ1 Standby current IDDD1, 2 Dynamic current current3 2.0 V V VDD = 5.25V, Tamb = 0C 100 A VDD = 5.25V, Tamb = 0C @ 1MHz 3 mA VDD = 5.25V, Tamb = 0C @ 50MHz 75 mA -200 mA 8 pF 12 pF IOS Short circuit output CIN Input pin capacitance3 1 pin at a time for no longer than 1 second Tamb = 25C, f = 1MHz CCLK Clock input capacitance3 Tamb = 25C, f = 1MHz -50 5 CI/O I/O pin capacitance3 Tamb = 25C, f = 1MHz 10 pF NOTES: 1. See Table 2 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested. AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES Commercial: 0C Tamb +70C; 4.75V VDD 5.25V SYMBOL PARAMETER tPD_PAL 7 10 12 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Propagation delay time, input (or feedback node) to output through PAL 2 7.5 2 10 2 12 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 9.5 3 12 3 14.5 ns tCO Clock to out (global synchronous clock from pin) 2 5.5 2 7 2 8 ns tSU_PAL Setup time (from input or feedback node) through PAL 4.5 7 8 tSU_PLA Setup time (from input or feedback node) through PAL + PLA 6.5 9 10.5 tH Hold time tCH Clock High time 3 4 4 tCL Clock Low time 3 4 4 tR Input Rise time 20 20 20 tF Input Fall time 20 20 20 fMAX1 Maximum FF toggle rate2 fMAX2 Maximum internal frequency2 fMAX3 Maximum external frequency2 tBUF Output buffer delay time tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 2 6 2 8.5 tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA 3 8 3 10.5 tCF Clock to internal feedback node delay time 4 5.5 6.5 ns tINIT Delay from valid VDD to valid reset 50 50 50 s tER Input to output disable2, 3 9 12 15 ns tEA Input to output valid2 9 12 15 ns tRP Input to register preset2 11 12.5 15 ns 11 12.5 15 ns 0 1/(tCH + tCL) ns 0 ns ns ns ns ns 167 125 125 MHz 1/(tSUPAL + tCF) 111 80 69 MHz 1/(tSUPAL + tCO) 95 71 63 1.5 reset2 tRR Input to register NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1998 Jul 23 0 ns 10 1.5 MHz 1.5 ns 2 10.5 ns 3 13 ns Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: -40C Tamb +85C; 4.5V VDD 5.5V SYMBOL PARAMETER TEST CONDITIONS MIN. VIL Input voltage low VDD = 4.5V VIH Input voltage high VDD = 5.5V VI Input clamp voltage VOL Output voltage low VDD = 4.5V, IOL = 12mA VOH Output voltage high VDD = 4.5V, IOH = -12mA 2.4 II Input leakage current VIN = 0 to VDD IOZ 3-Stated output leakage current VIN = 0 to VDD IDDQ1 Standby current V 2.0 V -1.2 V 0.5 V -10 10 A -10 10 A V VDD = 5.5V, Tamb = -40C 125 A VDD = 5.5V, Tamb = -40C @ 1MHz 4 mA Dynamic current IOS Short circuit output current3 CIN Input pin capacitance3 Tamb = 25C, f = 1MHz CCLK Clock input capacitance3 Tamb = 25C, f = 1MHz I/O pin UNIT 0.8 VDD = 4.5V, IIN = -18mA IDDD1, 2 CI/O MAX. VDD = 5.5V, Tamb = -40C @ 50MHz 1 pin at a time for no longer than 1 second capacitance3 -50 80 mA -230 mA 8 pF 12 pF 10 pF 5 Tamb = 25C, f = 1MHz NOTES: 1. See Table 2 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested. AC ELECTRICAL CHARACTERISTICS1 FOR INDUSTRIAL GRADE DEVICES Industrial: -40C Tamb +85C; 4.5V VDD 5.5V SYMBOL 10 PARAMETER 15 MIN. MAX. MIN. MAX. UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 10 2 15 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 12 3 17.5 ns tCO Clock to out (global synchronous clock from pin) 2 7 2 8 ns tSU_PAL Setup time (from input or feedback node) through PAL 8 8 ns tSU_PLA Setup time (from input or feedback node) through PAL + PLA 10 10.5 ns tH Hold time tCH Clock High time 5 5 tCL Clock Low time 5 5 tR Input Rise time tF Input Fall time fMAX1 Maximum FF toggle rate2 fMAX2 Maximum internal frequency2 fMAX3 Maximum external frequency2 tBUF Output buffer delay time tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 2 8.5 tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA 3 10.5 tCF Clock to internal feedback node delay time 6 6.5 ns tINIT Delay from valid VDD to valid reset 50 50 s tER Input to output disable2, 3 15 15 ns tEA Input to output valid2 15 15 ns tRP Input to register preset2 15 17 ns tRR Input to register reset2 15 17 ns 0 20 ns ns ns 20 20 1/(tCH + tCL) 20 ns ns 100 100 MHz 1/(tSUPAL + tCF) 71 69 MHz 1/(tSUPAL + tCO) 66 63 1.5 NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1998 Jul 23 0 11 MHz 1.5 ns 2 13.5 ns 3 16 ns Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N SWITCHING CHARACTERISTICS VDD S1 COMPONENT VALUES R1 390 R2 390 C1 35pF MEASUREMENT S1 S2 tPZH Open Closed tPZL Closed Closed tP Closed Closed R1 VIN VOUT R2 C1 S2 NOTE: For tPHZ and tPLZ C = 5pF, and 3-State levels are measured 0.5V from steady state active level. SP00618 VOLTAGE WAVEFORM VDD = 5V, 25C 7.0 +3.0V 6.9 90% 6.8 10% 6.7 tPD_PAL (ns) 0V 6.6 tR tF 1.5ns 1.5ns 6.5 SP00368 6.4 MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. 6.3 Input Pulses 6.2 6.1 6.0 1 2 4 8 12 16 NUMBER OF OUTPUTS SWITCHING SP00619 Figure 6. tPD_PAL vs. Outputs Switching Table 8. tPD_PAL vs. Number of Outputs Switching VDD = 5.00V, 25C NUMBER OF OUTPUTS 1 2 4 8 12 16 Typical (ns) 6.362 6.432 6.49 6.562 6.63 6.705 1998 Jul 23 12 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N PIN DESCRIPTIONS 100-Pin Thin Quad Flat Package 100 128-Pin Low Profile Quad Flat Package 128 76 1 75 1 103 102 TQFP LQFP 25 51 38 26 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function I/O-A2 I/O-A0 VDD I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 VDD I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C2 I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D10 I/O-D8 I/O-D7 I/O-D5 VDD Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 65 50 Function I/O-D4 I/O-D2 I/O-D0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E13 I/O-E15 VDD I/O-F0 I/O-F2 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G4 VDD I/O-G5 I/O-G7 Pin 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function I/O-G8 I/O-G10 I/O-G12 I/O-G13 I/O-G15 (TDO) GND I/O-H0 I/O-H2 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VDD I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SP00485 Function I/O-A3 I/O-A2 I/O-A0 NC NC NC VDD I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B11 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B3 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 I/O-C11 VDD I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C3 I/O-C2 NC NC NC I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D11 I/O-D10 I/O-D8 39 64 Pin 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Function I/O-D7 I/O-D5 VDD I/O-D4 I/O-D3 I/O-D2 I/O-D0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E3 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E11 I/O-E12 I/O-E13 I/O-E15 VDD I/O-F0 NC NC NC I/O-F2 I/O-F3 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F11 I/O-F12 I/O-F13 I/O-F15(TCK) I/O-G0 I/O-G2 I/O-G3 I/O-G4 Pin 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Function VDD I/O-G5 I/O-G7 I/O-G8 I/O-G10 I/O-G11 I/O-G12 I/O-G13 I/O-G15 (TDO) GND NC NC NC I/O-H0 I/O-H2 I/O-H3 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VDD I/O-H11 I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 I/O-A11 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4 SP00469A 1998 Jul 23 13 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N Package Thermal Characteristics Philips Semiconductors uses the Temperature Sensitive Parameter (TSP) method to test thermal resistance. This method meets Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC Package Databook. Thermal resistance varies slightly as a function of input power. As input power increases, thermal resistance changes approximately 5% for a 100% change in power. PERCENTAGE REDUCTION IN JA (%) 10 20 Figure 7 is a derating curve for the change in JA with airflow based on wind tunnel measurements. It should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. Also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. 30 40 PLCC/ QFP 50 JA Package 100-pin TQFP 47.4 C/W 128-pin LQFP 45.0 C/W 0 0 1 2 3 4 5 AIR FLOW (m/s) SP00419A Figure 7. Average Effect of Airflow on JA 1998 Jul 23 14 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking TQFP100: plastic thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm 1998 Jul 23 15 PZ5128C/PZ5128N SOT386-1 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm 1998 Jul 23 16 SOT425-1 Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking NOTES 1998 Jul 23 17 PZ5128C/PZ5128N Philips Semiconductors Product specification 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Date of release: 07-98 Document order number: 1998 Jul 23 18 9397 750 04177