SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3,
Elite Platform™ Precision Super-TCXO
Description
The SiT5356 is a ±100 ppb precision MEMS Super-TCXO
that is fully compliant to Telcordia GR-1244-CORE Stratum
3 oscillator specifications. Engineered for best dynamic
performance, the SiT5356 is ideal for high reliability
telecom, wireless and networking, industrial, precision
GNSS and audio/video applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5356 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5356 offers three device configurations that can be
ordered using Ordering Codes for:
The SiT5356 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to Manufacturing Guideline for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Features
◼ Any frequency from 1 MHz to 60 MHz in 1 Hz steps
◼ Factory programmable options for short lead time
◼ Best dynamic stability under airflow, thermal shock
▪ ±100 ppb stability across temperature
▪ ±1 ppb/C typical frequency slope (ΔF/ΔT)
▪ 1.5e-11 ADEV at 10 second averaging time
◼ -40°C to +105°C operating temperature
◼ No activity dips or micro jumps
◼ Resistant to shock, vibration and board bending
◼ On-chip regulators eliminate the need for external LDOs
◼ Digital frequency pulling (DCTCXO) via I2C
▪ Digital control of output frequency and pull range
▪ Up to ±3200 ppm pull range
▪ Frequency pull resolution down to 5 ppt
◼ 2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
◼ LVCMOS or clipped sinewave output
◼ RoHS and REACH compliant
◼ Pb-free, Halogen-free, Antimony-free
Applications
◼ 4G/5G radio, Small cell
◼ IEEE1588 boundary and grandmaster clocks
◼ Carrier-grade routers and switches
◼ Synchronous Ethernet
◼ Optical transport – SONET/SDH, OTN, Stratum 3
◼ DOCSIS 3.x remote PHY
◼ GPS disciplined oscillators
◼ Precision GNSS systems
◼ Test and measurement
Block Diagram
Figure 1. SiT5356 Block Diagram
5.0 mm x 3.2 mm Package Pinout
OE / VC / NC 1
2
3
456
7
8
910
SCL / NC
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA / NC
Figure 2. Pin Assignments (Top view)
(Refer to Table 13 for Pin Descriptions)
Rev 1.07
May 10, 2020
www.sitime.com
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 2 of 41
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Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the
SiTime Part Number Decoder.
Part
Family Silicon
Revision
Letter
Pull Range – DCTCXO mode only
"T": ±6.25 ppm
"R": ±10 ppm
"Q": ±12.5 ppm
"M": ±25 ppm
"B": ±50 ppm
"C": ±80 ppm
"E": ±100 ppm
"F": ±125 ppm
"G": ±150 ppm
"H": ±200 ppm
"X": ±400 ppm
"L": ±600 ppm
"Y": ±800 ppm
"S": ±1200 ppm
"Z": ±1600 ppm
"U": ±3200 ppm
Supply Voltage
"25": 2.5 V ±10%
"28": 2.8 V ±10%
"30": 3.0 V ±10%
"33": 3.3 V ±10%
Frequency
1.000000 MHz to 60.000000 MHz
Pin 1 Function – DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Temperature Range
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
Output Waveform
"-": LVCMOS[1]
"C": Clipped Sinewave
Frequency Stability
"Q": for ±0.1 ppm
"P": for ±0.2 ppm
"N": for ±0.25 ppm
Package Size
"F": 5.0 mm x 3.2 mm Pin 1 Function – TCXO mode only
"E": Output Enable
"N": No Connect
I2C Address Mode – DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I2C address. When the I2C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I2C pin addressable mode. Address is set by
the logic on A0 pin.
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
"X": 12 mm Tape & Reel, 250 u reel
(blank): bulk[2]
SiT5356AC - FQ - 33 E 0 - 19.123456 T
SiT5356AC - FQ - 33 V T - 19.123456 T
SiT5356AC - FQG33 J R - 19.123456 T
TCXO
VCTCXO
DCTCXO
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact SiTime.
2. Bulk is available for sampling only.
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 3 of 41
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TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features ....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics .............................................................................................................................................................. 4
Device Configurations and Pin-outs ........................................................................................................................................... 10
Pin-out Top Views............................................................................................................................................................... 10
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 11
Waveforms ................................................................................................................................................................................. 13
Timing Diagrams ........................................................................................................................................................................ 14
Stability Diagrams ...................................................................................................................................................................... 14
Typical Performance Plots ......................................................................................................................................................... 15
Architecture Overview ................................................................................................................................................................ 19
Frequency Stability ............................................................................................................................................................. 19
Output Frequency and Format ............................................................................................................................................ 19
Output Frequency Tuning ................................................................................................................................................... 19
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 20
Device Configurations ................................................................................................................................................................ 20
TCXO Configuration ........................................................................................................................................................... 20
VCTCXO Configuration ...................................................................................................................................................... 21
DCTCXO Configuration ...................................................................................................................................................... 22
VCTCXO-Specific Design Considerations ................................................................................................................................. 23
Linearity .............................................................................................................................................................................. 23
Control Voltage Bandwidth ................................................................................................................................................. 23
FV Characteristic Slope KV ................................................................................................................................................. 23
Pull Range, Absolute Pull Range ........................................................................................................................................ 24
DCTCXO-Specific Design Considerations ................................................................................................................................. 25
Pull Range and Absolute Pull Range .................................................................................................................................. 25
Output Frequency ............................................................................................................................................................... 26
I2C Control Registers .......................................................................................................................................................... 28
Register Descriptions .......................................................................................................................................................... 28
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 28
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 29
Register Address: 0x02. DIGITAL PULL RANGE CONTROL[18] ........................................................................................ 30
Serial Interface Configuration Description .......................................................................................................................... 31
Serial Signal Format ........................................................................................................................................................... 31
Parallel Signal Format ........................................................................................................................................................ 32
Parallel Data Format ........................................................................................................................................................... 32
I2C Timing Specification ...................................................................................................................................................... 34
I2C Device Address Modes ................................................................................................................................................. 35
Schematic Example ............................................................................................................................................................ 36
Dimensions and Patterns ........................................................................................................................................................... 37
Layout Guidelines ...................................................................................................................................................................... 38
Manufacturing Guidelines .......................................................................................................................................................... 38
Additional Information ................................................................................................................................................................ 39
Revision History ......................................................................................................................................................................... 40
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 4 of 41
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Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3 V Vdd.
Table 1. Output Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Coverage
Nominal Output Frequency Range
F_nom
1
–
60
MHz
Temperature Range
Operating Temperature Range
T_use
-20
–
+70
°C
Extended Commercial, ambient temperature
-40
–
+85
°C
Industrial, ambient temperature
-40
–
+105
°C
Extended Industrial, ambient temperature
Frequency Stability – Stratum 3+ Grade
Frequency Stability over
Temperature
F_stab
–
–
±0.1
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range, in TCXO, DCTCXO, or VCTCXO
(VCTCXO with ±6.25 ppm pull range, Vc=Vdd/2)
Initial Tolerance
F_init
–
–
±0.3
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
F_Vdd
–
±0.5
±2.5
ppb
Vdd ±5%
Output Load Sensitivity
F_load
–
±0.05
±0.4
ppb
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
Frequency vs. Temperature Slope
ΔF/ΔT
–
±0.9
±2
ppb/°C
0.5°C/min temperature ramp rate, -20 to 85°C
–
±1
±3.5
ppb/°C
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.9
±3.3
ppb/°C
0.5°C/min temperature ramp rate, 85 to 105°C
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
±0.008
±0.02
ppb/s
0.5°C/min temperature ramp rate, -20 to 85°C
–
±0.01
±0.03
ppb/s
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.008
±0.028
ppb/s
0.5°C/min temperature ramp rate, 85 to 105°C
24-hour holdover stability
F_24_Hold
–
–
±0.15
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
Hysteresis Over Temperature
F_hys
–
±25
±42
ppb
-40 to 105°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 19, contact SiTime for lower hysteresis
–
±15
±27
ppb
-40 to 85°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 19, contact SiTime for lower hysteresis
–
±10
±20
ppb
-20 to 70°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 19, contact SiTime for lower hysteresis
One-Day Aging
F_1d
–
±0.5
±2.0
ppb
At 85°C, after 30-days of continued operation. Aging is
measured with respect to day 31.
One-Year Aging
F_1y
–
±57
±230
ppb
At 85°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
5-Year Aging
F_5y
–
±73
±320
ppb
10-Year Aging
F_10y
–
±80
±360
ppb
20-Year Aging
F_20y
–
±87
±400
ppb
Allan deviation
ADEV
–
1.5e-11
–
–
10 second averaging time [3]
Frequency Stability – Stratum 3 Grade
Frequency Stability over
Temperature
F_stab
–
–
±0.2
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
–
–
±0.25
ppm
Initial Tolerance
F_init
–
–
±1
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
F_Vdd
–
±3.0
±6.5
ppb
Vdd ±5%
Output Load Sensitivity
F_load
–
±0.3
±1.1
ppb
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
Frequency vs. Temperature Slope
ΔF/ΔT
–
±6.4
±10
ppb/°C
-40 to 105°C
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
±0.05
±0.08
ppb/s
0.5°C/min temperature ramp rate
24-hour holdover stability
F_24_Hold
–
–
±0.28
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
One-Day Aging
F_1d
–
±3
±5
ppb
At 25°C, after 30-days of continued operation. Aging is
measured with respect to day 31
One-Year Aging
F_1y
–
±1
–
ppm
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
20-Year Aging
F_20y
–
±2
–
ppm
20-Year Total Stability
F_tot_20y
–
–
±4.6
ppm
Complies with Stratum 3 per GR-1244-CORE. Actual
performance is better
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 5 of 41
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Table 1. Output Characteristics (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
LVCMOS Output Characteristics
Duty Cycle
DC
45
–
55
%
Rise/Fall Time
Tr, Tf
0.8
1.2
1.9
ns
10% - 90% Vdd
Output Voltage High
VOH
90%
–
–
Vdd
IOH = +3 mA
Output Voltage Low
VOL
–
–
10%
Vdd
IOL = -3 mA
Output Impedance
Z_out_c
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.3 V
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.0 V
–
18
–
Ohms
Impedance looking into output buffer, Vdd = 2.8 V
–
19
–
Ohms
Impedance looking into output buffer, Vdd = 2.5 V
Clipped Sinewave Output Characteristics
Output Voltage Swing
V_out
0.8
–
1.2
V
Clipped sinewave output, 10 kΩ || 10 pF ±10%
Rise/Fall Time
Tr, Tf
–
3.5
4.6
ns
20% - 80% Vdd, F_nom = 19.2 MHz
Start-up Characteristics
Start-up Time
T_start
–
2.5
3.5
ms
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0 V to
Vdd
Output Enable Time
T_oe
–
–
680
ns
F_nom = 10 MHz. See Timing Diagrams section below
Time to Rated Frequency Stability
T_stability
–
5
45
ms
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value.
Vdd ramp time = 100 µs
Note:
3. Measured 2 hours after startup in a temperature chamber with a constant temperature in still air.
Table 2. DC Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Supply Voltage
Supply Voltage
Vdd
2.25
2.5
2.75
V
Contact SiTime for 2.25 V to 3.63 V continuous supply
voltage support
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
Current Consumption
Current Consumption
Idd
–
44
53
mA
F_nom = 19.2 MHz, No Load, TCXO and DCTCXO modes
–
48
57
mA
F_nom = 19.2 MHz, No Load, VCTCXO mode
OE Disable Current
I_od
–
43
51
mA
OE = GND, output weakly pulled down. TCXO, DCTCXO
–
47
55
mA
OE = GND, output weakly pulled down. VCTCXO mode
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 6 of 41
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Table 3. Input Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Input Characteristics – OE Pin
Input Impedance
Z_in
75
–
–
kΩ
Internal pull up to Vdd
Input High Voltage
VIH
70%
–
–
Vdd
Input Low Voltage
VIL
–
–
30%
Vdd
Frequency Tuning Range – Voltage Control or I2C mode
Pull Range
PR
±6.25
–
–
ppm
VCTCXO mode. Contact SiTime for ±12.5 and ±25 ppm
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
–
–
ppm
DCTCXO mode
Absolute Pull Range[3]
APR
±5.31
–
–
ppm
±0.1 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.05
–
–
ppm
±0.2 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.00
–
–
ppm
±0.25 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
Upper Control Voltage
VC_U
90%
–
–
Vdd
VCTCXO mode
Lower Control Voltage
VC_L
–
–
10%
Vdd
VCTCXO mode
Control Voltage Input Impedance
VC_z
8
–
–
MΩ
VCTCXO mode
Control Voltage Input Bandwidth
VC_bw
–
10
–
kHz
VCTCXO mode. Contact SiTime for other bandwidth
options
Frequency Control Polarity
F_pol
Positive
VCTCXO mode
Pull Range Linearity
PR_lin
–
0.5
1.0
%
VCTCXO mode
I2C Interface Characteristics, 200 Ohm, 550 pF (Max I2C Bus Load)
Bus Speed
F_I2C
≤ 400
kHz
-40 to 105°C
≤ 1000
kHz
-40 to 85°C
Input Voltage Low
VIL_I2C
–
–
30%
Vdd
DCTCXO mode
Input Voltage High
VIH_I2C
70%
–
–
Vdd
DCTCXO mode
Output Voltage Low
VOL_I2C
–
–
0.4
V
DCTCXO mode
Input Leakage current
IL
0.5
–
24
µA
0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
Input Capacitance
CIN
–
–
5
pF
DCTCXO mode
Note:
4. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 17 for APR with respect to other pull range options.
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 7 of 41
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Table 4. Jitter & Phase Noise – LVCMOS, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.48
ps
F_nom = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
0.8
1.1
ps
F_nom = 10 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6
9
ps
F_nom = 10 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
–
-80
-74
dBc/Hz
F_nom = 10 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-108
-102
dBc/Hz
100 Hz offset
–
-127
-123
dBc/Hz
1 kHz offset
–
-148
-145
dBc/Hz
10 kHz offset
–
-154
-151
dBc/Hz
100 kHz offset
–
-154
-150
dBc/Hz
1 MHz offset
–
-167
-163
dBc/Hz
5 MHz offset
–
-168
-164
dBc/Hz
Spurious
T_spur
–
-112
-105
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets
Table 5. Jitter & Phase Noise – Clipped Sinewave, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.45
ps
F_nom = 19.2 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.48
ps
F_nom = 60 MHz, Integration bandwidth = 12 kHz to 20 MHz
Phase Noise
1 Hz offset
–
-74
-68
dBc/Hz
F_nom = 19.2 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-102
-97
dBc/Hz
100 Hz offset
–
-121
-117
dBc/Hz
1 kHz offset
–
-142
-140
dBc/Hz
10 kHz offset
–
-148
-146
dBc/Hz
100 kHz offset
–
-149
-145
dBc/Hz
1 MHz offset
–
-162
-158
dBc/Hz
5 MHz offset
–
-164
-159
dBc/Hz
Spurious
T_spur
–
-109
-104
dBc
F_nom = 19.2 MHz, 1 kHz to 5 MHz offsets
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 8 of 41
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Table 6. Jitter & Phase Noise – LVCMOS, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.50
ps
F_nom = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
0.8
1.1
ps
F_nom = 10 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6
9
ps
F_nom = 10 MHz, population 1 k, measured as absolute value
Phase Noise
1 Hz offset
–
-80
-74
dBc/Hz
F_nom = 10 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-108
-102
dBc/Hz
100 Hz offset
–
-127
-123
dBc/Hz
1 kHz offset
–
-148
-145
dBc/Hz
10 kHz offset
–
-154
-151
dBc/Hz
100 kHz offset
–
-154
-150
dBc/Hz
1 MHz offset
–
-167
-162
dBc/Hz
5 MHz offset
–
-168
-163
dBc/Hz
Spurious
T_spur
–
-112
-101
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets, Vdd = 2.5 V
–
-112
-106
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets,
Vdd = 2.8 V, 3.0 V, 3.3 V
Table 7. Jitter & Phase Noise – Clipped Sinewave, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.46
ps
F_nom = 19.2 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.50
ps
F_nom = 60 MHz, Integration bandwidth = 12 kHz to 20 MHz
Phase Noise
1 Hz offset
–
-74
-68
dBc/Hz
F_nom = 19.2 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-102
-97
dBc/Hz
100 Hz offset
–
-121
-117
dBc/Hz
1 kHz offset
–
-142
-140
dBc/Hz
10 kHz offset
–
-148
-146
dBc/Hz
100 kHz offset
–
-149
-145
dBc/Hz
1 MHz offset
–
-162
-158
dBc/Hz
5 MHz offset
–
-164
-159
dBc/Hz
Spurious
T_spur
–
-109
-103
dBc
F_nom = 19.2 MHz, 1 kHz to 5 MHz offsets
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 9 of 41
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Table 8. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Test Conditions
Value
Unit
Storage Temperature
-65 to 125
°C
Continuous Power Supply Voltage Range (Vdd)
-0.5 to 4
V
Human Body Model (HBM) ESD Protection
JESD22-A114
2000
V
Soldering Temperature (follow standard Pb-free soldering guidelines)
260
°C
Junction Temperature[5]
130
°C
Input Voltage, Maximum
Any input pin
Vdd + 0.3
V
Input Voltage, Minimum
Any input pin
-0.3
V
Note:
5. Exceeding this temperature for an extended period of time may damage the device.
Table 9. Thermal Considerations[6]
Package
JA[7] (°C/W)
JC, Bottom (°C/W)
Ceramic 5.0 mm x 3.2 mm
54
15
Note:
6. Measured in still air. Refer to JESD51 for θJA and θJC definitions.
7. Devices soldered on a JESD51 2s2p compliant board.
Table 10. Maximum Operating Junction Temperature[8]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
105°C
115°C
Note:
8. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 11. Environmental Compliance
Parameter
Test Conditions
Value
Unit
Mechanical Shock Resistance
MIL-STD-883F, Method 2002
30000
g
Mechanical Vibration Resistance
MIL-STD-883F, Method 2007
70
g
Temperature Cycle
JESD22, Method A104
–
–
Solderability
MIL-STD-883F, Method 2003
–
–
Moisture Sensitivity Level
MSL1 @260°C
–
–
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 10 of 41
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Device Configurations and Pin-outs
Table 12. Device Configurations
Configuration
Pin 1
Pin 5
I2C Programmable Parameters
TCXO
OE/NC
NC
–
VCTCXO
VC
NC
–
DCTCXO
OE/NC
A0/NC
Frequency Pull Range, Frequency Pull Value, Output Enable control
Pin-out Top Views
OE/NC 1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 3. TCXO
VC 1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 4. VCTCXO
OE / NC 1
2
3
456
7
8
910
SCL
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA
Figure 5. DCTCXO
Table 13. Pin Description
Pin
Symbol
I/O
Internal Pull-up/Pull Down
Resistor
Function
1
OE/NC/VC
OE – Input
100 kΩ Pull-Up
H[9]: specified frequency output
L: output is high impedance. Only output driver is disabled
NC[11] – No Connect
–
H or L or Open: No effect on output frequency or other device functions
VC – Input
–
Control Voltage in VCTCXO Mode
2
SCL / NC[11]
SCL – Input
200 kΩ Pull-Up
I2C serial clock input
No Connect
H or L or Open: No effect on output frequency or other device functions
3
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
4
GND
Power
–
Connect to ground
5
A0 / NC[11]
A0 – Input
100 kΩ Pull-Up
Device I2C address when the address selection mode is via the A0 pin.
This pin is NC when the I2C device address is specified in the ordering
code.
A0 Logic Level I2C Address
0 1100010
1 1101010
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
6
CLK
Output
–
LVCMOS, or clipped sinewave oscillator output
7
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
8
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
9
VDD
Power
–
Connect to power supply[1010]
10
SDA / NC[11]
SDA – Input/Output
200 kΩ Pull Up
I2C Serial Data
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions
Notes:
9. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use
the NC option.
10. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the
device, and place the 10 μF capacitor less than 2 inches away.
11. All NC pins can be left floating and do not need to be soldered down.
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 11 of 41
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Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Vdd
OE Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
10µF
0.1µF 9 8 7 6
1 2 3 4
510
Power
Supply
VDD CLK Test Point
Vdd
OE Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10pF
+
-
Figure 6. LVCMOS Test Circuit (OE Function)
Figure 7. Clipped Sinewave Test Circuit (OE Function)
for AC and DC Measurements
10µF
0.1µF
+
-
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Control
Voltage
VC Function
CLK
15pF
(including probe
and fixture
capacitance)
Figure 8. LVCMOS Test Circuit (VC Function)
9 8 7 6
2 3 4
510
Power
Supply
VDD CLK Test Point
1
Control
Voltage
VC Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10pF
10µF
0.1µF
+
-
Figure 9. Clipped Sinewave Test Circuit (VC Function)
for AC and DC Measurements
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating
NC Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
Figure 10. LVCMOS Test Circuit (NC Function)
9 8 7 6
2 3 4
510
Power
Supply
VDD CLK Test Point
10pF
1
Any state
or floating
NC Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10µF
0.1µF
+
-
Figure 11. Clipped Sinewave Test Circuit (NC Function)
for AC and DC Measurements
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 12 of 41
www.sitime.com
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (continued)
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating NC
Function
CLK
SCL
SDA[11]
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
A0/NC
Figure 12. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating NC
Function
CLK
SCL
SDA[11]
10pF 10kΩ
(including probe
and fixture
resistance and
capacitance)
10µF
0.1µF
+
-
A0/NC
Figure 13. Clipped Sinewave Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
9 8 7 6
2 3 4
510
Power
Supply
VDD CLK
10pF
1
Any state
or floating
NC Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10µF
0.1µF
+
-
Test Point
A0/NC
Figure 14. Clipped Sinewave Test Circuit for Phase Noise Measurements, Applies to All Configurations
(NC Function shown for example only)
Note:
12. SDA is open-drain and may require pull-up resistor if not present in I2C test setup.
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 13 of 41
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Waveforms
90 % Vdd
50 % Vdd
10 % Vdd
tr tf
High Pulse
(TH) Low Pulse
(TL)
Period
Figure 15. LVCMOS Waveform Diagram[13]
tr tf
High Pulse
(TH) Low Pulse
(TL)
Period
20 % Vout
50 % Vout
80 % Vout
Vout
Figure 16. Clipped Sinewave Waveform Diagram[13]
Note:
13. Duty Cycle is computed as Duty Cycle = TH/Period.
SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.07
Page 14 of 41
www.sitime.com
Timing Diagrams
90% Vdd Vdd
Vdd Pin
Voltage
CLK Output
T_start
T_start: Time to start from power-off
HZ
Figure 17. Startup Timing
50% Vdd
Vdd
OE Voltage
CLK Output
T_oe
T_oe: Time to re-enable the clock output
HZ
Figure 18. OE Enable Timing (OE Mode Only)
Stability Diagrams
Figure 19. Illustration of hysteresis, where ΔF is max
frequency difference between up and down cycles
across temperature