M29W400DT70N6E - STMicroelectronics

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PRELIMINARY DATA

February 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29W400DT

M29W400DB

4 Mbit (512Kb x8 or 256Kb x16, Boot Block)

3V S upply Flash Mem ory

FEATURES SUMMARY

■SUPPLY VOLTAGE

–V

CC = 2.7V to 3.6V for Program, Erase and

Read

■ACCESS TIME: 45, 55, 70ns

■PRO GRAMMIN G TIME

– 10µs per Byte/Word typical

■11 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Locat ion)

– 2 Parameter and 8 Main Blocks

■PROGRAM/ERASE CONTROLLER

– Embedded Byte/ Word Program algorithms

■ERASE SUSPEND and RESUM E MOD ES

– Read and Program another Block during

Erase Su spend

■UNLOCK BYPASS PROGRAM COMMAND

– Fas ter Production/Batc h Prog ramm ing

■TEMPORARY BLOCK UNPROTECTION

MODE

■LOW POWER CONSUM PTION

– Standby and Autom atic Standby

■100,000 PROGRAM/ERASE CYCL ES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– Top Device Code M29W400DT: 00EEh

– Bottom Device Code M29W400D B: 00E Fh

Figure 1. Packages

TSOP48 (N)

12 x 20mm

TFBGA48 (ZA)

6 x 9mm

FBGA

SO44 (M)

M29W400DT, M 29W400DB
2/36
TABLE OF CONT ENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table  1. Signal Names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TSOP  Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. TFBGA Connect ions (Top view through package).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address In puts (A0 -A17).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
D ata Inputs/Ou tputs (DQ0-DQ7). .  . . . . . .  . . . . . . . . . . .  . . . . . . . . .  . . . .  . . . . . . . . .  . . . . . .  . . . . 1 0
D ata Inputs/Ou tputs (DQ8-DQ14).  . . . . . . . . . . . . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . . . . .10
D ata Input/Output or Address Input (DQ15A-1). . . .  . . . .  . .  . . . .  . . .  . . . .  . .  . . . .  . . . . . . . . . . . . . 10
Chip En able (E).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Out put Enabl e (G).  . . . . .  . . . . . . . . . . . . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . . . . . . 10
W rite Enable (W).  . . . . . . . . . . . . .  . . . .  . . . . . . . . .  . . . .  . . . . . . . . . . . . . . . .  . . . .  . . . . . . . . . . . . 10
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R eady/Busy  Out put (RB). . . . . . . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . .  . . . . 1 0
Byte/W ord Organization  Select (BYTE). . . .  . . . .  . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . 10
VCC Supply Volt age. . . . .  . . . . . .  . . . . . . . . . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . .  . . . . 10
VSS Ground. . . . .  . . . . . . . . . . . . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . . . . . . 10
BUS OPERAT IONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . .  . . . . . . . . .  . . . . . .  . . . .  . . . . . . . . . . . . . .  . . . . . .  . . . . . . . . .  . . . . . .  . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 1 1
Standby .  . . . . . . . .  . . . . . . . . . .  . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . . . . . . 11
Autom at ic Standby. . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . . . . . . . . 11
Special Bu s Ope ratio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ele ctronic Signature. . . .  . . . . . .  . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . . . . . . 11
Block Protection and Blocks Unprotection. . . . . . . .  . . . . . . .  . . . . . . . . . .  . . . . . . . . . . . . . . .  . . . . 11
Table 2. Bus Operations, BYTE = V IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bus Operations, B YTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMAND INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . .  . . . .  . . . . . .  . .  . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto Se lect Command. . .  . . . . . . . . . . . . . .  . . . .  . . . . . . . . .  . . . . . .  . . . .  . . . . . . . . . . . . . .  . . . . . 12
Program Comman d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass C ommand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass R eset Com mand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
C hip Erase Comm and.  . . . . . . . . . . . . . . .  . . . . . . . . . . .  . .  . . . .  . . . . . . . . . . . . . . . .  . . . .  . . . . . . 13
Block Erase  Command..  . . . . . .  . .  . . . .  . . .  . . . .  . .  . . . .  . . . . . . . . . . . . . . . .  . . . .  . . . . . .  . .  . . . . 1 3
Erase S uspend Com ma nd. . . . . . . . . . .  . . .  . . . .  . . . . . . . .  . . . .  . . .  . . . .  . . .  . . . .  . . . . . . . .  . . . . 1 3

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M29W400DT, M29W400DB
Erase Resume Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Protect and Ch ip Unprotect Com mands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table  5. Commands, 16-bit mode, BYT E = VIH  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table  6. Commands, 8-bit mode, BY TE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table  4. Program ,  Erase Times  and Program,  Erase Enduranc e Cycles .  . . . . . . . .  . . . . . . . . . . . 14
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Toggl e Bit (DQ6). .  . . . .  . . . . . . . . . . . . . . . .  . . . .  . . . . . .  . .  . . . . . .  . . . . . . . . . . .  . . . . . . .  . . . . . . 1 6
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 1 6
Alternative Toggle Bit (DQ2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table  7. Status Reg ister Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 7
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Data To ggle Flo wchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table  8. Absolute M aximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table  9. Operating and AC Meas urem ent Conditions. . .  . . . . . .  . . . . . . . . . .  . . . .  . . . . . . . .  . . . . 19
Figure 10. AC Measurement I/O Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table  10. Device Capacitance. .  . . . . . . . . . . . . . . . . . . . . .  . . . .  . . . . . . . . . . . . . .  . . . . . . . . . . . . 19
Table  11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Read Mode AC Wavef orm s . . .  . . . . . . . . . . .  . .  . . . .  . . . . . . . . . . . . . . . .  . . . .  . . . . . . 21
Table  12. Read AC Characteristics . . . . . . . . . . . . .  . . . .  . . . . . . . . .  . . . . . .  . . . .  . . . . . . . . . . . . . 21
Figure 13. Write AC Waveforms,  Write Enable Controlled .  . . . .  . . .  . . . .  . .  . . . .  . . . . . . . . . . . . . 22
Table  13. Write AC Characteristics, Write Enable Controlled . . .  . . . . . . . . . . . . . . . .  . . . .  . . . . . . 22
Figure 14. Write AC Waveforms, Ch ip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Write AC Characteristics, Chip Ena ble Controlled  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. Reset/Block T emporary Unp rotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Reset/Block T emporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. SO44 - 44 lead Plastic Sm all Outline, 525 mils body width,  Package Outlin e . . . .  . . . . 25
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package  Mechani ca l Data 25
Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline,  12 x 20mm, Package  Outline . .  . . . . . . 26
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm , Package Mechanical Data . 26
Figure 18. TFBGA48 6x9mm – 6x8 bal l array – 0.80mm pit ch, Bottom  View Package Outline . . . 27
Table  18. TFBG A48 6x9 mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table  19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M29W400DT, M 29W400DB

4/36

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Top Boot Block Ad dresse s M29W400DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. Bottom Boot Block Addresses M29W400DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

APPENDIX B. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

In-System Techn ique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. Programmer Techni que Bus Op erations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 30

Figure 19. Progra mmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. Programmer Equ ipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 21. In-System Equ ipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 22. In-System Equ ipment Chip Unprote ct Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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M29W400DT, M29W400DB

SUMMARY DESCRIPTION

The M29W400D is a 4 Mbit (512Kb x8 or 256Kb

x16) non- volatile memory that can be read, erased

and reprogrammed. T hese operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or EPROM.

The memory is divided into blocks that can be

erased independently so it is possible t o preserv e

valid data while old dat a is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. P rogram and Eras e com m ands are wri t-

ten to the Com mand Interface of t he memory. An

on-chip Program/Erase Controller simplifies the

process of program ming or erasing t he memory by

taking care of al l of the speci al operations that are

required to update the memory contents.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Figures 6 and 7, Block Addresses.

The first or la st 64 Kbytes h ave been divide d into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to s tart the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter st orage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enabl e, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in SO44, TSOP48 (12 x

20mm) and TFBGA48 (0.8mm pitch) packages.

The memory is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram Tabl e 1. Signal Names

AI06853

A0-A17

DQ0-DQ14

VCC

M29W400DT

M29W400DB

VSS

DQ15A–1

BYTE

A0-A17 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

(not available on SO44 package)

BYTE Byte/Word Organization Select

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

M29W400DT, M 29W400DB

6/36

Figu re 3. SO C onnections

Note: 1. NC = Not Connected

Figu re 4. TSOP C onnections

Note: 1. NC = Not Connected

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

AI06855

M29W400DT

M29W400DB

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI06854

M29W400DT

M29W400DB

24 25

DQ8

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

7/36

M29W400DT, M29W400DB

Figure 5. TFBGA Connec tions (Top v iew through package)

Note: 1. NC = Not Connected

AI06856

4321

DQ15

A–1

A7A3

DQ10DQ8E

DQ13DQ11DQ9G

VSS

DQ6DQ1VSS

DQ14

A12

NCA17A4

A14A10NCNCA6A2

RP A8

DQ4

DQ3

VCC

DQ12

BYTE

A15A11NCA1

A16DQ7DQ5DQ2A0

DQ0

RB W A13

M29W400DT, M 29W400DB

8/36

Figure 6. Block Addresses (x8)

Note: Also see Appe ndi x A, Tabl es 20 and 21 for a f ul l l isting of t he Block Address es.

AI06857

16 KByte

7FFFFh

7C000h

64 KByte

1FFFFh

10000h

64 KByte

0FFFFh

00000h

M29W400DT

Top Boot Block Addresses (x8)

32 KByte

77FFFh

70000h

64 KByte

60000h

6FFFFh

Total of 7

64 KByte Blocks

16 KByte

7FFFFh

70000h 64 KByte

64 KByte

03FFFh

00000h

M29W400DB

Bottom Boot Block Addresses (x8)

32 KByte

6FFFFh

1FFFFh 64 KByte

60000h

10000h

Total of 7

64 KByte Blocks

0FFFFh

08000h

8 KByte

7BFFFh

7A000h

79FFFh

78000h

8 KByte

07FFFh

06000h

05FFFh

04000h

9/36

M29W400DT, M29W400DB

Figure 7. Block Addresses (x16)

Note: Also see Appe ndi x A, T ables 20 and 2 1 f or a full listing of t he B l ock Add res ses.

AI06858

8 KWord

3FFFFh

3E000h

32 KWord

0FFFFh

08000h

32 KWord

07FFFh

00000h

M29W400DT

Top Boot Block Addresses (x16)

16 KWord

3BFFFh

38000h

32 KWord

30000h

37FFFh

Total of 7

32 KWord Blocks

8 KWord

3FFFFh

38000h 32 KWord

32 KWord

01FFFh

00000h

M29W400DB

Bottom Boot Block Addresses (x16)

16 KWord

37FFFh

0FFFFh 32 KWord

30000h

08000h

Total of 7

32 KWord Blocks

07FFFh

04000h

4 KWord

3DFFFh

3D000h

3CFFFh

3C000h

4 KWord

03FFFh

03000h

02FFFh

02000h

M29W400DT, M 29W400DB

10/36

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diag ram, and T able 1, Sign al

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A1 7). The Address Inputs

select the cell s in the memory arra y to access dur-

ing Bus Read operations. During Bus Wri te opera-

tions they control the commands sent to the

Comman d Interface of the internal stat e ma chine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs out put the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the int ernal state

machine.

Data Inputs/Outp ut s (DQ8-DQ 14). The Data In-

puts/Outputs out put the data stored at the selected

address during a Bus Read operati on when BYTE

is High, VIH. When BYTE is Low, VIL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bit s. When reading t he Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 Hi gh will select

the MSB . Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to inc lude this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memor y, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). T he Write Enable, W, controls

the Bus Write operation of the memory’s Com-

ma nd Inte r face.

Reset/Block Temporary Unprotect ( RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to t he memory or

to temporarily u nprotect al l Block s that have been

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, V IH, the memory will be read y for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/ Busy

Output section, Table 15 and Figure 15, Reset/

Temporary Unprot ect AC Charact e ristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to ident ify

when the memory array can be read . Ready/Busy

is high-impedance during Read mode, Auto Selec t

mode and Erase Suspend m ode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes h igh-impeda nc e. See Tabl e 15 and Figure

15, Reset/Temporary Unprotect AC Characteris-

tics.

During Program or Erase operations Ready/Busy

is Low, VOL. Ready/Busy will remain Low during

Read/Reset c ommands or Hardw are Rese ts until

the memory is ready to enter Read mode.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch bet ween t he 8-bit and 16-bit Bus m odes of

the memory. When Byte/Word Organization Se-

lect is Low, VIL, the mem ory is in 8-bit mode, when

it is High , V IH, the memory i s in 16 - bit mo de .

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is dis abled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevent s Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being al t ered will be invalid.

A 0.1µF capacitor should be connected between

the V CC Supply Voltage pin and the VSS Ground

pin to decoupl e the current surges from t he power

supply. The PCB track widths m ust be sufficient to

carry the currents required during program and

erase operat ions, ICC3.

VSS Ground. The VSS Ground is the referenc e for

all voltage measureme nts.

11/36

M29W400DT, M29W400DB

BUS OPERATIONS

There are five s tandard bus operations t hat control

the device. These are Bus Read, Bus Wri te, Out-

put Disable, Standby and Automat ic Standby. See

Tables 2 and 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chi p Enable

or Write Enable are ignored by the memory and do

not affect bus operat ions.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desi red address on the Address

Inputs, appl ying a Low s ig nal, VIL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The Dat a I nputs/Ou tputs will output the

value, see Figure 12, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desire d address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Dat a Input s/Outpu ts a re latched by the Com-

mand Interface on the rising edge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must remai n High, VIH, during th e whole Bus

Write operation. See Figures 13 and 14, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Outp ut Disable. The Data Inputs/Outputs are in

the high im pedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For t he Standby current

level see Table 11, DC Characteristi cs.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til t he operat ion com pletes.

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations. Additional bus opera-

tions can be perform ed to read the Electron ic Sig-

nature and also to apply and remove Block

Protection. These bus operations are intended for

use by programming eq uipm ent a nd are not usu-

ally used in applications. They require VID to be

applied to some pins.

Electronic Sign atur e. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These co des can be re ad by app lying the si gnals

listed in Tables 2 and 3, Bus Operat ions.

Block Protection and Blocks Unprotection.

Each block can be separately protected against

accidental Program or Erase. Protected blocks

can be unprotected t o allow dat a to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming eq uipment and the other for in-system

use. Bloc k Protec t and Chi p Unprot ect operat ions

are described in Appendi x B.

Table 2. Bus Operations, BYTE = VIL

No te: X = VIL or VIH.

Operation E G W Address Inputs

DQ15A–1, A0-A17 Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,

Others VIL or VIH Hi-Z EEh (M29W400DT)

EFh (M29W400DB)

M29W400DT, M 29W400DB

12/36

Table 3. Bus Operations, BYTE = VIH

No te: X = VIL or VIH.

COMMAND INTERFACE

All Bus Write operations t o the memory are in ter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a val id sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the mem ory is in 16-bit or 8-

bit mode. See e ither Table 5, or 6, depending on

the configuration that is being used, for a summary

of the c om m ands.

Read/Reset Comm and. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise s tated. It also resets t he errors in the S tatus

can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. Once the program or eras e o peration

has started the Read/Res et command is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Command. The Auto Select com-

mand i s us ed to read the Man ufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until another com-

mand is issued.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A 0 = VIL and A1 = VIL. The other address bits

may be set to e ither VIL or VIH. The Manufacturer

Code for STMicroelectronics is 0020h.

The Device Code can b e read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to e ither V IL or VIH. The

Device Code for the M29W400DT is 00EEh and

for the M29W 400DB is 00EFh.

Th e Bloc k Protection Status of e ach block c an be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A 12-A1 7 spec ifying t h e address of

th e block. The oth er address bits may be set to ei-

ther VIL or VIH. I f th e addr es sed b lock i s p rot ect ed

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Progra m Command . The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is nev er read and

no error condition is given.

During the program o peration the me mory will ig-

nore all co mmands. I t is not possible t o issue any

command to abort or pause the operation. Typical

program times are given in T able 4. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

Operation E G W Address Inputs

A0-A17 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,

Others VIL or VIH 00EEh (M29W400DT)

00EFh (M29W400DB)

13/36

M29W400DT, M29W400DB

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Comman d. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program c ommand to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass comm and.

Once the Unlock Bypass command has been is-

sued the memo ry will only acce pt the Unl ock By-

pass Program command and the Unlock Bypass

Reset command. The m emory can be read as if in

Read mode.

Unlock Bypass Prog ram Comm an d. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write ope ra tions, the

final write operation latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller.

The Program operation using the Unlock Bypass

Program c ommand behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be program m ed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, w hich l eaves the de vice in Unlo ck By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Comman d. The Unlock

Bypass Re se t comm and can be used t o return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are requir ed to issue the

Unlock Bypass Reset command. Read/Reset

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected th en these are ignored

and all the other blocks are erased. If all of the

blocks a re p rote cted the Ch i p Erase o perat i on ap-

pears to start but will terminate within about 100µs,

leaving the data unchange d. No error co ndition is

given when protected blocks are ignored.

During the erase operation the memory wi l l ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 4. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operatio n has com pleted t he

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’ 1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Wr ite operation using the address of the

additional block. The Bl ock Erase operation st arts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer r estarts when an additional block is select ed.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has start ed the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, l eaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Blo ck Erase ope ra tion the me mory will

ignore all commands except the Erase Suspend

co mmand. Typical b lock e ra se tim es are given in

Table 4. All Bus Read operations during the Block

Erase op eratio n w ill ou t pu t the S t a tus R eg i st er on

the Data Inputs/Outputs. See the section on the

Status Regist er for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selec ted bl ocks to ’1’ . All previous

data in the selected blocks is lost.

Erase Suspend Comm and. The Erase Suspend

Comman d m ay be used to temporari ly suspend a

Block Erase operation and return the memory to

M29W400DT, M 29W400DB

14/36

Read mode. The command requires one Bus

Write operation.

The Prog ram/Eras e Controlle r will sus pend within

the Erase Suspend Latency Time after the Erase

Suspend Comm and is issued (see Table 4 for nu-

merical values). Once the Program/ Erase Control -

ler has stopped the memory will be set to Read

mode and the Erase will be suspended. If the

Erase Suspend command is issued during the pe-

riod when the m emory is waiting for an additional

block (before t he Program/Erase Controller starts)

then the Erase is suspended i mm edi ately and wi ll

start immediately when the Erase Resume Com-

mand is issued. It is not possible to select any fur-

ther blocks to erase aft er the Erase Resume.

During Erase Suspend it is p ossi ble to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protec ted block o r in the suspen ded

block then the Program command is ignored and

the data remains unchanged. The St atus Register

is not read and no error condi tion is gi ven. Read-

ing from blocks that are being erased will output

the Status Register.

It is al so possible to issue the Auto Select and Un-

lock Bypass commands during an Erase Suspend.

The Read/Reset command must be issued to re-

turn t he device to Read Array m ode before the Re-

sume c omma nd w ill be ac c e pted.

Erase Resum e Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resum ed more than onc e.

Block Protect and

Chip Unprotect Commands.

Each block can be separately protected against

accidental Progra m or E rase. The whol e c hip can

be unprotect ed to allow the data inside the blocks

to be changed.

Block Protect and Chip Unprotect operations are

described in Appendi x B.

Table 4. Pro gra m , Erase Times and Progra m , Erase Enduran ce Cycle s

No te : 1. Typ i cal value s m easured at room tem perature and nominal voltages.

2. Sampled, but not 100% tested.

3. Max imum valu e m easured at wors t case cond i tions for bot h tempe rature an d VCC afte r 100,00 pr ogram/erase cy cles.

4. Max imum valu e m easured at wors t case cond i tions for bot h tempe rature an d VCC.

Parameter Min Typ (1,2) Max(2) Unit

Chip Erase (All bits in the memory set to ‘0’) 2.5 s

Chip Erase 6 35(3) s

Block Erase (64 Kbytes) 0.8 6(4) s

Program (Byte or Word) 10 200(3) µs

Chip Program (Byte by Byte) 5.5 30(3) s

Chip Program (Word by Word) 2.8 15(3) s

Erase Suspend Latency Time 18 25(4) µs

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

15/36

M29W400DT, M29W400DB

Table 5. Commands, 16- bi t mode, BYTE = VIH

Note: X Don’t Care, PA Program Addr ess, PD Prog ram Data, BA Any address i n t he Block. All values i n the t able a re in he xadecim al . T he

Com ma nd Inte rfac e only uses A-1 ; A0-A 1 0 a nd DQ 0- DQ7 to ve rif y the com man ds; A1 1-A1 7, DQ8 -D Q14 and DQ1 5 are Don 't Care.

DQ 15A-1 is A -1 when BYTE is VIL or DQ15 when BYTE is VIH.

Table 6. Commands, 8-bi t mode, BYTE = VIL

Note: X Don’t Care, PA Program A ddress, P D Prog ram Da ta , B A Any a ddress in the Block. All values i n the table are in hexadec i m al . The

Com ma nd Inte rfac e only uses A -1; A 0-A1 0 and DQ 0-DQ7 to veri fy the co mm an ds; A11- A17, DQ8 -DQ14 and DQ1 5 are Don' t Care.

DQ 15A-1 is A -1 when BYTE is VIL or DQ15 when BY T E is V IH.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

M29W400DT, M 29W400DB

16/36

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is acce ssed .

The bits in the Status Register are s um marized in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Pol ling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from t he ad-

dress just programmed output DQ7, not its com-

plement.

During Erase ope rations the Data Po lling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Aft er suc cessful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change f rom a ’0’ to a ’ 1’ when the Program/ Erase

Controller has suspe nded the Erase operation.

Figure 8, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A V alid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used t o

identify whether the Program/Er as e Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. T he To ggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-

sive Bus Read operations at any address. After

successful completion of the operation t he memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell wi thin a bl ock being

erased. The Toggle Bit will stop t oggling when the

Program/Erase Controller has suspended the

Erase operation.

If any attempt is ma de to erase a protected bl ock,

the o peration is aborted, n o error is sig nalle d and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspended b lock, the operatio n is aborted, no er-

ror is signalled and DQ6 toggl es for approximately

1µs.

Figure 9 , Data Toggle Flowchart, g ives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Erro r Bit is set to ’1’ wh en a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Rea d/Re se t comm and must be issued

before other command s a re issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that t he Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dres s w ill s how the bit is s ti ll ‘0’. On e of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1 ’

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing, the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ‘0’ and additional block s to be eras ed

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operation s. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes fro m ’0’ to ’1’ to ’0’, etc., with

successive Bus Re ad operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once t he operation completes the m emory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as i f in Read mode.

After an Erase operation that caus es t he Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or bloc ks have caused the er-

ror. The Altern ative Toggle Bit changes from ’0’ t o

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternati ve Togg le Bit does

not change if the addressed block has erased cor-

rectly.

17/36

M29W400DT, M29W400DB

Table 7. Status Register Bits

No te : Unspecified data bits sh ould be ignored.

Figu re 8. Da ta Po lli ng Fl owch ar t Figu r e 9. Da ta To ggle Fl owchart

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 ––0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370C

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

M29W400DT, M 29W400DB

18/36

MAX I MUM R AT I N G

Stressing the device ab ove t he rati ng l isted in t he

Absolute Maximum Ratings" table may caus e per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note: 1. Min i m um voltage m ay undershoot to –2V du ri ng trans i tion and for less t han 20ns during transitions.

2. Max imum voltage may overshoot to V CC +2V during trans i tion and for less than 20n s during tr ansitio ns.

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V

VCC Supply Voltage –0.6 4 V

VID Identification Voltage –0.6 13.5 V

19/36

M29W400DT, M29W400DB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, a nd the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9, Operating and

AC Measurement Conditions. Designers should

check t hat the operating cond itions in their circuit

match the operating conditions when relying on

the quot ed parameters.

Table 9. Operating and AC Measurem en t Conditions

Figu re 10 . AC Measurement I/O W aveform Figure 11. AC Measure m ent Load Cir cui t

Table 10. Device Capacitance

No te : Sam pled o nl y, not 100% t ested.

Parameter

M29W400D

Unit45 55 70

Min Max Min Max Min Max

VCC Supply Voltage 3.0 3.6 2.7 3.6 2.7 3.6 V

Ambient Operating Temperature (range 6) –40 85 –40 85 –40 85 °C

Ambient Operating Temperature (range 1) 0 70 0 70 0 70

Load Capacitance (CL)30 30 100 pF

Input Rise and Fall Times 10 10 10 ns

Input Pulse Voltages 0 to VCC 0 to VCC 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 VCC/2 VCC/2 V

AI04498

VCC

VCC/2

AI04499

CL includes JIG capacitance

DEVICE

UNDER

TEST

25kΩ

VCC

25kΩ

VCC

0.1µF

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

M29W400DT, M 29W400DB

20/36

Table 11. DC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH,

f = 6MHz 10 mA

ICC2 Supply Current (Standby) E = VCC ±0.2V,

RP = VCC ±0.2V 100 µA

ICC3 (1) Supply Current (Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC +0.3 V

VOL Output Low Voltage IOL = 1.8mA 0.45 V

VOH Output High Voltage IOH = –100µAVCC –0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO Program/Erase Lockout Supply

Voltage 1.8 2.3 V

21/36

M29W400DT, M29W400DB

Figure 12. Read Mode AC Waveforms

Table 12. Read AC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29W400D Unit

45 55 70

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 45 55 70 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max455570ns

ELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max455570ns

GLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max303035ns

EHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max202530ns

GHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max202530ns

EHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or Address

Transition to Output Transition Min 0 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 40 ns

AI02907

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

M29W400DT, M 29W400DB

22/36

Figure 13. Write AC Waveforms, Wr ite Enable Controlled

Table 13. Write AC Characteristics, Write Enable Controlle d

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W400D Unit

45 55 70

tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 45 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 30 45 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 45 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 µs

AI01869C

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

23/36

M29W400DT, M29W400DB

Figure 14. Write AC Waveforms, Chip Enable Control led

Table 14. W rite AC Characteristics, Chip Enable Controlled

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W400D Unit

45 55 70

tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 45 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 30 45 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 45 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 µs

AI01870C

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

M29W400DT, M 29W400DB

24/36

Figure 15. Reset/Block Tem porary Unp rotec t AC Wavefo rms

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W400D Unit

45 55 70

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 500 ns

AI02931

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

25/36

M29W400DT, M29W400DB

PACKAGE MECHANICAL

Figure 16. SO44 - 44 lead Plasti c Small Outline, 525 mils body wi dth, Package Outline

Not e: Drawing is not to scale.

Table 16. SO44 – 44 lead Pl astic Small Outline, 525 mils body width, Packag e Mechani cal Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.80 0.1102

A1 0.10 0.0039

A2 2.30 2.20 2.40 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079

CP 0.08 0.0030

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

E 13.30 13.20 13.50 0.5236 0.5197 0.5315

EH 16.00 15.75 16.25 0.6299 0.6201 0.6398

e1.27 – – 0.0500 – –

L 0.80 0.0315

a8 8

N44 44

SO-d

LA1 α

eCP

M29W400DT, M 29W400DB

26/36

Figure 17. TSO P4 8 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Pa ckage Outline

Not e: Drawing is not to scale.

Table 17. TS OP 48 – 48 lead Plastic Thin Sma ll Outline, 12 x 20mm, Package Me chan ical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7283

e 0.500 – – 0.0197 – –

E 11.900 12.100 0.4685 0.4764

L 0.500 0.700 0.0197 0.0276

alfa 0 5 0 5

N48 48

TSOP-a

1 N

N/2

DIE

LA1 α

27/36

M29W400DT, M29W400DB

Figure 18. T FBGA48 6x9mm – 6x8 ball array – 0. 80mm pi tch, Bottom View Package Outline

Not e: Drawing is not to scale.

Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Packa ge Me chan ical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.200 0.0079

A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 9.000 8.900 9.100 0.3543 0.3504 0.3583

e 0.800 – – 0.0315 – –

E1 5.600 – – 0.2205 – –

FD 1.000 – – 0.0394 – –

FE 1.700 – – 0.0669 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

E1E

BGA-Z00

ddd

FE SD

BALL "A1"

M29W400DT, M 29W400DB

28/36

PAR T NUMBERING

Table 19. Ordering Information Scheme

Devices are shipped from the factory wit h the memory content bits erased t o ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office neares t to you.

Example: M29W400DB 55 N 6 T

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

400D = 4 Mbit (512Kx8 or 256Kx16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

45 = 45ns

55 = 55ns

70 = 70ns

Package

M = SO44

N = TSOP48: 12 x 20mm

ZA = TFBGA48: 6 x 9mm

Temperature Range

6 = –40 to 85 °C

1 = 0 to 70 °C

Option

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

29/36

M29W400DT, M29W400DB

APPENDIX A. BLOCK ADDRESS TABLE

Table 20. Top Boot Block Addresse s

M29W400DT Table 21. B ottom Boot Block Addresses

M29W400DB

#Size

(Kbytes) Address Rang e

(x8) Address Range

(x16)

10 16 7C000h-7FFFFh 3E000h-3FFFFh

9 8 7A000h-7BFFFh 3D000h-3DFFFh

8 8 78000h-79FFFh 3C000h-3CFFFh

7 32 70000h-77FFFh 38000h-3BFFFh

6 64 60000h-6FFFFh 30000h-37FFFh

5 64 50000h-5FFFFh 28000h-2FFFFh

4 64 40000h-4FFFFh 20000h-27FFFh

3 64 30000h-3FFFFh 18000h-1FFFFh

2 64 20000h-2FFFFh 10000h-17FFFh

1 64 10000h-1FFFFh 08000h-0FFFFh

0 64 00000h-0FFFFh 00000h-07FFFh

#Size

(Kbytes) Address Rang e

(x8) Address Range

(x16)

10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh

8 64 50000h-5FFFFh 28000h-2FFFFh

7 64 40000h-4FFFFh 20000h-27FFFh

6 64 30000h-3FFFFh 18000h-1FFFFh

5 64 20000h-2FFFFh 10000h-17FFFh

4 64 10000h-1FFFFh 08000h-0FFFFh

3 32 08000h-0FFFFh 04000h-07FFFh

2 8 06000h-07FFFh 03000h-03FFFh

1 8 04000h-05FFFh 02000h-02FFFh

0 16 00000h-03FFFh 00000h-01FFFh

M29W400DT, M 29W400DB

30/36

APPENDIX B. BL OCK PROTECTION

Block protection can be used to prev ent any oper-

ation from modifying the dat a stored in the Flash.

Each Block can be protected individually. Once

protected, Program and Erase operations on the

block fail to change the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In- System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pi n, RP; this is described in the S ign al De-

scriptions section.

Unlike the Command Interface of the Program/

Erase Cont roller, the techniques for prot ecting and

unprotecting blocks change between different

Flash memory suppliers. For example, the tech-

niques for AMD parts will not work on STMicro-

electronics parts. Care should be taken when

changing drivers for one part t o work on another.

Programme r Techniq ue

The Programmer technique uses high (VID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard micropr oces sor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a block follow the flowchart in Figure 19,

Programmer Equipment Block Protect Flowchart.

To unprotect the whole chip it is necessary to pro-

tect all of the blocks firs t, then all blocks can be un-

protected at the same time. To unprotect the chip

follow Figure 20, Programmer Equipment Chip

Unprotect Flowchart. Table 22, Programmer

Technique Bus Operations, gives a summary of

each operation.

The timing on these flowcharts is critical. Care

should be taken t o ensure that, where a pau se is

specified, it is followed as clos ely as possible. Do

not abort the procedure be fore reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP . This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this techniqu e is suitable

for use after the Flash has been fitted to the sys-

tem.

To protect a block follow the flowchart in Figure 21,

In-System Block Protect Flowchart. To unprotect

the whole c hip it is necessary to protect all of the

blocks f irst, then all the blocks can be unprotected

at the same time. To unprotect the chip foll ow Fig-

ure 22, I n-System Chip Unprotect Fl owchart.

The timing on these flowcharts is critical. Care

should be taken t o ensure that, where a pau se is

specified, it is followed as clos ely as possible. Do

not allow the m icroprocessor t o service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Table 22. Program mer Tech niqu e Bus Op erati ons, BYTE = VIH or VIL

Operation E G W Address Inputs

A0-A17 Data Inputs/Out puts

DQ15 A–1, DQ14 -DQ0

Block Protect VIL VID VIL Pulse A9 = VID, A12-A17 Block Address

Others = X X

Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH

Others = X X

Block Protection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9=V

ID,

A12-A17 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block Unprotection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A 6 = VIH, A9 = VID,

A12-A17 Block Address

Others = X

Retry = XX01h

Pass = XX00h

31/36

M29W400DT, M29W400DB

Figure 19. Programmer Equipment Block Protect Flowchart

ADDRESS = BLOCK ADDRESS

AI03469

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

M29W400DT, M 29W400DB

32/36

Fi gure 20. Pr ogra m m er Equipme nt Chi p U nprot ect Flowchar t

PROTECT ALL BLOCKS

AI03470

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT BLOCK

n = 0

CURRENT BLOCK = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

BLOCK

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

33/36

M29W400DT, M29W400DB

Figure 21. In-System Equipment Blo ck Protect Flowchart

AI03471

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

M29W400DT, M 29W400DB

34/36

Figure 22. In-System Equipment Chi p Unprotect Flowchart

AI03472

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT BLOCK = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL BLOCKS

INCREMENT

CURRENT BLOCK

LAST

BLOCK

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

35/36

M29W400DT, M29W400DB

RE VISION HISTORY

Table 23. D ocum ent Revision History

Date Version Revision Details

26-Jul-2002 -01 First Issue

19-Feb-2003 2.0

Revision numbering modified: a minor revision will be indicated by incrementing the digit

after the dot, and a major revision, by incrementing the digit before the dot (revision

version 01 equals 1.0). Revision History moved to end of document.

Typical after 100k W/E Cycles column removed from Table 4, Program, Erase Times and

Program, Erase Endurance Cycles, Data Retention and Erase Suspend Latency Time

parameters added. Common Flash Interface removed from datasheet.

Lead-free package options E and F added to Table 19, Ordering Information Scheme.

Document promoted from Product Preview to Preliminary Data status.

M29W400DT, M 29W400DB

36/36

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by i m pl i cation or oth erwise under any pat ent or paten t ri ghts of STMic roelec tr onics. Speci fications ment i oned in this publicati on are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical com ponents in life support devices or systems without express writ ten approval of STM i croelectronics.

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