BC858AWT3 - ON Semiconductor L.L.C.

2–159Motorola Small–Signal Transistors, FETs and Diodes Device Data

General Purpose Transistors

PNP Silicon

These transistors are designed for general purpose amplifier

applications. They are housed in the SOT–323/SC–70 which is

designed for low power surface mount applications.

MAXIMUM RATINGS

Rating Symbol BC856 BC857 BC858 Unit

Collector–Emitter Voltage VCEO –65 –45 –30 V

Collector–Base Voltage VCBO –80 –50 –30 V

Emitter–Base Voltage VEBO –5.0 –5.0 –5.0 V

Collector Current — Continuous IC–100 –100 –100 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board, (1)

TA = 25°CPD150 mW

Thermal Resistance, Junction to Ambient R

JA 833 °C/W

Junction and Storage Temperature TJ, Tstg –55 to +150 °C

DEVICE MARKING

BC856AWT1 = 3A; BC856BWT1 = 3B; BC857AWT1 = 3E; BC857BWT1 = 3F;

BC858AWT1 = 3J; BC858BWT1 = 3K; BC858CWT1 = 3L

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Collector–Emitter Breakdown Voltage BC856 Series

(IC = –10 mA) BC857 Series

BC858 Series

V(BR)CEO –65

–45

–30

—

Collector–Emitter Breakdown Voltage BC856 Series

(IC = –10 µA, VEB = 0) BC857 Series

BC858 Series

V(BR)CES –80

–50

–30

—

Collector–Base Breakdown Voltage BC856 Series

(IC = –10

A) BC857 Series

BC858 Series

V(BR)CBO –80

–50

–30

—

Emitter–Base Breakdown Voltage BC856 Series

(IE = –1.0

A) BC857 Series

BC858 Series

V(BR)EBO –5.0

–5.0

—

Collector Cutof f Current (VCB = –30 V)

Collector Cutoff Current (VCB = –30 V, TA = 150°C) ICBO —

——

—–15

–4.0 nA

µA

1. FR–5 = 1.0 x 0.75 x 0.062 in

Preferred devices are Motorola recommended choices for future use and best overall value.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

BC856AWT1,BWT1

BC857AWT1,BWT1

BC858AWT1,BWT1,

CWT1

Motorola Preferred Devices

CASE 419–02, STYLE 3

SOT–323/SC–70

COLLECTOR

BASE

EMITTER

BC856AWT1,BWT1 BC857AWT1,BWT1 BC858AWT1,BWT1,CWT1

2–160 Motorola Small–Signal Transistors, FETs and Diodes Device Data

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)

Characteristic Symbol Min Typ Max Unit

ON CHARACTERISTICS

DC Current Gain BC856A, BC857A, BC585A

(IC = –10 µA, VCE = –5.0 V) BC856A, BC857A, BC858A

BC858C

(IC = –2.0 mA, VCE = –5.0 V) BC856A, BC857A, BC858A

BC856B, BC857B, BC858B

BC858C

hFE —

—

125

220

420

150

270

180

290

520

—

250

475

800

—

Collector–Emitter Saturation V oltage

(IC = –10 mA, IB = –0.5 mA)

(IC = –100 mA, IB = –5.0 mA)

VCE(sat) —

——

—–0.3

–0.65

Base–Emitter Saturation V oltage

(IC = –10 mA, IB = –0.5 mA)

(IC = –100 mA, IB = –5.0 mA)

VBE(sat) —

—–0.7

–0.9 —

—

Base–Emitter On Voltage

(IC = –2.0 mA, VCE = –5.0 V)

(IC = –10 mA, VCE = –5.0 V)

VBE(on) –0.6

——

—–0.75

–0.82

SMALL–SIGNAL CHARACTERISTICS

Current–Gain — Bandwidth Product

(IC = –10 mA, VCE = –5.0 Vdc, f = 100 MHz) fT100 — — MHz

Output Capacitance

(VCB = –10 V, f = 1.0 MHz) Cob — — 4.5 pF

Noise Figure

(IC = –0.2 mA, VCE = –5.0 Vdc, RS = 2.0 kΩ,

f = 1.0 kHz, BW = 200 Hz)

NF — — 10 dB

BC856AWT1,BWT1 BC857AWT1,BWT1 BC858AWT1,BWT1,CWT1

2–161Motorola Small–Signal Transistors, FETs and Diodes Device Data

BC857/BC858

Figure 1. Normalized DC Current Gain

IC, COLLECTOR CURRENT (mAdc)

Figure 2. “Saturation” and “On” Voltages

IC, COLLECTOR CURRENT (mAdc)

–0.2

0.2

Figure 3. Collector Saturation Region

IB, BASE CURRENT (mA)

Figure 4. Base–Emitter Temperature Coefficient

IC, COLLECTOR CURRENT (mA)

–0.6

–0.7

–0.8

–0.9

–1

–0.5

–0.2

–0.4

–0.1

–0.3

1.6

1.2

2.0

2.8

2.4

–1.2

–1.6

–2.0

–0.02 –1.0 –10

0–20

–0.1

–0.4

–0.8

hFE

NORMALI

D D

RRENT

AIN

V, VOLTAGE (VOLTS)

VCE

COLLECTOR–EMITTER

OLTA

)

VB, TEMPERATURE COEFFICIENT (mV/ C)°θ

1.5

1.0

0.7

0.5

0.3

–0.2 –10 –100

–1.0

TA = 25°CVBE(sat) @ IC/IB = 10

VCE(sat) @ IC/IB = 10

VBE(on) @ VCE = –10 V

VCE = –10 V

TA = 25°C

–55°C to +125°C

IC = –100 mA

IC = –20 mA

–0.5 –1.0 –2.0 –5.0 –10 –20 –50 –100 –200 –0.1 –0.2 –0.5 –1.0 –2.0 –5.0 –10 –20 –50 –100

IC = –200 mAIC = –50 mAIC =

–10 mA

Figure 5. Capacitances

VR, REVERSE VOLTAGE (VOLTS)

Figure 6. Current–Gain – Bandwidth Product

IC, COLLECTOR CURRENT (mAdc)

–0.4

1.0

100

200

300

400

7.0

5.0

3.0

2.0

–0.5

CAPACITANCE

(pF

)

f , CURRENT–GAIN – BANDWIDTH PRODUCT (MHz)

TA = 25°C

Cob

Cib

–0.6 –1.0 –2.0 –4.0 –6.0 –10 –20 –30 –40

150

–1.0 –2.0 –3.0 –5.0 –10 –20 –30 –50

VCE = –10 V

TA = 25°C

1.0

BC856AWT1,BWT1 BC857AWT1,BWT1 BC858AWT1,BWT1,CWT1

2–162 Motorola Small–Signal Transistors, FETs and Diodes Device Data

BC856

Figure 7. DC Current Gain

IC, COLLECTOR CURRENT (AMP)

Figure 8. “On” Voltage

IC, COLLECTOR CURRENT (mA)

–0.8

–1

–0.6

–0.2

–0.4

1.0

2.0

–0.1 –1.0 –10 –200

–0.2

0.2

0.5

–0.2 –1.0 –10 –200

TJ = 25°C

VBE(sat) @ IC/IB = 10

VCE(sat) @ IC/IB = 10

VBE @ VCE = –5.0 V

Figure 9. Collector Saturation Region

IB, BASE CURRENT (mA)

Figure 10. Base–Emitter Temperature Coefficient

IC, COLLECTOR CURRENT (mA)

–1.0

–1.2

–1.6

–2.0

–0.02 –1.0 –10

0–20

–0.1

–0.4

–0.8

VCE

COLLECTOR–EMITTER

OLTA

OLTS)

VB, TEMPERA TURE COEFFICIENT (mV/ C)°θ

–0.2 –2.0 –10 –200

–1.0

TJ = 25°C

IC =

–10 mA

hFE

RRENT

AIN

(

NORMALI

)

V, VOLTAGE (VOLTS)

VCE = –5.0 V

TA = 25°C

0–0.5 –2.0 –5.0 –20 –50 –100

–0.05 –0.2 –0.5 –2.0 –5.0

–100 mA

–20 mA

–1.4

–1.8

–2.2

–2.6

–3.0 –0.5 –5.0 –20 –50 –100

–55°C to 125°C

θVB for VBE

–2.0 –5.0 –20 –50 –100

Figure 11. Capacitance

VR, REVERSE VOLTAGE (VOLTS)

Figure 12. Current–Gain – Bandwidth Product

IC, COLLECTOR CURRENT (mA)

–0.1 –0.2 –1.0 –50

2.0 –2.0 –10 –100

100

200

500

6.0

4.0

–1.0 –10 –100

VCE = –5.0 V

CAPACITANCE

(pF

)

f , CURRENT–GAIN – BANDWIDTH PRODUCT

–0.5 –5.0 –20

TJ = 25°C

Cob

Cib

8.0

–50 mA –200 mA

BC856AWT1,BWT1 BC857AWT1,BWT1 BC858AWT1,BWT1,CWT1

2–163Motorola Small–Signal Transistors, FETs and Diodes Device Data

Figure 13. Thermal Response

t, TIME (ms)

1.0

r(t), TRANSIENT THERMAL

2.0 5.01.00.50.20.1

RESIST ANCE (NORMALIZED)

0.7

0.5

0.3

0.2

0.1

0.07

0.05

0.03

0.02

0.01 20 5010 200 500100 1.0 k 2.0 k 5.0 k 10 k

Figure 14. Active Region Safe Operating Area

VCE, COLLECTOR–EMITTER VOLTAGE (V)

–200

–1.0

IC, COLLECTOR CURRENT (mA)

TA = 25°C

D = 0.5

0.2

0.1 0.05 SINGLE PULSE

SINGLE PULSE

BONDING WIRE LIMIT

THERMAL LIMIT

SECOND BREAKDOWN LIMIT

3 ms

TJ = 25°C

ZθJC(t) = r(t) RθJC

RθJC = 83.3°C/W MAX

ZθJA(t) = r(t) RθJA

RθJA = 200°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) – TC = P(pk) RθJC(t)

t1t2

P(pk)

DUTY CYCLE, D = t1/t2

–100

–50

–10

–5.0

–2.0 –5.0 –10 –30 –45 –65 –100

1 s

BC558

BC557

BC556

The safe operating area curves indicate IC–VCE limits of the

transistor that must be observed for reliable operation. Collector load

lines for specific circuits must fall below the limits indicated by the

applicable curve.

The data of Figure 14 is based upon TJ(pk) = 150°C; TC or TA is

variable depending upon conditions. Pulse curves are valid for duty

cycles to 10% provided TJ(pk) ≤ 150°C. TJ(pk) may be calculated from

the data in Figure 13. At high case or ambient temperatures, thermal

limitations will reduce the power that can be handled to values less

than the limitations imposed by the secondary breakdown.

2–2 Motorola Small–Signal Transistors, FETs and Diodes Device Data

EMBOSSED TAPE AND REEL

SOT-23, SC-59, SC-70/SOT-323, SC–90/SOT–416, SOT-223 and SO-16 packages are available only in

Tape and Reel. Use the appropriate suffix indicated below to order any of the SOT-23, SC-59,

SC-70/SOT-323, SOT-223 and SO-16 packages. (See Section 6 on Packaging for additional information).

SOT-23: available in 8 mm Tape and Reel

Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.

SC-59: available in 8 mm Tape and Reel

Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.

SC-70/ available in 8 mm Tape and Reel

SOT-323: Use the device title (which already includes the “T1” suffix) to order the 7 inch/3000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/10,000 unit reel.

SOT-223: available in 12 mm Tape and Reel

Use the device title (which already includes the “T1” suffix) to order the 7 inch/1000 unit reel.

Replace the “T1” suffix in the device title with a “T3” suffix to order the 13 inch/4000 unit reel.

SO-16: available in 16 mm Tape and Reel

Add an “R1” suffix to the device title to order the 7 inch/500 unit reel.

Add an “R2” suffix to the device title to order the 13 inch/2500 unit reel.

RADIAL TAPE IN FAN FOLD BOX OR REEL

TO-92 packages are available in both bulk shipments and in Radial Tape in Fan Fold Boxes or Reels.

Fan Fold Boxes and Radial Tape Reel are the best methods for capturing devices for automatic insertion in

printed circuit boards.

TO-92: available in Fan Fold Box

Add an “RLR” suffix and the appropriate Style code* to the device title to order the Fan Fold box.

available in 365 mm Radial Tape Reel

Add an “RLR” suffix and the appropriate Style code* to the device title to order the Radial Tape

Reel.

*Refer to Section 6 on Packaging for Style code characters and additional information on ordering

*requirements.

DEVICE MARKINGS/DATE CODE CHARACTERS

SOT-23, SC-59, SC-70/SOT-323, and the SC–90/SOT–416 packages have a device marking and a date

code etched on the device. The generic example below depicts both the device marking and a representa-

tion of the date code that appears on the SC-70/SOT-323, SC-59 and SOT-23 packages.

ABCD

The “D” represents a smaller alpha digit Date Code. The Date Code indicates the actual month in which the

part was manufactured.

Tape and Reel Specifications

6–2 Motorola Small–Signal Transistors, FETs and Diodes Device Data

Tape and Reel Specifications

and Packaging Specifications

Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as the

shipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a secure

cavity for the product when sealed with the “peel–back” cover tape.

•Two Reel Sizes Available (7″ and 13″)

•Used for Automatic Pick and Place Feed Systems

•Minimizes Product Handling

•EIA 481, –1, –2

•SOD–123, SC–59, SC–70/SOT–323, SC–70ML/SOT–363,

SOT–23, TSOP–6, in 8 mm Tape

•SOT–223 in 12 mm Tape

•SO–14, SO–16 in 16 mm Tape

Use the standard device title and add the required suffix as listed in the option table on the following page. Note that the individual

reels have a finite number of devices depending on the type of product contained in the tape. Also note the minimum lot size is

one full reel for each line item, and orders are required to be in increments of the single reel quantity.

OF FEED

DIRECTION

SC–59, SC–70/SOT–323, SOT–23

8 mm8 mm

12 mm

SOT–223

SOD–123

16 mm

SO–14, 16

SC–70ML/SOT–363, TSOP–6

T1 ORIENTATION

8 mm

SC–70ML/SOT–363

T2 ORIENTATION

8 mm

EMBOSSED TAPE AND REEL ORDERING INFORMATION

Package Tape Width

(mm) Pitch

mm (inch) Reel Size

mm (inch)

Devices Per Reel

and Minimum

Order Quantity Device

Suffix

SC–59 8 4.0 ± 0.1 (.157 ± .004) 178 (7) 3,000 T1

SC–70/SOT–323 8 4.0 ± 0.1 (.157 ± .004) 178 (7) 3,000 T1

8 330 (13) 10,000 T3

SO–14 16 8.0 ± 0.1 (.315 ± .004) 178 (7) 500 R1

16 330 (13) 2,500 R2

SO–16 16 8.0 ± 0.1 (.315 ± .004) 178 (7) 500 R1

16 330 (13) 2,500 R2

SOD–123 8 4.0 ± 0.1 (.157 ± .004) 178 (7) 3,000 T1

8 330 (13) 10,000 T3

SOT–23 8 4.0 ± 0.1 (.157 ± .004) 178 (7) 3,000 T1

8 330 (13) 10,000 T3

SOT–223 12 8.0 ± 0.1 (.315 ± .004) 178 (7) 1,000 T1

12 330 (13) 4,000 T3

SC–70ML/SOT–363 8 4.0 ± 0.1 (.157 ± .004) 178 (7) 3,000 T1

8 178 (7) 3,000 T2

TSOP–6 8 4.0 ± 0.1 (.157 ± .004) 178 (7) 3,000 T1

6–3

Tape and Reel SpecificationsMotorola Small–Signal Transistors, FETs and Diodes Device Data

EMBOSSED TAPE AND REEL DATA FOR DISCRETES

CARRIER TAPE SPECIFICATIONS

B1K0

Top Cover

Tape

Embossment

User Direction of Feed

Center Lines

of Cavity

DP2

10 Pitches Cumulative Tolerance on Tape

± 0.2 mm

(± 0.008″)

For Components

2.0 mm x 1.2 mm and Larger

* Top Cover Tape

Thickness (t1)

0.10 mm

(.004″) Max.

Embossment

Embossed Carrier

R Min

Bending Radius

Maximum Component Rotation

T ypical Component

Cavity Center Line

T ypical Component

Center Line

100 mm

(3.937″)

250 mm

(9.843″)

1 mm

(.039″) Max

1 mm Max

10°

Tape and Components

Shall Pass Around Radius “R”

Without Damage

Tape

For Machine Reference Only

Including Draft and RADII

Concentric Around B0

Camber (Top V iew)

Allowable Camber To Be 1 mm/100 mm Nonaccumulative Over 250 mm

See

Note 1

Bar Code Label

DIMENSIONS

Tape

Size B1 Max D D1E F K P0P2R Min T Max W Max

8mm 4.55 mm

(.179″)

1mm

–0.0

( 0 9+ 004

1.0 Min

(.039″)

5±

1mm

(.069±.004″)3.5±0.05 mm

(.138±.002″)2.4 mm Max

(.094″)

1mm

(.157±.004″)

1mm

(.079±.002″)25 mm

(.98″)

6mm

(.024″)8.3 mm

(.327″)

12 mm 8.2 mm

(.323″)

(

004

″

–0.0)

(.060″)5.5±0.05 mm

(.217±.002″)6.4 mm Max

(.252″)

30 mm

(1.18″)12±.30 mm

(.470±.012″)

16 mm 12.1 mm

(.476″)7.5±0.10 mm

(.295±.004″)7.9 mm Max

(.311″)16.3 mm

(.642″)

24 mm 20.1 mm

(.791″)11.5±0.1 mm

(.453±.004″)11.9 mm Max

(.468″)24.3 mm

(.957″)

Metric dimensions govern — English are in parentheses for reference only.

NOTE 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within .05 mm min. to .50 mm max.,

NOTE 1: the component cannot rotate more than 10° within the determined cavity.

NOTE 2: If B1 exceeds 4.2 mm (.165) for 8 mm embossed tape, the tape may not feed through all tape feeders.

NOTE 3: Pitch information is contained in the Embossed Tape and Reel Ordering Information on pg. 5.12–3.

Tape and Reel Specifications

6–4 Motorola Small–Signal Transistors, FETs and Diodes Device Data

EMBOSSED TAPE AND REEL DATA FOR DISCRETES

Full Radius

T Max

20.2 mm Min

(.795″)

1.5 mm Min

(.06″)13.0 mm ± 0.5 mm

(.512″ ± .002″)

50 mm Min

(1.969″)

Outside Dimension

Measured at Edge

Inside Dimension

Measured Near Hub

Size A Max GT Max

8 mm 330 mm

(12.992″)8.4 mm + 1.5 mm, –0.0

(.33″ + .059″, –0.00) 14.4 mm

(.56″)

12 mm 330 mm

(12.992″)12.4 mm + 2.0 mm, –0.0

(.49″ + .079″, –0.00) 18.4 mm

(.72″)

16 mm 360 mm

(14.173″)16.4 mm + 2.0 mm, –0.0

(.646″ + .078″, –0.00) 22.4 mm

(.882″)

24 mm 360 mm

(14.173″)24.4 mm + 2.0 mm, –0.0

(.961″ + .070″, –0.00) 30.4 mm

(1.197″)

Reel Dimensions

Metric Dimensions Govern — English are in parentheses for reference only

6–5

Packaging SpecificationsMotorola Small–Signal Transistors, FETs and Diodes Device Data

TO–92 EIA, IEC, EIAJ

Radial Tape in Fan Fold

Box or On Reel

Radial tape in fan fold box or on reel of the reliable TO–92 package are

the best methods of capturing devices for automatic insertion in printed

circuit boards. These methods of taping are compatible with various

equipment for active and passive component insertion.

•Available in Fan Fold Box

•Available on 365 mm Reels

•Accommodates All Standard Inserters

•Allows Flexible Circuit Board Layout

•2.5 mm Pin Spacing for Soldering

•EIA–468, IEC 286–2, EIAJ RC1008B

Ordering Notes:

When ordering radial tape in fan fold box or on reel, specify the style per

Figures 3 through 8. Add the suffix “RLR” and “Style” to the device title, i.e.

MPS3904RLRA. This will be a standard MPS3904 radial taped and

supplied on a reel per Figure 9.

Fan Fold Box Information — Order in increments of 2000.

Reel Information — Order in increments of 2000.

US/European Suffix Conversions

US EUROPE

RLRA RL

RLRE RL1

RLRM ZL1

TO–92

RADIAL

TAPE IN

FAN FOLD

BOX OR

ON REEL

Packaging Specifications

6–6 Motorola Small–Signal Transistors, FETs and Diodes Device Data

TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

H2A H2A

F1 F2

P2 P2

P1 P

H2B H2B

H4 H5

Figure 1. Device Positioning on Tape

Specification

Inches Millimeter

Symbol Item Min Max Min Max

DTape Feedhole Diameter 0.1496 0.1653 3.8 4.2

D2 Component Lead Thickness Dimension 0.015 0.020 0.38 0.51

F1, F2 Component Lead Pitch 0.0945 0.110 2.4 2.8

HBottom of Component to Seating Plane .059 .156 1.5 4.0

H1 Feedhole Location 0.3346 0.3741 8.5 9.5

H2A Deflection Left or Right 0 0.039 0 1.0

H2B Deflection Front or Rear 0 0.051 0 1.0

H4 Feedhole to Bottom of Component 0.7086 0.768 18 19.5

H5 Feedhole to Seating Plane 0.610 0.649 15.5 16.5

LDefective Unit Clipped Dimension 0.3346 0.433 8.5 11

L1 Lead Wire Enclosure 0.09842 — 2.5 —

PFeedhole Pitch 0.4921 0.5079 12.5 12.9

P1 Feedhole Center to Center Lead 0.2342 0.2658 5.95 6.75

P2 First Lead Spacing Dimension 0.1397 0.1556 3.55 3.95

TAdhesive Tape Thickness 0.06 0.08 0.15 0.20

T1 Overall Taped Package Thickness — 0.0567 — 1.44

T2 Carrier Strip Thickness 0.014 0.027 0.35 0.65

WCarrier Strip Width 0.6889 0.7481 17.5 19

W1 Adhesive Tape Width 0.2165 0.2841 5.5 6.3

W2 Adhesive Tape Position .0059 0.01968 .15 0.5

NOTES:

1. Maximum alignment deviation between leads not to be greater than 0.2 mm.

2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.

3. Component lead to tape adhesion must meet the pull test requirements established in Figures 5, 6 and 7.

4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.

5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.

6. No more than 1 consecutive missing component is permitted.

7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.

8. Splices will not interfere with the sprocket feed holes.

6–7

Packaging SpecificationsMotorola Small–Signal Transistors, FETs and Diodes Device Data

TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

ÇÇÇÇÇÇÇ

ADHESIVE TAPE ON

TOP SIDE

FLAT SIDE

CARRIER

STRIP

FLAT SIDE OF TRANSISTOR

AND ADHESIVE TAPE VISIBLE.

ADHESIVE TAPE ON

TOP SIDE

ROUNDED SIDE CARRIER

STRIP

ROUNDED SIDE OF TRANSIST OR AND

ADHESIVE TAPE VISIBLE.

252 mm

9.92”

58 mm

2.28”

MAX

13”

MAX

330 mm

Style M fan fold box is equivalent to styles E and F of

reel pack dependent on feed orientation from box. Style P fan fold box is equivalent to styles A and B of

reel pack dependent on feed orientation from box.

100 GRAM

PULL FORCE 16 mm

HOLDING

FIXTURE HOLDING

FIXTURE

HOLDING

FIXTURE

16 mm

70 GRAM

PULL FORCE

500 GRAM PULL FORCE

The component shall not pull free with a 300 gram

load applied to the leads for 3 ± 1 second. The component shall not pull free with a 70 gram

load applied to the leads for 3 ±1 second.

There shall be no deviation in the leads and

no component leads shall be pulled free of

the tape with a 500 gram load applied to the

component body for 3 ± 1 second.

Figure 2. Style M Figure 3. Style P Figure 4. Fan Fold Box Dimensions

Figure 5. Test #1 Figure 6. Test #2 Figure 7. Test #3

ADHESION PULL TESTS

FAN FOLD BOX STYLES

Packaging Specifications

6–8 Motorola Small–Signal Transistors, FETs and Diodes Device Data

TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

REEL STYLES

ARBOR HOLE DIA.

30.5mm ± 0.25mm

MARKING NOTE

RECESS DEPTH

9.5mm MIN

48 mm

MAX

CORE DIA.

82mm ± 1mm

HUB RECESS

76.2mm ± 1mm

365mm + 3, – 0mm

38.1mm ± 1mm

Material used must not cause deterioration of components or degrade lead solderability

CARRIER STRIP

ADHESIVE T APE

ROUNDED

SIDE

FEED

Rounded side of transistor and adhesive tape visible.

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP FLAT SIDE

FEED

Flat side of transistor and carrier strip visible

(adhesive tape on reverse side).

CARRIER STRIP

ADHESIVE T APE FLAT SIDE

FEED

Flat side of transistor and adhesive tape visible. Rounded side of transistor and carrier strip visible

(adhesive tape on reverse side).

FEED

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP ROUNDED

SIDE

Figure 8. Reel Specifications

Figure 9. Style A Figure 10. Style B

Figure 11. Style E Figure 12. Style F

Surface Mount Information

7–10 Motorola Small–Signal Transistors, FETs and Diodes Device Data

INFORMATION FOR USING SURFACE MOUNT PACKAGES

RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must

be the correct size to ensure proper solder connection inter-

face between the board and the package. With the correct

pad geometry, the packages will self align when subjected to

a solder reflow process.

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a func-

tion of the drain/collector pad size. These can vary from the

minimum pad size for soldering to a pad size given for

maximum power dissipation. Power dissipation for a surface

mount device is determined by TJ(max), the maximum rated

junction temperature of the die, RθJA, the thermal resistance

from the device junction to ambient, and the operating

temperature, TA. Using the values provided on the data

sheet, PD can be calculated as follows:

PD = TJ(max) – TA

RθJA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into

the equation for an ambient temperature T A of 25°C, one can

calculate the power dissipation of the device. For example,

for a SOT–223 device, PD is calculated as follows.

PD = 150°C – 25°C

156°C/W = 800 milliwatts

The 156°C/W for the SOT–223 package assumes the use

of the recommended footprint on a glass epoxy printed circuit

board to achieve a power dissipation of 800 milliwatts. There

are other alternatives to achieving higher power dissipation

from the surface mount packages. One is to increase the

area of the drain/collector pad. By increasing the area of the

drain/collector pad, the power dissipation can be increased.

Although the power dissipation can almost be doubled with

this method, area is taken up on the printed circuit board

which can defeat the purpose of using surface mount

technology. For example, a graph of R θJA versus drain pad

area is shown in Figure 1.

Another alternative would be to use a ceramic substrate or

an aluminum core board such as Thermal Clad. Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

TO AMBIENT ( C/W)°

JA,

THERMAL

TANCE

NCTI

0.8 W atts

1.25 Watts* 1.5 W atts

A, AREA (SQUARE INCHES)

0.0 0.2 0.4 0.6 0.8 1.0

160

140

120

100

Board Material = 0.0625″

G–10/FR–4, 2 oz Copper TA = 25°C

*Mounted on the DPAK footprint

Figure 1. Thermal Resistance versus Drain Pad

Area for the SOT–223 Package (Typical)

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

circuit board, solder paste must be applied to the pads.

Solder stencils are used to screen the optimum amount.

These stencils are typically 0.008 inches thick and may be

made of brass or stainless steel. For packages such as the

SOT–23, SC–59, SC–70/SOT–323, SC–90/SOT–416,

SOD–123, SOT–223, SOT–363, SO–14, SO–16, and

TSOP–6 packages, the stencil opening should be the same

as the pad size or a 1:1 registration.

7–11

Surface Mount InformationMotorola Small–Signal Transistors, FETs and Diodes Device Data

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within a

short time could result in device failure. Therefore, the

following items should always be observed in order to mini-

mize the thermal stress to which the devices are subjected.

•Always preheat the device.

•The delta temperature between the preheat and soldering

should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering method,

the difference should be a maximum of 10°C.

•The soldering temperature and time should not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.

Gradual cooling should be used since the use of forced

cooling will increase the temperature gradient and will

result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive

thermal shock and stress which can result in damage to the

device.

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control

settings that will give the desired heat pattern. The operator

must set temperatures for several heating zones and a figure

for belt speed. Taken together, these control settings make

up a heating “profile” for that particular circuit board. On

machines controlled by a computer, the computer remem-

bers these profiles from one operating session to the next.

Figure 2 shows a typical heating profile for use when

soldering a surface mount device to a printed circuit board.

This profile will vary among soldering systems, but it is a

good starting point. Factors that can affect the profile include

the type of soldering system in use, density and types of

components on the board, type of solder used, and the type

of board or substrate material being used. This profile shows

temperature versus time. The line on the graph shows the

actual temperature that might be experienced on the surface

of a test board at or near a central solder joint. The two

profiles are based on a high density and a low density board.

The Vitronics SMD310 convection/infrared reflow soldering

system was used to generate this profile. The type of solder

used was 62/36/2 Tin Lead Silver with a melting point

between 177–189°C. When this type of furnace is used for

solder reflow work, the circuit boards and solder joints tend to

heat first. The components on the board are then heated by

conduction. The circuit board, because it has a large surface

area, absorbs the thermal energy more efficiently, then

distributes this energy to the components. Because of this

effect, the main body of a component may be up to 30

degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 2

VENT

“SOAK”

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT STEP 7

COOLING

200°C

150°C

100°C

50°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

205° TO 219°C

PEAK AT

SOLDER JOINT

DESIRED CUR VE FOR LOW

MASS ASSEMBLIES

100°C

150°C

160°C170°C

140°C

Figure 2. Typical Solder Heating Profile

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

Surface Mount Information

7–12 Motorola Small–Signal Transistors, FETs and Diodes Device Data

Footprints for Soldering

0.094

2.4

SC–59

inches

0.037

0.95

0.037

0.95

0.039

1.0

0.031

0.8

SOT–23

inches

0.037

0.95

0.037

0.95

0.079

2.0

0.035

0.9

0.031

0.8

SO–14, SO–16

inches

0.060

1.52

0.275

7.0

0.024

0.6 0.050

1.270

0.155

4.0

SOT–223

0.079

2.0

0.15

3.8

0.248

6.3

0.079

2.0

0.059

1.5 0.059

1.5

0.091

2.3

0.091

2.3

inches

0.035

0.9

0.075

0.7

1.9

0.028

0.65

0.025

0.65

0.025

SC–70/SOT–323

ÉÉÉ

1.4

0.5 min. (3x)

0.5

SOT 416/SC–90

7–13

Surface Mount InformationMotorola Small–Signal Transistors, FETs and Diodes Device Data

SOT–363

(SC–70 6 LEAD)

ÉÉÉ

0.5 mm (min)

0.4 mm (min)

0.65 mm 0.65 mm

1.9 mm

SOD–123

ÉÉÉÉ

ÉÉÉ

inches

0.91

0.036

1.22

0.048

2.36

0.093

4.19

0.165

inches

0.028

0.7

0.074

1.9

0.037

0.95

0.037

0.95

0.094

2.4

0.039

1.0

TSOP–6

Package Outline Dimensions

8–2 Motorola Small–Signal Transistors, FETs and Diodes Device Data

Package Outline Dimensions

Dimensions are in inches unless otherwise noted.

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSION D AND J APPLY BETWEEN L AND K

MINIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIMENSION K MINIMUM.

SECTION X–X

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.175 0.205 4.45 5.20

B0.170 0.210 4.32 5.33

C0.125 0.165 3.18 4.19

D0.016 0.022 0.41 0.55

F0.016 0.019 0.41 0.48

G0.045 0.055 1.15 1.39

H0.095 0.105 2.42 2.66

J0.015 0.020 0.39 0.50

K0.500 ––– 12.70 –––

L0.250 ––– 6.35 –––

N0.080 0.105 2.04 2.66

P––– 0.100 ––– 2.54

R0.115 ––– 2.93 –––

V0.135 ––– 3.43 –––

CASE 029–04

(TO–226AA) TO–92

PLASTIC

STYLE 21:

PIN 1. COLLECTOR

2. EMITTER

3. BASE

STYLE 22:

PIN 1. SOURCE

2. GATE

3. DRAIN

STYLE 14:

PIN 1. EMITTER

2. COLLECTOR

3. BASE

STYLE 30:

PIN 1. DRAIN

2. GATE

3. SOURCE

STYLE 1:

PIN 1. EMITTER

2. BASE

3. COLLECTOR

STYLE 2:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

STYLE 3:

PIN 1. ANODE

2. ANODE

3. CATHODE

STYLE 5:

PIN 1. DRAIN

2. SOURCE

3. GATE

STYLE 7:

PIN 1. SOURCE

2. DRAIN

3. GATE

STYLE 15:

PIN 1. ANODE 1

2. CATHODE

3. ANODE 2

STYLE 17:

PIN 1. COLLECTOR

2. BASE

3. EMITTER

STYLE 4:

PIN 1. CATHODE

2. CATHODE

3. ANODE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSIONS D AND J APPLY BETWEEN L AND K

MIMIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIMENSION K MINIMUM.

SEATING

PLANE

SECTION X–X

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.175 0.205 4.44 5.21

B0.290 0.310 7.37 7.87

C0.125 0.165 3.18 4.19

D0.018 0.022 0.46 0.56

F0.016 0.019 0.41 0.48

G0.045 0.055 1.15 1.39

H0.095 0.105 2.42 2.66

J0.018 0.024 0.46 0.61

K0.500 ––– 12.70 –––

L0.250 ––– 6.35 –––

N0.080 0.105 2.04 2.66

P––– 0.100 ––– 2.54

R0.135 ––– 3.43 –––

V0.135 ––– 3.43 –––

CASE 029–05

(TO–226AE) TO–92

1–WATT PLASTIC

STYLE 1:

PIN 1. EMITTER

2. BASE

3. COLLECTOR

STYLE 14:

PIN 1. EMITTER

2. COLLECTOR

3. BASE

STYLE 22:

PIN 1. SOURCE

2. GATE

3. DRAIN

8–3

Package Outline DimensionsMotorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. PACKAGE CONTOUR OPTIONAL WITHIN DIA B

AND LENGTH A. HEAT SLUGS, IF ANY, SHALL BE

INCLUDED WITHIN THIS CYLINDER, BUT SHALL

NOT BE SUBJECT TO THE MIN LIMIT OF DIA B.

2. LEAD DIA NOT CONTROLLED IN ZONES F, TO

ALLOW FOR FLASH, LEAD FINISH BUILDUP,

AND MINOR IRREGULARITIES OTHER THAN

HEAT SLUGS.

CASE 51–02

(DO–204AA)

DO–7

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A5.84 7.62 0.230 0.300

B2.16 2.72 0.085 0.107

D0.46 0.56 0.018 0.022

F––– 1.27 ––– 0.050

K25.40 38.10 1.000 1.500

All JEDEC dimensions and notes apply.

ÉÉ

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND ZONE R IS

UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSIONS D AND J APPLY BETWEEN L AND K

MINIMUM. LEAD DIMENSION IS UNCONTROLLED

IN P AND BEYOND DIM K MINIMUM.

CASE 182–02

PLASTIC

(T0–226AC) TO–92

SEATING

PLANE

SECTION X–X

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.175 0.205 4.45 5.21

B0.170 0.210 4.32 5.33

C0.125 0.165 3.18 4.49

D0.016 0.022 0.41 0.56

F0.016 0.019 0.407 0.482

G0.050 BSC 1.27 BSC

H0.100 BSC 3.54 BSC

J0.014 0.016 0.36 0.41

K0.500 ––– 12.70 –––

L0.250 ––– 6.35 –––

N0.080 0.105 2.03 2.66

P––– 0.050 ––– 1.27

R0.115 ––– 2.93 –––

V0.135 ––– 3.43 –––

STYLE 1:

PIN 1. ANODE

2. CATHODE

Package Outline Dimensions

8–4 Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

CASE 318–08

(TO–236AB) SOT–23

12DIM

AMIN MAX MIN MAX

MILLIMETERS

0.1102 0.1197 2.80 3.04

INCHES

B0.0472 0.0551 1.20 1.40

C0.0350 0.0440 0.89 1.11

D0.0150 0.0200 0.37 0.50

G0.0701 0.0807 1.78 2.04

H0.0005 0.0040 0.013 0.100

J0.0034 0.0070 0.085 0.177

K0.0140 0.0285 0.35 0.69

L0.0350 0.0401 0.89 1.02

S0.0830 0.1039 2.10 2.64

V0.0177 0.0236 0.45 0.60

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIUMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

STYLE 6:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

STYLE 8:

PIN 1. ANODE

2. NO CONNECTION

3. CATHODE

STYLE 9:

PIN 1. ANODE

2. ANODE

3. CATHODE

STYLE 10:

PIN 1. DRAIN

2. SOURCE

3. GATE

STYLE 11:

PIN 1. ANODE

2. CATHODE

3. CATHODE–ANODE

STYLE 12:

PIN 1. CATHODE

2. CATHODE

3. ANODE

STYLE 18:

PIN 1. NO CONNECTION

2. CATHODE

3. ANODE

STYLE 19:

PIN 1. CATHODE

2. ANODE

3. CATHODE–ANODE

STYLE 21:

PIN 1. GATE

2. SOURCE

3. DRAIN

PLASTIC

DIM

AMIN MAX MIN MAX

INCHES

2.70 3.10 0.1063 0.1220

MILLIMETERS

B1.30 1.70 0.0512 0.0669

C1.00 1.30 0.0394 0.0511

D0.35 0.50 0.0138 0.0196

G1.70 2.10 0.0670 0.0826

H0.013 0.100 0.0005 0.0040

J0.09 0.18 0.0034 0.0070

K0.20 0.60 0.0079 0.0236

L1.25 1.65 0.0493 0.0649

S2.50 3.00 0.0985 0.1181

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

CASE 318D–04

SC–59

STYLE 3:

PIN 1. ANODE

2. ANODE

3. CATHODE

STYLE 1:

PIN 1. EMITTER

2. BASE

3. COLLECTOR

STYLE 2:

PIN 1. N.C.

2. ANODE

3. CATHODE

STYLE 4:

PIN 1. N.C.

2. CATHODE

3. ANODE

STYLE 5:

PIN 1. CATHODE

2. CATHODE

3. ANODE

8–5

Package Outline DimensionsMotorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

123

0.08 (0003) C

DIM

AMIN MAX MIN MAX

MILLIMETERS

0.249 0.263 6.30 6.70

INCHES

B0.130 0.145 3.30 3.70

C0.060 0.068 1.50 1.75

D0.024 0.035 0.60 0.89

F0.115 0.126 2.90 3.20

G0.087 0.094 2.20 2.40

H0.0008 0.0040 0.020 0.100

J0.009 0.014 0.24 0.35

K0.060 0.078 1.50 2.00

L0.033 0.041 0.85 1.05

M0 10 0 10

S0.264 0.287 6.70 7.30

NOTES:

3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

4. CONTROLLING DIMENSION: INCH.

____

CASE 318E–04

SOT–223

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 3:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

STYLE 2:

PIN 1. ANODE

2. CATHODE

3. NC

4. CATHODE

CASE 318G–02

TSOP–6

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. GATE

4. SOURCE

5. DRAIN

6. DRAIN

456

0.05 (0.002)

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A0.1142 0.12202.90 3.10

B0.0512 0.06691.30 1.70

C0.0354 0.04330.90 1.10

D0.0098 0.01970.25 0.50

G0.0335 0.04130.85 1.05

H0.0005 0.00400.013 0.100

J0.0040 0.01020.10 0.26

K0.0079 0.02360.20 0.60

L0.0493 0.06101.25 1.55

M0 10 0 10

S0.0985 0.11812.50 3.00

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

PLASTIC

Package Outline Dimensions

8–6 Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

CASE 419–02

SC–70/SOT–323

CRN

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.071 0.087 1.80 2.20

B0.045 0.053 1.15 1.35

C0.035 0.049 0.90 1.25

D0.012 0.016 0.30 0.40

G0.047 0.055 1.20 1.40

H0.000 0.004 0.00 0.10

J0.004 0.010 0.10 0.25

K0.017 REF 0.425 REF

L0.026 BSC 0.650 BSC

N0.028 REF 0.700 REF

R0.031 0.039 0.80 1.00

S0.079 0.087 2.00 2.20

V0.012 0.016 0.30 0.40

0.05 (0.002)

STYLE 3:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

STYLE 4:

PIN 1. CATHODE

2. CATHODE

3. ANODE

STYLE 2:

PIN 1. ANODE

2. N.C.

3. CATHODE

STYLE 5:

PIN 1. ANODE

2. ANODE

3. CATHODE

STYLE 7:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

STYLE 9:

PIN 1. ANODE

2. CATHODE

3. CATHODE–ANODE

STYLE 10:

PIN 1. CATHODE

2. ANODE

3. ANODE–CATHODE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM

AMIN MAX MIN MAX

MILLIMETERS

1.80 2.200.071 0.087

INCHES

B1.15 1.350.045 0.053

C0.80 1.100.031 0.043

D0.10 0.300.004 0.012

G0.65 BSC0.026 BSC

H––– 0.10–––0.004

J0.10 0.250.004 0.010

K0.10 0.300.004 0.012

N0.20 REF0.008 REF

S2.00 2.200.079 0.087

V0.30 0.400.012 0.016

B0.2 (0.008) MM

123

654

–B–

D6 PL

CASE 419B-01

SOT–363

STYLE 1:

PIN 1. EMITTER 2

2. BASE 2

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

6. COLLECTOR 2

STYLE 6:

PIN 1. ANODE 2

2. N/C

3. CATHODE 1

4. ANODE 1

5. N/C

6. CATHODE 2

8–7

Package Outline DimensionsMotorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

STYLE 1:

PIN 1. CATHODE

2. ANODE

ÂÂÂ

CASE 425–04

SOD–123

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.055 0.071 1.40 1.80

B0.100 0.112 2.55 2.85

C0.037 0.053 0.95 1.35

D0.020 0.028 0.50 0.70

E0.004 ––– 0.25 –––

H0.000 0.004 0.00 0.10

J––– 0.006 ––– 0.15

K0.140 0.152 3.55 3.85

CASE 463–01

SOT–416/SC–90

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A0.70 0.80 0.028 0.031

B1.40 1.80 0.055 0.071

C0.60 0.90 0.024 0.035

D0.15 0.30 0.006 0.012

G1.00 BSC 0.039 BSC

H––– 0.10 ––– 0.004

J0.10 0.25 0.004 0.010

K1.45 1.75 0.057 0.069

L0.10 0.20 0.004 0.008

S0.50 BSC 0.020 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

0.20 (0.008) B

–A–

–B–

3 PL

0.20 (0.008) A

STYLE 1:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

STYLE 4:

PIN 1. CATHODE

2. CATHODE

3. ANODE

Package Outline Dimensions

8–8 Motorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

14 8

HG D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

____

CASE 646–06

14–PIN DIP

PLASTIC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

CASE 648–08

16–PIN DIP

PLASTIC

8–9

Package Outline DimensionsMotorola Small–Signal Transistors, FETs and Diodes Device Data

PACKAGE OUTLINE DIMENSIONS (continued)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B–

P7 PL

14 8

71 M

0.25 (0.010) B M

0.25 (0.010) A S

–T–

RX 45

SEATING

PLANE D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

____

CASE 751A–03

SO–14

PLASTIC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

CASE 751B–05

SO–16

PLASTIC