19-0774; Rev 2) 12/96 Improved, SPST/SPDT Analog Switches General Description Maxim's redesigned DG417/DG418/BG419 precision, CMOS, monolithic analog switches now feature quar- anteed on-resistance matching (38 max) between switches and guaranteed on-resistance flatness over the signal range (49 max}. These switches conduct equally well in either direction anc quarantee low charge injection, low power consumption, and an ESD tolerance of 2000V minimum per Method 3015.7. The new design offers low off-leakage current over temper- ature (less tnan 5nA at +85C). The DG417/DG418 are single-pole/single-throw (SPST) switches. The DG417 is normally closed, and the DG418 is normally open. The DG419 is single- pole/double-throw (SPDT) with one normally closed switch and one normally cpen switch. Switching times are less than 1/5ns max for ton and less than 145ns max for torr. Operation is from a single +10V to +30V supply, or bipolar 4.5V to +20V supplies. The improved DG417/DG418/DG419 are fabricated with a AAV silicon-gate process. Applications Communications Systems Sample-and-Hold Circuits Test Equipment Battery-Operated Systems Fax Machines PBX, PABX Military Radios Modems Guidance and Control Systems Audio Signal Routing MIAXLMAI New Features # Plug-In Upgrades for Industry-Standard DG417/DG418/DG419 + Improved Ros(on) Match Between Channels (3Q max, DG419 only) + Guaranteed RFLAT(ON) Over Signal Range (402 max) # Improved Charge Injection (10pC max} + Improved Off-Leakage Current Over Temperature (<5nA at +85C) # Withstand Electrostatic Discharge {2000V min) per Method 3015.7 Existing Features + Low Rpsyon} (8522 max) # Single-Supply Operation +10V to +30V Bipolar-Supply Operation 4.5V to 20V + Low Power Consumption (35yW max) + Rail-to-Rail Signal Handling + TTLICMOS-Logic Compatible Ordering Information PART TEMP. RANGE PIN-PACKAGE DG417CJ OC to +70C 8 Plastic DIP DG417CY OC to +70C 850 DG417C/D OPC to +70C Dice* DG417D -40C to +85C Plastic DIP DG417DY -40C to +85C 850 Ordering information continued at end of data sheet. * Contact factory for dice specifications. Pin Configurations/Functional Diagrams/Truth Tables TOP VIEW . a, a) s [i] _o7a_a] 0 [1] ofa ]a]0 bay fal nc, [2| 7] v- N.c. [2| 7 | v- 1 fz} 7 7] v- eno [3 inc} 6] IN GND [3 | ice] IN GND [3 ict Te] IN {| ANAXIAA | ANAXLAA | LAXLAA wl oon7 51 La pene |i! Te Mong [el DIP/SO DIP/SO DIP/SO 06a? DoAi8 DG49 [ose] SWITCH [ome || SWIICH [ose | SWICHT | SwiicH? 0 ON 0 OFF 0 ON OFF 1 OFF 1 ON 1 OFF ON N.C. = NO INTERNAL CONNECTION SWITCHES SHOWN FOR LOGIC "0" INPUT MAXIM Maxim integrated Products 1 For free samples & the latest literature: http:/www.maxim-ic.com, or phone 1-800-998-8800 6L790/81P9OU/LLP79dDG417/DG418/DG419 Improved, SPST/SPDT Analog Switches ABSOLUTE MAXIMUM RATINGS Voltage Referenced to V- Continuous Power Dissipation (Ta = +70C) MV occ ccc eecceeecneee tee sseeestescssasseeeeeeceeesnaeseneritesiteseeees 44yV Plastic DIP (derate 9.09mWiPC above +/0C) .... 72 7r0W CS 25 SO (derate 5.88mWC above +70C) oe 471mwWw Veet ne cnn (GND - 0.3V) to (V+ + 0.3V) CERDIP (derate 8.00mW/C above +70C) vei 640mW Digital Inputs Vs, Vp (Note 1)... (V-- 2V) to (V+ + 2V) or 30mA Operating Temperature Ranges (whichever occurs first) D4 Cece ccc cect tee ceceeeccsaesenesentseeeaes O to +70C Continuous Current (any terminal) (Note 1) 0... ee 30mA DCA Dc cect ees ecesceeteetenereese -A0C to +B85C Peak Current, S or D (pulsed at 1ms, 10% duty cycle max)..100mA DGAT_AK cece een areeteersaeneeneiteey -55C to +125C Storage Temperature RANQe ween -65C to +150C Lead Temperature (soldering, 10sec)... +300C Note 1: Signals on S, D, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward current to maximum current ratings. Stresses beyond those listed under "Absolute Maximum Ratings may Cause permanent damage to the device. These are stress ratings anly, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure io absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICSDual Supplies (V+ = +15V, V- = -15V, VL = 5V, GND = OV, Vin, = 0.8V, VINH = 2.4, TA = TMIN to TMAX, Unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN (Note 2) MAX UNITS SWITCH Analog Signal Range Vs ..Vp | (Note 3) -15 15 Vv C,0 20 35 orain-Souree Ve = 13.5, Ve =-13.5V,) 7, _ 9560 Ros(on) | Vp = +10, A 20 30 2 On-Resistance le = -10mA S=- 10m TA = TMIN to Tmax 45 On-Resistance Match Ve = 15V, V- = -15V, Ta = +25C 3 Between Channels ARos(on) | Vb = +10. Q (Nate 4) Ig = -10mA Ta = TMIN to Tmax 4 On-Resistance Flainess |, i - py V- = -18V, TA = +25C 4 O (Note 4) FLAT(ON)| Vb = +9, Is = -10mA TA = TMIN to TMAX 6 Source-Off V+ = 16.5, V- = -16.5V, | TA = +25C 0.25 0.25 Leakage Current IS(OFF) Vo = +15.5V, Ta = TmIn to C,D -5 5 nA (Note 5} Vs = F15.5V TMAX A -20 20 Ta = +25C -0.25 0.1 0.25 DG417, V+ =16.5, | DGa1g | TA=Tminto | .D = Drain-Off Ve = -16.5V TMAX A -20 aq Leakage Current ID(OFF) ~ 7 nA (Note 5) Vo = 15 5, Ta = +25C 075 O01 075 Vs==199Y | peai9 lt, =Twyto | D -10 10 TMAX A -40 40 Ta = +25C -0.4 0.4 DG41 7/ v+ =16.5v, | oG41g | TA=Tminto | D 10 10 Drain-On Ye = -16.5 TMAX A -40 40 Leakage Current ID(ON) Vv ; Vv ; nA (Note 5) p= +15.5V, Ta = +25C -0.75 0.75 s=#155V | oGai9 [T,-Twto | GD 0 10 TMAX A -40 40 2 MA AXLAAImproved, SPST/SPDT Analog Switches ELECTRICAL CHARACTERISTICSDual Supplies (continued) (V+ = +15V, V- = -15V, VL = 5V, GND = OV, VINL = 0.8V. VINH = 2.4Y, Ta = TMIN to TMAYX. Unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS {Note 2} LOGIC INPUT Logic Input Current with _ | Input Voltage High lINH Vin = 2.4V 0.5 0.005 0.5 LA Logic Input Current with _ | Input Voltage Low INL Vin = 0.8V 0.5 0.005 0.5 LA DYNAMIC DG417/DG418 Ta = +25C 100 175 Turn-On Time ns ON Vp = +10, Figure 2 Ta = TMIN to TMAX 250 DG417/DG418 Ta = +25C 60 145 Turn-Off Time a ns u OFF Vp = +10V, Figure 2 Ta = TMIN to TMAX 210 Transition Time tT DG419. Ta = 428C a ns iti i Break: Before- Make tp | DG419, V1 = Ve2 = +10V, Figure 4, Ta = +25C 5 13 ns Interval Charge Injection (Note 3) Q VGEN = OV, Figure 5, Ta = +25C 3 10 pe Off-lsolation . . Rejection Ratio (Note 6) OIRR Ry = 500Q, C_ = 5pF, f = IMHz, Figure 6, Ta = +25C 68 dB Crosstalk (Note 7) DG419, RL = 509, CL = 5pF, f = IMHz, Figure 7, as dB Ta = +25C Drain Off-Capacitance Cp orr | Vo = OV, f= MHz, Figure 8, Ta = +25C 8 pF Source Off-Capacitance | Csiorr) | Vp = OV. f = 1MHz. Figure 8, Ta = +25C 8 pF Drain-Source Colon) | Vs = OV, F=1MHZ. | pG417/DG418 30 : or Figure 9, pF On-Capacitance Ta = 425C Cs (on) | [A= + DG419 35 SUPPLY = -=- Ta = +25C -1 -0,0001 4 Positive Supply Current I+ V+ = 1B.SV, Vo = -16.5V, A LA Vin = OV or SV Ta = TMIN to TMAX 5 5 = -=- Ta = +25C -1 -0,0001 4 Negative Supply Current V+ = 16.5, V 16.5V, HA Vin = OV or 5V Ta = TIN to TMAX -5 5 = -=- Ta = +25C -1 -0,0001 4 Logic Supply Current IL V+ = T6.5, Ve = -16.BV, LA Vin = OV or SV Ta = TMIN to TMAX 5 5 = -=- Ta = +25C -1 -0,0001 4 Ground Current IGND V+ = 16.8V, V 16.5V, LA Vin = OV or SV Ta = TIN to TMAX 5 5 MAXIM 3 6L790/81P9OU/LLP79dDG417/DG418/DG419 Improved, SPST/SPDT Analog Switches ELECTRICAL CHARACTERISTICSSingle Supply (V+ =472V, V- = OV, VL = 5V, GND = OV, VINH = 2.4, VINL = 0.8V, Ta = +25C, unless otherwise noted.) MIN TYP MAX PARAMETER SYMBOL CONDITIONS (Note 2) UNITS SWITCH Analog Signal Range VaNaALocG | (Note 3) 0 12 Vv Drain-Source On-Resistance | Rosion) | Is = -10MA, Vp = 3.8V, V+ = 10.8V 40 100 Q DYNAMIC Turn-On Time ton D0G417/DG418, Vp = BY, Figure 2 110 ns Turm-Off Time lOFF D0G417/DG418, Vp = BY, Figure 2 40 ns Break-Before-Make Interval tp 06419, RL = 100082, Cy = 35pF, Fiqure 4 60 ns Charge Injection (Note 3) QO C_ = 10nF, Vcen = OV, Roen = OV, Figure 5 2 10 pc SUPPLY Positive Supply Current 1, | Ali channels on or off, Vr = 13.2N, -0.0001 yA VL = 5.25. Vin = OV or 5V . All channels on or off, V+ = 13.2V, Negative Supply Current - VL = 5.25, Vin - OV or 5V -0.0001 LA Logic Supply Current IL ON OV cre or off, VL = 5.25V, -9,9001 pA All channels on or off, VL = 5.25V, Ground Current IGND | iy OV or SV -0.0001 UA Note 2: Typical values are for design aid only, are not guaranteed, and are not subject to production testing. The algebraic convention where the most negative value is a minimum and the most positive value a maximum is usec in this data sheet. Note 3: Guaranteed by design. Note 4: On-resistance match between channels and flatness is quaranteed only with bipolar-supply operation. Flatness is defined as the difference between th maximum and the minimum value of on-resistance as measured at the extrernes of the specified analog range. Note 5: Leakage parameters Is(orr), ID(OFF). anc ID(ON) are 100% tested at the maximum rated hot temperature and guaranteed by correlation at +25C. Note 6: Off-lsolation Rejection Ratio = 20log (Vos), Vo = output, Vs = input to off switch. Note 7: Between any two switches. 4 MAAIMImproved, SPST/SPDT Analog Switches Typical Operating Characteristics (Ta = +25C, unless otherwise noted.) ON-RESISTANCE vs. Vp AND ON-RESISTANCE vs. Vp AND ON-RESISTANCE vs. Vp POWER-SUPPLY VOLTAGE TEMPERATURE (SINGLE SUPPLY) 50 = 35 * 140 2 w (eyo Ve 18V ft B: V+ = 10, 30 f= T5 Ty = 4125C] 120 40 : Ye=-1 | Cr V+ = 15, 25 BR 100 a 3 Y. = -15V a AN] aA a 2 30 D: V+ = 20V, = Ms 4 fl = 2 = i z S Ye =- S 2 a ~ rd S 80 Z 25 z XP * A, z mo 15 ae 60 5 m_| Ta = -55C 10 Ta=+25C 40 10 | | 5 5 20 20 -10 0 10 20 20 10 0 10 20 20 Vp (V} Vo (} Vb {v) ON-RESISTANCE vs. Vp AND OFF-LEAKAGE CURRENT vs. ON-LEAKAGE CURRENT vs. TEMPERATURE TEMPERATURE TEMPERATURE 70 = 100 r 100 V+=12 5 Ve = 16.5 5 Ve = 16.5 5 V-=0 8 - = -16.5V a Ve = -16.5 a 60 10 yp = et5y 10 Fb yp =215 Ths 4125C _ Vg = T15 Vg = 15 50 fo | = 1 A zr 4 Lf & NLA 1 85 c 4 | 3 = = +85" Q 29 |Z =o | Sat x z Ly [| & - = 7 te | Ta = 425C Z a 30 | ned & 0.01 7 2 0.01 4 20 0.001 0.001 AO #7 #4) 10 0.0001 0.0001 0 5 10 15 20 15 25 125 75 5 125 Vo) TEMPERATURE {C} TEMPERATURE (C} CHARGE INJECTION vs. SUPPLY CURRENT vs. ANALOG VOLTAGE TEMPERATURE 60 100 = Va 15 z Ar i+ atV+ = 16.5 z Ve = -15V 3 B: |- at V- = -16.5V 8 40 10 Pee iy at -a 4 ~ 3 i=) 1 = 0 = 0.1 o \ = al = -20 0.01 -40 9.001 60 0.0001 20-15-10 -5 0 5 10 15 20 75 25 125 Vp (} TEMPERATURE {C} MAXIM 5 6LP9C/8LP9OU/LLP79dDG417/DG418/DG419 Improved, SPST/SPDT Analog Switches Pin Description PIN DG417 | DG41s | DG419 NAME FUNCTION 1 _ _ S Analog-Switch Source Terminal (normally closed) _ 1 _ S Analog-Switch Source Terminal (normally open) 2 $1 Analog-Switch Source Terminal 1 (normally closed) 2 2 _ N.C. No Internal Connection 3 3 3 GND Logic Ground 4 4 4 V+ Analog-Signal Positive Supply Input 5 5 5 VL Logic-Level Positive Supoly Input 6 6 8 IN Logic-Level Inout 7 7 7 Y- Analog-Signal Negative Supply Input 8 8 1 D Analog-Switch Drain Terminal _ _ 8 $2 Analog-Switch Source Terminal 2 (normally open) Applications information Operation with Supply Voltages Other than +15V Using supply voltages other than +15V reduces the analog signal range. The DG417/DG418/DG419 switch- s operate with +4.5V to +20V bipolar supplies or with a +10 to +30V single supply; connect V- to OV when operating with a single supply. Also, all device types can operate with unbalanced supplies, such as +24V and -5. VL must be connected to +5V to be TTL com- patible, or to V+ for CMOS-logic level inputs. The lypical Operating Characteristics graphs show typical on-resistance with +20V, +15V, +10V, and +5V sup- plies. (Switching times increase by a factor of two or more for operation at +5V.} Overvoltage Pretection Proper power-supply sequencing is recommended for all CMOS cevices. Do not exceed the absolute maxi- mum ratings because stresses beyonce the listed rat- ings may cause permanent damage to the devices. Always sequence V+ on first, followed by VL, V-, and logic inputs. If power-supply sequencing is not possi- ble, add two small, external signal diodes in series with the supply pins for avervoltage protection (Figure 1). $ ova D Vg l MAALSA | DG47_ y- figure 7. Overvoltage Protection Using External Blocking Diodes Adding diodes reduces the analog signal range to 1V below V+ and 1V above V-, without affecting low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between V+ and V- should not exceed +44V. MAAIMImproved, SPST/SPDT Analog Switches Test Circutts/Timing Diagrams vy ta < 20ns Logic * ftps 205 INPUT 50% r oy __? i te| [OFF |-< YOu oxy O9Ki SWITCH py f OUT ae tou OUTPUT t | toy | LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. JVLAXLAA BY +15 DG47 | | BG478 SWITCH VL switch |p -. 5 OUTPUT INPUT ~. Po. ta , <= 30002 35F Pee ep 1 L GND ve = = Logic 1) INPUT T Lt | CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL Your = Vo ( RL+ Rosia) figure 2. DG417DG418 Switching Time ay ta < 20ns LOGIC 50% i tp < 20ns INPUT gy trans. [- m) TRANS |=at swiTcH Your 0.8 Your | OUTPUT p, 0.8 X Voure / Youre = [M___ #VLAXLAA DGFTE +15 +o | | si V+ L RG D Vour _|S2@ at ' RL C. ! SS IN ho =, 100k S5pF L os LaGIC O GND V- oe INPUT LL J ~ C_ INCLUDES FIXTURE AND STRAY CAPACITANCE, figure 3. DG419 Transition lime MAXIM 6L790/81P9OU/LLP79dDG417/DG418/DG419 Improved, SPST/SPDT Analog Switches Test Circuits/Timing Diagrams (continued) LOGIC + INPUT fm Ov = ouTI ee SWITCH ov OUTPUT 1 Yout2 [~ 0.9 x Your SWITCH Your OUTPUT 2 | 0 ~ MA AXAILAA DG4IP +10 _|___, 92 ~ D VOUT o[_" _+ | << RL CL = sion 35pF IN1, IN2 lS | | LOGIC J GND y- i INPUT Bu | I T = 15 C_ INCLUDES FIXTURE AND STRAY CAPACITANCE. figure 4. DG419 Break-Before-Make terval Your \ N ON re ON \ IN " Q = AVour x CL IN DEPENDS ON SWITCH CONFIGURATION: INPUT POLARITY DETERMINED BY SENSE OF SWITCH. /VLAXLAA +5V +15 OG47 | GHB VL We DG4T9 3 of D T VouT i Vorn _ fy CL | GND | 10nF figure. Charge ityection MAAIMImproved, SPST/SPDT Analog Switches Test Circuits/Timing Diagrams (continued) 6L790/81P9OU/LLP79d JU AXLWVI 15V BV ODG: MAXLVI sone * + 417 1OnF 415 +V 419 OG4IB + OG4I9 SIGNAL = SIGNAL = n m1 GENERATOR OdBi - ve YL GENERATOR 0dBm D 50a oO D [ ey op 51 ian AAA & t OV or o + i + "L 7 | = = [IN pi = cere A a = oor24y Of ed Y t NETWORK ~~ |Slors2 f = NETWORK ~~ 182 at D ANALYZER * ANALYZER * ca mo < END Yd sank a GND V- 1OnF SS al 4 + | t J < | = = -15V = = = -15 = Figure 6. Off-iseiation Rejection Ratio Figure 7, DG419 Crosstatk sy AN AXL/VI asy ay AMA AXLAA + + one 8 * DOAIT *On aG4i? DG4IE 4} |* |e | DG4I9 a | BG419 ~ Ve L ~ Ve vL D D a oC 4\s 4 j' - ' Q vy IN OV or yy IN OV or CAPACITANCE |_- ' grnmernees To ay CAPACITANCE Lf ! wns <f- t+ ay METER , METER i wf S of 5 | = f= IMHz = OND u. Oak f= MHz = CND v sone I -15 1 L -15 1 Figure & Drain-Source Of Capackance MAXIM Figure 9. Drain-Source On-CapachariceDG417/DG418/DG419 Improved, SPST/SPDT Analog Switches __ Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE DG417DK -40C to +85C 8 CERDIP DG417AK -56C to +1256C 8 CERDIP** DG418C] C to +70C 8 Plastic DIP DG418CY OPC to +70C 8 SO DG418C/D 0C to +70C Dice* DG418DJ -40C to +85C 8 Plastic DIP DG418DY -40C to +85C 850 DG418DK -4A0C to +85C 8 CERDIP DG418AK -08C to +125C 8 CERDIP** DG419CL 0C to + 70C 8 Plastic DIP DG419CY 0C to +70C 8 50 DG419C/D OC ta +70C Dice* DG419DJ -40C to +85C 8 Plastic DIP DG419DY -40C to +85C 850 DG419DK -40C to +85C 8 CERDIP DG419AK -55C to +125C 8 CERDIP** *Comact factory for aice specifications. Conact factory for avaiability and processing to MIL-STD-8838. 10 Chip Topography 4 9 0.076" 1.93mm a 5 0,058" 1.47mm TRANSISTOR COUNT: 32 SUBSTRATE CONNECTED TO V+ DIE PAD DG417 DG418 DG419 1 D N.C, 5 2 GND GND GND 3 V+ V+ V+ 4 VL VL VL 5 IN IN IN 6 V- V- V- 7 NLC, S 5 8 N.C, BD D 9 S N.C. D MAAIMImproved, SPST/SPDT Analog Switches Package Information MAXIM pe EF y SP i +] a et | | | E Te A fo o 3 G1"5 [316 [445 ] De DO.745 [0.755 [16.32 [19.43 [16 5 7 cals c > NOTES: DRE OO NOT INCLUDE MOLD FLASH MOLD FLASH OP eee TOM MOT TO EACEED 15mm 00 . CONTROLLING TINENSION MILLIMETER t 10.240 (0.310 [610 [7.87 5 i MEETS JEDEC Ms00]-*% AS SHOWN 5 6 IN ABOVE TABLE SIMILIAF TO JEDEC MO-058AB N= SUNBER OF PINS a {I MAXI | PACKAGE FAMILY OUTLINE: PUIP 300" [! , [21-0043 A bE. uate e DLE DO NOT INCLUDE MOLD FLASH MOLD FLASH OF PROTRUSIONS NOT TO ExXCEEO 15mm 006%) u H]U.ce8 [f.c44) 5.80) 4.20 do2mm 004% . CONTROLLING DIMENSIOM MILLIMETER MEETS JEQEC MSgie-** AS SHOWN IN ABOVE TABLE . N= SUMBER OF PINS NOT 1 2 3, LEADS 170 BE COPLANAR WITHIM 4 5 5. AA AKLAYAPacvace FaMiLy OUTLINE: SOIC to [4 [21-0041 4 Fe La eae ghia ares OEM) COW AUPE _ REL 11 6LP9CG/8LP9OU/LLP79dDG417/DG418/DG419 Improved, SPST/SPDT Analog Switches pal | [" es YT) | i 4 [I : 2 Bl EB Package Information (continued) De] r al le NOTES: 1 CONTROLLING DIMENCION: INCH 2 MEETS 1835 CASE OUTLINE CONFIGURATION 44 43 SHOWwh JN ABOWE TABLE 3 N = NUMBER OF PINS AA ALAA |Peciace FawILY OUTLINE: COIP 300 (4 [21-0045 4 | IDM CTO MEW Maxim cannot assume responsibility for use of any circuitry ether than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 940386 (408) 737-7600 1996 Maxim Integrated Products Printed USA AAAXALM js 2 registered trademark of Maxim Integrated Products.