1M Static RAMs
03/05/99–LDS.106-F
1
DEVICES INCORPORATED
L7C106
256K x 4 Static RAM
minimum access time, or when the
memory is deselected. In addition,
data may be retained in inactive
storage with a supply voltage as low
as 2 V. The L7C106 consumes only
1.5 mW (typical), at 3 V, allowing
effective battery backup operation.
The L7C106 provides asynchronous
(unclocked) operation with matching
access and cycle times. An active-low
Chip Enable and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
Memory locations are specified on
address pins A0 through A17. Reading
from a designated location is
accomplished by presenting an
address and driving CE and OE LOW
while WE remains HIGH. The data in
the addressed memory location will
then appear on the Data Out pins
within one access time. The output
pins stay in a high-impedance state
when CE or OE is HIGH, or WE is
LOW.
Writing to an addressed location is
accomplished when the active-low CE
and WE inputs are both LOW. Either
signal may be used to terminate the
write operation. Data In and Data Out
signals have the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C106 can
withstand an injection current of up to
200 mA on any pin without damage.
q256K x 4 Static RAM with Chip
Select Powerdown, Output Enable
qAuto-Powerdown™ Design
qAdvanced CMOS Technology
qHigh Speed — to 17 ns maximum
qLow Power Operation
Active: 400 mW typical at 25 ns
Standby: 5 mW typical
qData Retention at 2 V for Battery
Backup Operation
qPlug Compatible with Cypress
CY7C106
qPackage Styles Available:
• 28-pin Plastic DIP
• 28-pin Sidebraze, Hermetic DIP
• 28-pin Plastic SOJ
FEATURES DESCRIPTION
L7C106
256K x 4 Static RAM
DEVICES INCORPORATED
The L7C106 is a high-performance,
low-power CMOS static RAM. The
storage circuitry is organized as 262,144
words by 4 bits per word. The 4 Data
In and Data Out signals share I/O pins.
The L7C106 has an active-low Chip
Enable and a separate Output Enable.
This device is available in three speeds
with maximum access times from 17 ns
to 25 ns.
Inputs and outputs are TTL compat-
ible. Operation is from a single +5 V
power supply. Power consumption
is 400 mW (typical) at 25 ns. Dissipa-
tion drops to 50 mW (typical) when
the memory is deselected.
Two standby modes are available.
Proprietary Auto-Powerdown™
circuitry reduces power consumption
automatically during read or write
accesses which are longer than the
L7C106 BLOCK DIAGRAM
ROW
ADDRESS
COLUMN SELECT
& COLUMN SENSE
ROW SELECT
I/O
3-0
9
COLUMN ADDRESS
512 x 512 x 4
MEMORY
ARRAY
9
4
CONTROL
OE
WE
CE
OBSOLETE
DEVICES INCORPORATED
L7C106
256K x 4 Static RAM
1M Static RAMs
03/05/99–LDS.106-F
2
MAXIMUM RATINGS
Above which useful life may be impaired (Notes 1, 2)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ................................................................................................................ ............... > 200 mA
OPERATING CONDITIONS
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Active Operation, Commercial 0°C to +70°C 4.5 V ≤ VCC ≤ 5.5 V
Active Operation, Industrial –40°C to +85°C 4.5 V ≤ VCC ≤ 5.5 V
Data Retention, Commercial 0°C to +70°C 2.0 V ≤ VCC ≤ 5.5 V
Data Retention, Industrial –40°C to +85°C 2.0 V ≤ VCC ≤ 5.5 V
L7C106
Symbol Parameter Test Condition Min Typ Max Unit
VOH Output High Voltage VCC = 4.5 V, IOH = –4.0 mA 2.4 V
VOL Output Low Voltage IOL = 8.0 mA 0.4 V
VIH Input High Voltage 2.2 VCC V
+0.3
VIL Input Low Voltage (Note 3) –3.0 0.8 V
IIX Input Leakage Current GND ≤ VIN ≤ VCC –10 +10 µA
IOZ Output Leakage Current (Note 4) –10 +10 µA
ICC2 VCC Current, TTL Inactive (Note 7) 10 20 mA
ICC3 VCC Current, CMOS Standby (Note 8) 1 4.0 mA
ICC4 VCC Current, Data Retention VCC = 3.0 V (Notes 9, 10) 500 1000 µA
CIN Input Capacitance Ambient Temp = 25°C, VCC = 5.0 V 5 pF
COUT Output Capacitance Test Frequency = 1 MHz (Note 10) 7pF
ELECTRICAL CHARACTERISTICS
Over Operating Conditions (Note 5)
L7C106-
Symbol Parameter Test Condition 25 20 17 Unit
ICC1 VCC Current, Active (Note 6) 100 125 145 mA
OBSOLETE
1M Static RAMs
03/05/99–LDS.106-F
3
DEVICES INCORPORATED
L7C106
256K x 4 Static RAM
L7C106–
25 20 17
Symbol Parameter Min Max Min Max Min Max
tAVAV Read Cycle Time 25 20 17
tAVQV Address Valid to Output Valid (Notes 13, 14) 25 20 17
tAXQX Address Change to Output Change 3 3 3
tCLQV Chip Enable Low to Output Valid (Notes 13, 15) 25 20 17
tCLQZ Chip Enable Low to Output Low Z (Notes 20, 21) 333
tCHQZ Chip Enable High to Output High Z (Notes 20, 21) 10 8 8
tOLQV Output Enable Low to Output Valid 10 10 9
tOLQZ Output Enable Low to Output Low Z (Notes 20, 21) 000
tOHQZ Output Enable High to Output High Z (Notes 20, 21) 10 7 6
tPU Input Transition to Power Up (Notes 10, 19) 000
tPD Power Up to Power Down (Notes 10, 19) 25 20 17
tCHVL Chip Enable High to Data Retention (Note 10) 000
SWITCHING CHARACTERISTICS
Over Operating Range
READ CYCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
READ CYCLE — ADDRESS CONTROLLED
Notes 13, 14
READ CYCLE — CE/OE CONTROLLED
Notes 13, 15
DATA RETENTION
Notes 9, 10
PREVIOUS DATA VALID DATA VALID
ADDRESS
DATA OUT
t
AVAV
I
CC
t
PD
t
AVQV
t
AXQX
t
PU
HIGH
IMPEDANCE
DATA VALID
HIGH IMPEDANCE
DATA OUT
50% 50%
t
PU
I
CC
OE
t
OLQZ
t
PD
t
AVAV
t
OHQZ
t
CHQZ
t
OLQV
t
CLQZ
t
CLQV
CE
4.5 V
DATA RETENTION MODE
4.5 V
CE
V
CC
t
CHVL
t
AVAV
V
IH
V
IH
≥ 2 V
OBSOLETE
DEVICES INCORPORATED
L7C106
256K x 4 Static RAM
1M Static RAMs
03/05/99–LDS.106-F
4
SWITCHING CHARACTERISTICS
Over Operating Range
L7C106–
25 20 17
Symbol Parameter Min Max Min Max Min Max
tAVAV Write Cycle Time 20 20 17
tCLEW Chip Enable Low to End of Write Cycle 15 15 13
tAVBW Address Valid to Beginning of Write Cycle 0 0 0
tAVEW Address Valid to End of Write Cycle 15 15 13
tEWAX End of Write Cycle to Address Change 0 0 0
tWLEW Write Enable Low to End of Write Cycle 15 15 13
tDVEW Data Valid to End of Write Cycle 10 9 8
tEWDX End of Write Cycle to Data Change 0 0 0
tWHQZ Write Enable High to Output Low Z (Notes 20, 21) 000
tWLQZ Write Enable Low to Output High Z (Notes 20, 21) 776
WRITE CYCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
WRITE CYCLE — WE CONTROLLED
Notes 16, 17, 18, 19
WRITE CYCLE — CE CONTROLLED
Notes 16, 17, 18, 19
DATA-IN VALID
HIGH IMPEDANCE
ADDRESS
DATA OUT
DATA IN
t
PD
CE
I
CC
WE
t
WLQZ
t
PU
t
PU
t
DVEW
t
EWDX
t
WHQZ
t
EWAX
t
WLEW
t
AVEW
t
CLEW
t
AVBW
t
AVAV
DATA-IN VALID
ADDRESS
DATA IN
HIGH IMPEDANCE
tAVBW
WE
tAVAV
tCLEW
tAVEW tWLEW
tDVEW tEWDX
tEWAX
tPDtPU
CE
I
CC
DATA OUT
OBSOLETE
1M Static RAMs
03/05/99–LDS.106-F
5
DEVICES INCORPORATED
L7C106
256K x 4 Static RAM
1. Maximum Ratings indicate stress specifi-
cations only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating con-
ditions for extended periods may affect re-
liability of the tested device.
2. The products described by this specifica-
tion include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive elec-
trical stress values.
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V.
A current in excess of 100 mA is required to
reach –2.0 V. The device can withstand in-
definite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
4. Tested with GND ≤ VOUT ≤ VCC. The
device is disabled, i.e., CE = VCC.
5. A series of normalized curves is available
to supply the designer with typical DC and
AC parametric information for Logic Devices
Static RAMs. These curves may be used to
determine device characteristics at various
temperatures and voltage levels.
6. Tested with all address and data inputs
changing at the maximum cycle rate. The
device is continuously enabled for writing,
i.e., CE ≤ VIL, WE ≤ VIL. Input pulse levels
are 0 to 3.0 V.
7. Tested with outputs open and all address
and data inputs changing at the maximum
read cycle rate. The device is continuously
disabled, i.e., CE ≥ VIH.
8. Tested with outputs open and all address
and data inputs stable. The device is con-
tinuously disabled, i.e., CE = VCC. Input
levels are within 0.2 V of VCC or GND.
9. Data retention operation requires that
VCC never drop below 2.0 V. CE must be
≥VCC – 0.2 V. All other inputs must meet
VIN ≥ VCC – 0.2 V or VIN ≤ 0.2 V to ensure
full powerdown. For low power version (if
applicable), this requirement applies only to
CE and WE; there are no restrictions on data
and address.
10. These parameters are guaranteed but
not 100% tested.
NOTES
+5 V
OUTPUT
R
1
480Ω
30 pF R
2
255Ω
INCLUDING
JIG AND
SCOPE
11. Test conditions assume input transition
times of less than 3 ns, reference levels of
1.5 V, output loading for specified IOL and
IOH plus 30 pF (Fig. 1a), and input pulse
levels of 0 to 3.0 V (Fig. 2).
12. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the exter-
nal system driving the chip. For example,
tAVEW is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-
ments of all parts. Responses from the inter-
nal circuitry are specified from the point of
view of the device. Access time, for ex-
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
13. WE is high for the read cycle.
14. The chip is continuously selected (CE
low).
15. All address lines are valid prior-to or
coincident-with the CE transition to active.
16. The internal write cycle of the memory
is defined by the overlap of CE active and
WE low. All three signals must be active to
initiate a write. Any signal can terminate a
write by going inactive. The address, data,
and control input setup and hold times
should be referenced to the signal that be-
comes active last or becomes inactive first.
17. If WE goes low before or concurrent
with the latter of CE going active, the output
remains in a high impedance state.
18. If CE goes inactive before or concurrent
with WE going high, the output remains in
a high impedance state.
19. Powerup from ICC2 to ICC1 occurs as a
result of any of the following conditions:
a. Falling edge of CE.
b. Falling edge of WE (CE active).
c. Transition on any address line (CE
active).
d. Transition on any data line (CE, and WE
active).
The device automatically powers down
from ICC1 to ICC2 after tPD has elapsed from
any of the prior conditions. This means that
power dissipation is dependent on only
cycle rate, and is not on Chip Select pulse
width.
20. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
21. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 1b. This parameter is sampled and
not 100% tested.
22. All address timings are referenced from
the last valid address line to the first transi-
tioning address line.
23. CE or WE must be inactive during ad-
dress transitions.
24. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. In-
adequate attention to setups and proce-
dures can cause a good part to be rejected as
faulty. Long high inductance leads that
cause supply bounce must be avoided by
bringing the VCC and ground planes di-
rectly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required
between VCC and ground. To avoid signal
reflections, proper terminations must be
used.
FIGURE 1a.
<3 ns
GND
+3.0 V 90%
10%
90%
10%
<3 ns
FIGURE 2.
+5 V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R
1
480Ω
R
2
255Ω
FIGURE 1b.
OBSOLETE
DEVICES INCORPORATED
L7C106
256K x 4 Static RAM
1M Static RAMs
03/05/99–LDS.106-F
6
28-pin — 0.4" wide 28-pin — 0.4" wide
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CE
OE
GND
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CE
OE
GND
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
ORDERING INFORMATION
0°C to +70°C — COMMERCIAL SCREENING
–40°C to +85°C — COMMERCIAL SCREENING
Sidebraze Hermetic DIP
(D11)
L7C106DC25
L7C106DC20
L7C106DC17
Plastic DIP
(P11)
L7C106PC25
L7C106PC20
L7C106PC17
L7C106PI25
L7C106PI20
L7C106PI17
Plastic SOJ
(W7)
L7C106WC25
L7C106WC20
L7C106WC17
L7C106WI25
L7C106WI20
L7C106WI17
Speed
25 ns
20 ns
17 ns
25 ns
20 ns
17 ns
OBSOLETE
