L7C106 L7C106 DEVICES INCORPORATED 256K x 4 Static RAM 256K x 4 Static RAM DEVICES INCORPORATED DESCRIPTION The L7C106 is a high-performance, low-power CMOS static RAM. The storage circuitry is organized as 262,144 words by 4 bits per word. The 4 Data In and Data Out signals share I/O pins. The L7C106 has an active-low Chip Enable and a separate Output Enable. This device is available in three speeds with maximum access times from 17 ns to 25 ns. Inputs and outputs are TTL compatible. Operation is from a single +5 V power supply. Power consumption is 400 mW (typical) at 25 ns. Dissipation drops to 50 mW (typical) when the memory is deselected. Two standby modes are available. Proprietary Auto-PowerdownTM circuitry reduces power consumption automatically during read or write accesses which are longer than the O CE WE OE CONTROL The L7C106 provides asynchronous (unclocked) operation with matching access and cycle times. An active-low Chip Enable and a three-state I/O bus with a separate Output Enable control simplify the connection of several chips for increased storage capacity. Memory locations are specified on address pins A0 through A17. Reading from a designated location is accomplished by presenting an address and driving CE and OE LOW while WE remains HIGH. The data in the addressed memory location will then appear on the Data Out pins within one access time. The output pins stay in a high-impedance state when CE or OE is HIGH, or WE is LOW. O Writing to an addressed location is accomplished when the active-low CE and WE inputs are both LOW. Either signal may be used to terminate the write operation. Data In and Data Out signals have the same polarity. 512 x 512 x 4 MEMORY ARRAY BS 9 ROW SELECT L7C106 BLOCK DIAGRAM ROW ADDRESS minimum access time, or when the memory is deselected. In addition, data may be retained in inactive storage with a supply voltage as low as 2 V. The L7C106 consumes only 1.5 mW (typical), at 3 V, allowing effective battery backup operation. TE q 256K x 4 Static RAM with Chip Select Powerdown, Output Enable q Auto-PowerdownTM Design q Advanced CMOS Technology q High Speed -- to 17 ns maximum q Low Power Operation Active: 400 mW typical at 25 ns Standby: 5 mW typical q Data Retention at 2 V for Battery Backup Operation q Plug Compatible with Cypress CY7C106 q Package Styles Available: * 28-pin Plastic DIP * 28-pin Sidebraze, Hermetic DIP * 28-pin Plastic SOJ LE FEATURES 4 COLUMN SELECT & COLUMN SENSE I/O 3-0 Latchup and static discharge protection are provided on-chip. The L7C106 can withstand an injection current of up to 200 mA on any pin without damage. 9 COLUMN ADDRESS 1M Static RAMs 1 03/05/99-LDS.106-F L7C106 DEVICES INCORPORATED 256K x 4 Static RAM MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2) Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ -3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 200 mA Mode Active Operation, Commercial Active Operation, Industrial Data Retention, Commercial Data Retention, Industrial Temperature Range (Ambient) 0C to +70C -40C to +85C 0C to +70C -40C to +85C Supply Voltage 4.5 V VCC 5.5 V 4.5 V VCC 5.5 V 2.0 V VCC 5.5 V 2.0 V VCC 5.5 V LE ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5) L7C106 Parameter Test Condition Min VOH Output High Voltage VCC = 4.5 V, IOH = -4.0 mA 2.4 VOL Output Low Voltage IOL = 8.0 mA VIH Input High Voltage VIL Input Low Voltage IIX Input Leakage Current IOZ Output Leakage Current (Note 4) ICC2 VCC Current, TTL Inactive (Note 7) ICC3 VCC Current, CMOS Standby (Note 8) ICC4 VCC Current, Data Retention VCC = 3.0 V (Notes 9, 10) CIN Input Capacitance COUT Symbol ICC1 Output Capacitance Typ Max Unit V V 2.2 VCC +0.3 V -3.0 0.8 V -10 +10 A -10 +10 A 10 20 mA 1 4.0 mA 500 1000 A Ambient Temp = 25C, VCC = 5.0 V 5 pF Test Frequency = 1 MHz (Note 10) 7 pF O 0.4 (Note 3) GND VIN VCC BS O Symbol TE OPERATING CONDITIONS To meet specified electrical and switching characteristics L7C106- Parameter Test Condition VCC Current, Active (Note 6) 25 20 17 Unit 100 125 145 mA 1M Static RAMs 2 03/05/99-LDS.106-F L7C106 DEVICES INCORPORATED 256K x 4 Static RAM SWITCHING CHARACTERISTICS Over Operating Range READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C106- 25 Symbol Parameter Min tAVAV Read Cycle Time tAVQV Address Valid to Output Valid (Notes 13, 14) tAXQX Address Change to Output Change tCLQV Chip Enable Low to Output Valid (Notes 13, 15) tCLQZ Chip Enable Low to Output Low Z (Notes 20, 21) tCHQZ Chip Enable High to Output High Z (Notes 20, 21) tOLQV Output Enable Low to Output Valid tOLQZ Output Enable Low to Output Low Z (Notes 20, 21) tOHQZ Output Enable High to Output High Z (Notes 20, 21) tPU Input Transition to Power Up (Notes 10, 19) tPD Power Up to Power Down (Notes 10, 19) tCHVL Chip Enable High to Data Retention (Note 10) 20 Max 25 Min 17 Max 20 25 3 25 17 17 3 20 17 3 TE 3 10 8 8 10 10 9 0 0 10 0 LE 0 7 0 25 0 Max 20 3 3 Min 6 0 20 0 17 0 READ CYCLE -- ADDRESS CONTROLLED Notes 13, 14 tAVAV ADDRESS tAVQV DATA OUT PREVIOUS DATA VALID tAXQX tPD O tPU DATA VALID ICC CE BS READ CYCLE -- CE/OE CONTROLLED Notes 13, 15 tAVAV tCLQV tCHQZ tCLQZ OE tOLQZ DATA OUT tOLQV tPU O ICC tOHQZ HIGH IMPEDANCE DATA VALID HIGH IMPEDANCE tPD 50% 50% DATA RETENTION Notes 9, 10 DATA RETENTION MODE 4.5 V VCC 4.5 V tCHVL CE 2V tAVAV VIH VIH 1M Static RAMs 3 03/05/99-LDS.106-F L7C106 DEVICES INCORPORATED 256K x 4 Static RAM SWITCHING CHARACTERISTICS Over Operating Range WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns) L7C106- 25 Min 20 Max Parameter tAVAV Write Cycle Time 20 20 17 tCLEW Chip Enable Low to End of Write Cycle 15 15 13 tAVBW Address Valid to Beginning of Write Cycle 0 0 0 tAVEW Address Valid to End of Write Cycle 15 15 13 tEWAX End of Write Cycle to Address Change tWLEW Write Enable Low to End of Write Cycle tDVEW Data Valid to End of Write Cycle tEWDX End of Write Cycle to Data Change tWHQZ Write Enable High to Output Low Z (Notes 20, 21) tWLQZ Write Enable Low to Output High Z (Notes 20, 21) Max 0 15 15 13 10 9 8 0 0 0 0 0 7 LE WRITE CYCLE -- WE CONTROLLED Notes 16, 17, 18, 19 Min Max 0 TE 0 Min 17 Symbol 7 0 6 tAVAV ADDRESS tCLEW CE tAVEW tDVEW O tAVBW DATA IN tEWDX DATA-IN VALID tWLQZ DATA OUT HIGH IMPEDANCE tPU tWHQZ tPD tPU BS ICC tEWAX tWLEW WE WRITE CYCLE -- CE CONTROLLED Notes 16, 17, 18, 19 ADDRESS tAVAV tAVBW O CE tCLEW tAVEW tEWAX tWLEW WE tDVEW DATA IN DATA OUT tEWDX DATA-IN VALID HIGH IMPEDANCE tPU tPD ICC 1M Static RAMs 4 03/05/99-LDS.106-F L7C106 DEVICES INCORPORATED 256K x 4 Static RAM NOTES 3. This product provides hard clamping of transient undershoot. Input levels below ground will be clamped beginning at -0.6 V. A current in excess of 100 mA is required to reach -2.0 V. The device can withstand indefinite operation with inputs as low as -3 V subject only to power dissipation and bond wire fusing constraints. 4. Tested with GND VOUT VCC. The device is disabled, i.e., CE = VCC. 13. WE is high for the read cycle. 14. The chip is continuously selected (CE low). 15. All address lines are valid prior-to or coincident-with the CE transition to active. 16. The internal write cycle of the memory is defined by the overlap of CE active and WE low. All three signals must be active to initiate a write. Any signal can terminate a write by going inactive. The address, data, and control input setup and hold times should be referenced to the signal that becomes active last or becomes inactive first. 17. If WE goes low before or concurrent with the latter of CE going active, the output remains in a high impedance state. O 5. A series of normalized curves is available to supply the designer with typical DC and AC parametric information for Logic Devices Static RAMs. These curves may be used to determine device characteristics at various temperatures and voltage levels. 12. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. For example, tAVEW is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Access time, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 6. Tested with all address and data inputs changing at the maximum cycle rate. The device is continuously enabled for writing, i.e., CE VIL, WE VIL. Input pulse levels are 0 to 3.0 V. 8. Tested with outputs open and all address and data inputs stable. The device is continuously disabled, i.e., CE = VCC. Input levels are within 0.2 V of VCC or GND. O 9. Data retention operation requires that VCC never drop below 2.0 V. CE must be VCC - 0.2 V. All other inputs must meet VIN VCC - 0.2 V or VIN 0.2 V to ensure full powerdown. For low power version (if applicable), this requirement applies only to CE and WE; there are no restrictions on data and address. 21. Transition is measured 200 mV from steady state voltage with specified loading in Fig. 1b. This parameter is sampled and not 100% tested. 22. All address timings are referenced from the last valid address line to the first transitioning address line. 23. CE or WE must be inactive during address transitions. 24. This product is a very high speed device and care must be taken during testing in order to realize valid test information. Inadequate attention to setups and procedures can cause a good part to be rejected as faulty. Long high inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper terminations must be used. FIGURE 1a. R 1 480 +5 V OUTPUT INCLUDING JIG AND SCOPE 18. If CE goes inactive before or concurrent with WE going high, the output remains in a high impedance state. BS 7. Tested with outputs open and all address and data inputs changing at the maximum read cycle rate. The device is continuously disabled, i.e., CE VIH. 20. At any given temperature and voltage condition, output disable time is less than output enable time for any given device. TE 2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 11. Test conditions assume input transition times of less than 3 ns, reference levels of 1.5 V, output loading for specified IOL and IOH plus 30 pF (Fig. 1a), and input pulse levels of 0 to 3.0 V (Fig. 2). LE 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability of the tested device. 19. Powerup from ICC2 to ICC1 occurs as a result of any of the following conditions: R2 255 30 pF FIGURE 1b. a. Falling edge of CE. b. Falling edge of WE (CE active). c. Transition on any address line (CE active). OUTPUT d. Transition on any data line (CE, and WE active). The device automatically powers down from ICC1 to ICC2 after tPD has elapsed from any of the prior conditions. This means that power dissipation is dependent on only cycle rate, and is not on Chip Select pulse width. 10. These parameters are guaranteed but not 100% tested. R1 480 +5 V INCLUDING JIG AND SCOPE R2 255 5 pF FIGURE 2. +3.0 V GND 90% 10% <3 ns 90% 10% <3 ns 1M Static RAMs 5 03/05/99-LDS.106-F L7C106 DEVICES INCORPORATED 256K x 4 Static RAM ORDERING INFORMATION 28-pin -- 0.4" wide 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE TE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Speed Plastic DIP (P11) O LE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 28-pin -- 0.4" wide Sidebraze Hermetic DIP (D11) Plastic SOJ (W7) 25 ns 20 ns 17 ns BS 0C to +70C -- COMMERCIAL SCREENING L7C106PC25 L7C106PC20 L7C106PC17 L7C106DC25 L7C106DC20 L7C106DC17 L7C106WC25 L7C106WC20 L7C106WC17 -40C to +85C -- COMMERCIAL SCREENING L7C106PI25 L7C106PI20 L7C106PI17 L7C106WI25 L7C106WI20 L7C106WI17 O 25 ns 20 ns 17 ns 1M Static RAMs 6 03/05/99-LDS.106-F