K4R571669A-FCK8 - Samsung Electronics

Direct RDRAM™

K4R571669A/K4R881869A

Page -1 Version 1.4 July 2002

July 2002

Version 1.4

Direct RDRAMTM

512K x 16/18bit x 32s banks

256/288Mbit RDRAM(A-die)

Direct RDRAM™

K4R571669A/K4R881869A

Page 0 Version 1.4 July 2002

Change History

Version 1.11( September 2001) - Preliminary

- First Copy

- Based on the Rambus Datasheet 0.9ver

Version 1.2( March 2002) - Preliminary

- Add 1066MHz -32 binning

- Modify VIN from 260mV swing to 300mV

Version 1.3( April 2002) - Preliminary

- Modify Timing Characteristics ( tQR1,tQF1,tPROP1)

- Add Minimum operation temperature at Absolute Maximum Ratings table

Version 1.4( July 2002) - Preliminary

- Combine 800MHz and 1066MHz

- Modify Timing Parameters(tRDP, tRTP)

Direct RDRAM™

K4R571669A/K4R881869A

Page 1 Version 1.4 July 2002

Overview

The Rambus Direct RDRAM™ is a general purpose high-

performance memory device suitable for use in a broad

range of applications including computer memory, graphics,

video, and any other application where high bandwidth and

low latency are required.

The 256/288-Mbit Direct Rambus DRAMs (RDRAM) are

extremely high-speed CMOS DRAMs organized as 16M

words by 16 or 18 bits. The use of Rambus Signaling Level

(RSL) technology permits up to 1066 MHz transfer rates

while using conventional system and board design technolo-

gies. Direct RDRAM devices are capable of sustained data

transfers up to at 0.938ns per two bytes (7.5ns per sixteen

bytes).

The architecture of the Direct RDRAMs allows the highest

sustained bandwidth for multiple, simultaneous randomly

addressed memory transactions. The separate control and

data buses with independent row and column control yield

over 95% bus efficiency. The Direct RDRAM's 32 banks

support up to four simultaneous transactions.

System oriented features for mobile, graphics and large

memory systems include power management, byte masking,

and x18 organization. The two data bits in the x18 organiza-

tion are general and can be used for additional storage and

bandwidth or for error correction.

Features

♦Highest sustained bandwidth per DRAM device

- 2.1GB/s sustained data transfer rate

- Separate control and data buses for maximized

efficiency

- Separate row and column control buses for

easy scheduling and highest performance

- 32 banks: four transactions can take place simul-

taneously at full bandwidth data rates

♦Low latency features

- Write buffer to reduce read latency

- 3 precharge mechanisms for controller flexibility

- Interleaved transactions

♦Advanced power management:

- Multiple low power states allows flexibility in power

consumption versus time to transition to active state

- Power-down self-refresh

♦Organization: 2kbyte pages and 32 banks, x 16/18

- x18 organization allows ECC configurations or

increased storage/bandwidth

- x16 organization for low cost applications

♦Interleaved Device Mode(IDM) for enhanced system reli-

ability

♦Uses Rambus Signaling Level (RSL) for up to 1066MHz

operation

The 256/288-Mbit Direct RDRAMs are offered in a CSP

horizontal package suitable for desktop as well as low-

profile add-in card and mobile applications.

Key Timing Parameters/Part Numbers

a.“32s” - 32 banks which use a “split” bank architecture.

b.“F” - WBGA package.

c.“C” - RDRAM core uses normal power self refresh.

Figure 1: Direct RDRAM CSP Package

Organization

Speed

Part Number

Bin I/O

Freq.

MHz

tRAC

(Row

Access

Time) ns

512Kx16x32sa-CM8 800 40 K4R571669A-FbCcM8

-CK8 800 45 K4R571669A-FCK8

512Kx18x32s

-CT9 1066 32P K4R881869A-FCT9

-CN9 1066 32 K4R881869A-FCN9

-CM9 1066 35 K4R881869A-FCM9

-CM8 800 40 K4R881869A-FCM8

-CK8 800 45 K4R881869A-FCK8

K4RXXXX69A-Fxxx

SAMSUNG 230

Direct RDRAM™

K4R571669A/K4R881869A

Page 2 Version 1.4 July 2002

COL

ROW

Pinouts and Definitions

Center-Bonded Devices

These tables shows the pin assignments of the center-bonded

RDRAM package. The mechanical dimensions of this

package are shown in a later section. Refer to Section

“Center-Bonded WBGA Package” on page 18. Note - pin #1

is at the A1 position.

Table 1: Center-Bonded Device (top view)

10 VDD GND VDD GND VDD VDD VDD VDD GND VDD

8GND VDD CMD VDD GND GNDa GNDa VDD VDD GND GND VDD VDD GND GND VCMOS VDD GND

7VDD DQA8 DQA7 DQA5 DQA3 DQA1 CTMN CTM RQ7 RQ5 RQ3 RQ1 DQB1 DQB3 DQB5 DQB7 DQB8 VDD

4GND GND DQA6 DQA4 DQA2 DQA0 CFM CFMN RQ6 RQ4 RQ2 RQ0 DQB0 DQB2 DQB4 DQB6 GND GND

3VDD GND SCK VCMOS GND VDD GND VDDa VREF GND VDD GND GND VDD SIO0 SIO1 GND VDD

1VDD GND GND VDD GND GND GND GND GND VDD

ABC D EFG H JKLMNPRSTU

Chip

Top View

The pin #1(ROW 1, COL A) is located at the

A1 position on the top side and the A1 position

is marked by the marker “ ”.

K4RXXXX69A-Fxxx

SAMSUNG 230

Direct RDRAM™

K4R571669A/K4R881869A

Page 3 Version 1.4 July 2002

Table 2: Pin Description

Signal I/O Type # Pins

center Description

SIO1,SIO0 I/O CMOSa2Serial input/output. Pins for reading from and writing to the control regis-

ters using a serial access protocol. Also used for power management.

CMD ICMOSa1Command input. Pins used in conjunction with SIO0 and SIO1 for reading

from and writing to the control registers. Also used for power manage-

ment.

SCK ICMOSa1Serial clock input. Clock source used for reading from and writing to the

control registers

VDD 24 Supply voltage for the RDRAM core and interface logic.

VDDa 1Supply voltage for the RDRAM analog circuitry.

VCMOS 2Supply voltage for CMOS input/output pins.

GND 28 Ground reference for RDRAM core and interface.

GNDa 2Ground reference for RDRAM analog circuitry.

DQA8..DQA0 I/O RSLb9Data byte A. Nine pins which carry a byte of read or write data between

the Channel and the RDRAM. DQA8 is not used (no connection) by

RDRAMs with a x16 organization.

CFM IRSLb1Clock from master. Interface clock used for receiving RSL signals from

the Channel. Positive polarity.

CFMN IRSLb1Clock from master. Interface clock used for receiving RSL signals from

the Channel. Negative polarity

VREF 1Logic threshold reference voltage for RSL signals

CTMN IRSLb1Clock to master. Interface clock used for transmitting RSL signals to the

Channel. Negative polarity.

CTM IRSLb1Clock to master. Interface clock used for transmitting RSL signals to the

Channel. Positive polarity.

RQ7..RQ5 or

ROW2..ROW0 IRSLb3Row access control. Three pins containing control and address informa-

tion for row accesses.

RQ4..RQ0 or

COL4..COL0 IRSLb5Column access control. Five pins containing control and address informa-

tion for column accesses.

DQB8..

DQB0 I/O RSLb9Data byte B. Nine pins which carry a byte of read or write data between

the Channel and the RDRAM. DQB8 is not used (no connection) by

RDRAMs with a x16 organization.

Total pin count per package 92

a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.

b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

Direct RDRAM™

K4R571669A/K4R881869A

Page 4 Version 1.4 July 2002

Figure 2: 256/288-Mbit (512Kx16/18x32s) Direct RDRAM Block Diagram

Bank 31

DQA8..DQA0

1:8 Demux8:1 Mux

Write Buffer

1:8 Demux

Write Buffer

8:1 Mux

Bank 30

Bank 29

Bank 18

Bank 17

Bank 16

Bank 15

Bank 14

Bank 13

Bank 1

Bank 0

SAmp

1/2

DQB8..DQB0

1:8 Demux 1:8 Demux

Packet Decode

ROW2..ROW0 COL4..COL0CTM CTMN CFM CFMN

SCK,CMD

RCLKTCLK

Control Registers

DCCOP CBC MAMBDXXOP BXDR RROP BR

887555556

95511

AV MS

Write

Buffer

MatchMatch

Mux

Match

DEVID

512x128x144

Internal DQB Data Path

Column Decode & Mask

REFR

Row Decode

Mux

ACT

RD, WR

Power Modes

DRAM Core

Mux

XOP Decode

PREX

PREC

9 99

9 9

PRER

COLX COLC COLM

SIO0,SIO1

Sense Amp

Internal DQA Data Path

Packet Decode

ROWA ROWR

RCLK RCLK

RCLKTCLK

RQ7..RQ5 or

RQ4..RQ0 or

SAmp

0/1

SAmp

0SAmp

14/15 SAmp

SAmp

13/14 SAmp

16/17 SAmp

17/18

SAmp

16 SAmp

29/30 SAmp

30/31 SAmp

64x72

SAmp

1/2

SAmp

0/1SAmp

SAmp

14/15

SAmp

15 SAmp

13/14

SAmp

16/17

SAmp

17/18 SAmp

SAmp

29/30

SAmp

30/31

SAmp

64x72

Bank 2

•••

Direct RDRAM™

K4R571669A/K4R881869A

Page 5 Version 1.4 July 2002

General Description

Figure2 is a block diagram of the 256/288-Mbit Direct

RDRAM. It consists of two major blocks: a “core” block

built from banks and sense amps similar to those found in

other types of DRAM, and a Direct Rambus interface block

which permits an external controller to access this core at up

to 2.1GB/s.

Control Registers: The CMD, SCK, SIO0, and SIO1

pins appear in the upper center of Figure2. They are used to

write and read a block of control registers. These registers

supply the RDRAM configuration information to a

controller and they select the operating modes of the device.

The REFR value is used for tracking the last refreshed row.

Most importantly, the five bit DEVID specifies the device

address of the RDRAM on the Channel.

Clocking: The CTM and CTMN pins (Clock-To-Master)

generate TCLK (Transmit Clock), the internal clock used to

transmit read data. The CFM and CFMN pins (Clock-From-

Master) generate RCLK (Receive Clock), the internal clock

signal used to receive write data and to receive the ROW and

COL pins.

DQA,DQB Pins: These 16/18 pins carry read (Q) and

write (D) data across the Channel. They are multiplexed/de-

multiplexed from/to two 64/72-bit data paths (running at

one-eighth the data frequency) inside the RDRAM.

Banks: The 32Mbyte core of the RDRAM is divided into

thirty two 1Mbyte banks, each organized as 512 rows, with

each row containing 128 dualocts, and each dualoct

containing 16/18 bytes. A dualoct is the smallest unit of data

that can be addressed.

Sense Amps: The RDRAM contains 34 sense amps. Each

sense amp consists of 1kbyte of fast storage (512 bytes for

DQA and 512 bytes for DQB) and can hold one-half of one

row of one bank of the RDRAM. The sense amp may hold

any of the 1024 half-rows of an associated bank. However,

each sense amp is shared between two adjacent banks of the

RDRAM (except for sense amps 0, 15, 16, and 31). This

introduces the restriction that adjacent banks may not be

simultaneously accessed.

RQ Pins: These pins carry control and address informa-

tion. They are broken into two groups. RQ7..RQ5 are also

called ROW2..ROW0, and are used primarily for controlling

row accesses. RQ4..RQ0 are also called COL4..COL0, and

are used primarily for controlling column accesses.

ROW Pins: The principle use of these three pins is to

manage the transfer of data between the banks and the sense

amps of the RDRAM. These pins are de-multiplexed into a

24-bit ROWA (row-activate) or ROWR (row-operation)

packet.

COL Pins: The principle use of these five pins is to

manage the transfer of data between the DQA/DQB pins and

the sense amps of the RDRAM. These pins are de-multi-

plexed into a 23-bit COLC (column-operation) packet and

either a 17-bit COLM (mask) packet or a 17-bit COLX

(extended-operation) packet.

ACT Command: An ACT (activate) command from an

ROWA packet causes one of the 512 rows of the selected

bank to be loaded to its associated sense amps (two 512

bytes sense amps for DQA and two for DQB).

PRER Command: A PRER (precharge) command from

an ROWR packet causes the selected bank to release its two

associated sense amps, permitting a different row in that

bank to be activated, or permitting adjacent banks to be acti-

vated.

RD Command: The RD (read) command causes one of

the 128 dualocts of one of the sense amps to be transmitted

on the DQA/DQB pins of the Channel.

WR Command: The WR (write) command causes a

dualoct received from the DQA/DQB data pins of the

Channel to be loaded into the write buffer. There is also

space in the write buffer for the BC bank address and C

column address information. The data in the write buffer is

automatically retired (written with optional bytemask) to one

of the 128 dualocts of one of the sense amps during a subse-

quent COP command. A retire can take place during a RD,

WR, or NOCOP to another device, or during a WR or

NOCOP to the same device. The write buffer will not retire

during a RD to the same device. The write buffer reduces the

delay needed for the internal DQA/DQB data path turn-

around.

PREC Precharge: The PREC, RDA and WRA

commands are similar to NOCOP, RD and WR, except that a

precharge operation is performed at the end of the column

operation. These commands provide a second mechanism

for performing precharge.

PREX Precharge: After a RD command, or after a WR

command with no byte masking (M=0), a COLX packet may

be used to specify an extended operation (XOP). The most

important XOP command is PREX. This command provides

a third mechanism for performing precharge.

Direct RDRAM™

K4R571669A/K4R881869A

Page 6 Version 1.4 July 2002

Packet Format

Figure3 shows the formats of the ROWA and ROWR

packets on the ROW pins. Table3 describes the fields which

comprise these packets. DR4T and DR4F bits are encoded to

contain both the DR4 device address bit and a framing bit

which allows the ROWA or ROWR packet to be recognized

by the RDRAM.

The AV (ROWA/ROWR packet selection) bit distinguishes

between the two packet types. Both the ROWA and ROWR

packet provide a five bit device address and a five bit bank

address. An ROWA packet uses the remaining bits to

specify a nine bit row address, and the ROWR packet uses

the remaining bits for an eleven bit opcode field. Note the

use of the “RsvX” notation to reserve bits for future address

field extension.

Figure3 also shows the formats of the COLC, COLM, and

COLX packets on the COL pins. Table4 describes the fields

which comprise these packets.

The COLC packet uses the S (Start) bit for framing. A

COLM or COLX packet is aligned with this COLC packet,

and is also framed by the S bit.

The 23 bit COLC packet has a five bit device address, a five

bit bank address, a seven bit column address, and a four bit

opcode. The COLC packet specifies a read or write

command, as well as some power management commands.

The remaining 17 bits are interpreted as a COLM (M=1) or

COLX (M=0) packet. A COLM packet is used for a COLC

write command which needs bytemask control. The COLM

packet is associated with the COLC packet from at least

tRTR earlier. A COLX packet may be used to specify an

independent precharge command. It contains a five bit

device address, a five bit bank address, and a five bit opcode.

The COLX packet may also be used to specify some house-

keeping and power management commands. The COLX

packet is framed within a COLC packet but is not otherwise

associated with any other packet.

Table 3: Field Description for ROWA Packet and ROWR Packet

Field Description

DR4T,DR4F Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.

DR3..DR0 Device address for ROWA or ROWR packet.

BR4..BR0 Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.

AV Selects between ROWA packet (AV=1) and ROWR packet (AV=0).

R8..R0 Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.

ROP10..ROP0 Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.

Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet

Field Description

SBit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.

DC4..DC0 Device address for COLC packet.

BC4..BC0 Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0 ’ s).

C6..C0 Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.

COP3..COP0 Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.

MSelects between COLM packet (M=1) and COLX packet (M=0).

MA7..MA0 Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.

MB7..MB0 Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.

DX4..DX0 Device address for COLX packet.

BX4..BX0 Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’ s).

XOP4..XOP0 Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.

Direct RDRAM™

K4R571669A/K4R881869A

Page 7 Version 1.4 July 2002

Figure 3: Packet Formats

CTM/CFM

COL4

COL3

COL2

COL1

COL0

T8T9T10 T11 T12 T13 T14 T15

T8T9T10 T11

T0T1T2T3

S=1aMA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

CTM/CFM

ROW2 DR4T DR2 BR0 BR3 RsvR R8 R5

ROW1 DR4F DR1 BR1 BR4 RsvR R7 R4 R1

ROW0 DR3 DR0 BR2 RsvB AV=1 R6 R3 R0

ACT a0

PREX d0MSK (b1)

PRER c0

WR b1

CTM/CFM

COL4 DC4 S=1 C6

COL3 DC3 C5 C3

COL2 DC2 COP1 RsvB BC2 C2

DC1 COP0 BC4 BC1 C1

DC0 COP2 COP3 BC3 BC0 C0

COL1

COL0

CTM/CFM

ROW2

ROW1

ROW0

CTM/CFM

COL4

COL3

COL2

COL1

COL0

ROP2DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5

DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1

DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0

S=1bDX4 XOP4 RsvB BX1

M=0 DX3 XOP3 BX4 BX0

DX2 XOP2 BX3

DX1 XOP1 BX2

DX0 XOP0

T0T4T8T12

T1T5T9T13

T2T6T10 T14

T3T7T11 T15

ROWA Packet

COLM Packet

COLC Packet

COLX Packet

ROWR Packet

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0 tPACKET

a The COLM is associated with a

previous COLC, and is aligned

with the present COLC, indicated

by the Start bit (S=1) position.

b The COLX is aligned

with the present COLC,

indicated by the Start

bit (S=1) position.

Direct RDRAM™

K4R571669A/K4R881869A

Page 8 Version 1.4 July 2002

Field Encoding Summary

Table5 shows how the six device address bits are decoded

for the ROWA and ROWR packets. The DR4T and DR4F

encoding merges a fifth device bit with a framing bit. When

neither bit is asserted, the device is not selected. Note that a

broadcast operation is indicated when both bits are set.

Broadcast operation would typically be used for refresh and

power management commands. If the device is selected, the

DM (DeviceMatch) signal is asserted and an ACT or ROP

command is performed.

Table6 shows the encodings of the remaining fields of the

ROWA and ROWR packets. An ROWA packet is specified

by asserting the AV bit. This causes the specified row of the

specified bank of this device to be loaded into the associated

sense amps.

An ROWR packet is specified when AV is not asserted. An

11 bit opcode field encodes a command for one of the banks

of this device. The PRER command causes a bank and its

two associated sense amps to precharge, so another row or

an adjacent bank may be activated. The REFA (refresh-acti-

vate) command is similar to the ACT command, except the

row address comes from an internal register REFR, and

REFR is incremented at the largest bank address. The REFP

(refresh-precharge) command is identical to a PRER

command.

The NAPR, NAPRC, PDNR, ATTN, and RLXR commands

are used for managing the power dissipation of the RDRAM

and are described in more detail in “Power State Manage-

ment” on page49. The TCEN and TCAL commands are

used to adjust the output driver slew rate and they are

described in more detail in “Current and Temperature

Control” on page55.

Table 5: Device Field Encodings for ROWA Packet and ROWR Packet

DR4T DR4F Device Selection Device Match signal (DM)

1 1 All devices (broadcast) DM is set to 1

0 1 One device selected DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0

1 0 One device selected DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0

0 0 No packet present DM is set to 0

Table 6: ROWA Packet and ROWR Packet Field Encodings

DM aAV ROP10..ROP0 Field Name Command Description

10 98765432:0

0- ------------ No operation.

1 1 Row address ACT Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb.

1 0 11000xcxx000 PRER Precharge bank BR4..BR0 of this device.

1 0 0001100x000 REFA Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.

Increment REFR if BR4..BR0 = 11111 (see Figure52).

1 0 1010100x000 REFP Precharge bank BR4..BR0 of this device after REFA (see Figure52).

1 0 xx00001x000 PDNR Move this device into the powerdown (PDN) power state (see Figure49).

1 0 xx00010x000 NAPR Move this device into the nap (NAP) power state (see Figure49).

1 0 xx00011x000 NAPRC Move this device into the nap (NAP) power state conditionally

1 0 xxxxxxx0000 ATTNbMove this device into the attention (ATTN) power state (see Figure47).

1 0 xxxxxxx1000 RLXR Move this device into the standby (STBY) power state (see Figure48).

1 0 0000000x001 TCAL Temperature calibrate this device (see Figure55).

1 0 0000000x010 TCEN Temperature calibrate/enable this device (see Figure55).

1 0 00000000000 NOROP No operation.

a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table5.

b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).

c. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).

Direct RDRAM™

K4R571669A/K4R881869A

Page 9 Version 1.4 July 2002

Table7 shows the COP field encoding. The device must be

in the ATTN power state in order to receive COLC packets.

The COLC packet is used primarily to specify RD (read) and

WR (write) commands. Retire operations (moving data from

the write buffer to a sense amp) happen automatically. See

Figure18 for a more detailed description.

The COLC packet can also specify a PREC command,

which precharges a bank and its associated sense amps. The

RDA/WRA commands are equivalent to combining RD/WR

with a PREC. RLXC (relax) performs a power mode transi-

tion. See “Power State Management” on page49.

Table8 shows the COLM and COLX field encodings. The

M bit is asserted to specify a COLM packet with two 8 bit

bytemask fields MA and MB. If the M bit is not asserted, an

COLX is specified. It has device and bank address fields,

and an opcode field. The primary use of the COLX packet is

to permit an independent PREX (precharge) command to be

specified without consuming control bandwidth on the ROW

pins. It is also used for the CAL(calibrate) and SAM (sam-

ple) current control commands (see “Current and Tempera-

ture Control” on page55), and for the RLXX power mode

command (see “Power State Management” on page49).

Table 7: COLC Packet Field Encodings

SDC4.. DC0

(select device)aCOP3..0 Name Command Description

0---- ----- -No operation.

1/= (DEVID4 ..0) ----- -Retire write buffer of this device.

1== (DEVID4 ..0) x000bNOCOP Retire write buffer of this device.

1== (DEVID4 ..0) x001 WR Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer.

1== (DEVID4 ..0) x010 RSRV Reserved, no operation.

1== (DEVID4 ..0) x011 RD Read column C6..C0 of bank BC4..BC0 of this device.

1== (DEVID4 ..0) x100 PREC Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure15).

1== (DEVID4 ..0) x101 WRA Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.

1== (DEVID4 ..0) x110 RSRV Reserved, no operation.

1== (DEVID4 ..0) x111 RDA Same as RD, but precharge bank BC4..BC0 afterward.

1== (DEVID4 ..0) 1xxx RLXC Move this device into the standby (STBY) power state (see Figur e48).

a. “/=” means not equal, “==” means equal.

b. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).

Table 8: COLM Packet and COLX Packet Field Encodings

MDX4 .. DX0

(selects device) XOP4..0 Name Command Description

1---- - MSK MB/MA bytemasks used by WR/WRA.

0/= (DEVID4 ..0) - - No operation.

0== (DEVID4 ..0) 00000 NOXOP No operation.

0== (DEVID4 ..0) 1xxx0aPREX Precharge bank BX3..BX0 of this device (see Figure15).

0== (DEVID4 ..0) x10x0 CAL Calibrate (drive) IOL current for this device (see Figure54).

0== (DEVID4 ..0) x11x0 CAL/SAM Calibrate (drive) and Sample ( update) IOL current for this device (see Figure54).

0== (DEVID4 ..0) xxx10 RLXX Move this device into the standby (STBY) power state (see Figur e48).

0== (DEVID4 ..0) xxxx1 RSRV Reserved, no operation.

a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).

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K4R571669A/K4R881869A

Page 10 Version 1.4 July 2002

Electrical Conditions

Table 9: Electrical Conditions

Symbol Parameter and Conditions Min Max Unit

TJJunction temperature under bias -100 °C

VDD, VDDA Supply voltage 2.50 - 0.13 2.50 + 0.13 V

VDD,N, VDDA,N Supply voltage droop (DC) during NAP interval (t

NLIMIT) - 2.0 %

vDD,N, vDDA,N Supply voltage ripple (AC) during NAP interval (t

NLIMIT)-2.0 2.0 %

VCMOSaSupply voltage for CMOS pins (2.5V controllers)

Supply voltage for CMOS pins (1.8V controllers) VDD

1.80 - 0.1 VDD

1.80 + 0.2 V

VREF Reference voltage 1.40 - 0.2 1.40 + 0.2 V

VDIL

RSL data input - low voltage @ tCYCLE=1.875ns VREF - 0.5 VREF - 0.15 V

RSL data input - low voltage @ tCYCLE=2.50ns VREF - 0.5 VREF - 0.2

VDIH

RSL data input - high voltageb @ tCYCLE=1.875ns VREF + 0.15 VREF + 0.5 V

RSL data input - high voltageb @ tCYCLE=2.50ns VREF + 0.2 VREF + 0.5

RDA RSL data asymmetry : RDA = (VDIH - VREF) / (VREF - VDIL)0.67 1.00 -

VCM RSL clock input - common mode VCM = (VCIH+VCIL)/2 1.3 1.8 V

VCIS,CTM RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins). 0.35 1.00 V

VCIS,CFM RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins). 0.225 1.00 V

VIL,CMOS CMOS input low voltage - 0.3cVCMOS/2 - 0.25 V

VIH,CMOS CMOS input high voltage VCMOS/2 + 0.25 VCMOS+0.3dV

a. VCMOS must remain on as long as VDD is applied and cannot be turned off.

b. VDIH is typically equal to VTERM (1.8V±0.1V) under DC conditions in a system.

c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.

d. Voltage overshoot is limited toVCMOS +0.7V for a duration of less than 5ns

Direct RDRAM™

K4R571669A/K4R881869A

Page 11 Version 1.4 July 2002

Electrical Characteristics

Table 10: Electrical Characteristics

Symbol Parameter and Conditions Min Max Unit

ΘJC Junction-to-Case thermal resistance -0.5 °C/Watt

IREF VREF current @ VREF,MAX -10 10 µA

IOH RSL output high current @ (0≤VOUT≤VDD)-10 10 µA

IALL

RSL IOL current @ tCYCLE= 1.875ns VOL = 0.9V, VDD,MIN , TJ,MAXa32.0 90.0 mA

RSL IOL current @ tCYCLE= 2.50ns VOL = 0.9V, VDD,MIN , TJ,MAXa

a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.

30.0 90.0

∆IOL RSL IOL current resolution step -1.5 mA

rOUT Dynamic output impedance @ VOL= 0.9V 150 -Ω

IOL,NOM

RSL IOL current @ VOL = 1.0V b,c@ tCYCLE=1.875ns

b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and

CCB are initialized to a value of 64. This value applies to all DQA and DQB pins.

c. This measurement is made in automatic current control mode in a 25Ω test system with VTERM= 1.714V and VREF= 1.357V and with the ASYMA

and ASYMB register fields set to 0.

27.1 30.1 mA

RSL IOL current @ VOL = 1.0Vb,c @ tCYCLE=2.50ns 26.6 30.6

II,CMOS CMOS input leakage current @ (0≤VI,CMOS≤VCMOS)-10.0 10.0 µA

VOL,CMOS CMOS output voltage @ IOL,CMOS= 1.0mA -0.3 V

VOH,CMOS CMOS output high voltage @ IOH,CMOS= -0.25mA VCMOS-0.3 -V

Direct RDRAM™

K4R571669A/K4R881869A

Page 12 Version 1.4 July 2002

Timing Conditions

Table 11: Timing Conditions

Symbol Parameter Min Max Unit Figure(s)

tCYCLE

CTM and CFM cycle times (-1066) 1.875 2.5 ns Figure56

CTM and CFM cycle times (-800) 2.50 3.33

tCR, tCF CTM and CFM input rise and fall times. Use the minimum value of

these parameters during testing. 0.2 0.5 ns Figure56

tCH, tCL CTM and CFM high and low times 40% 60% tCYCLE Figure56

tTR

CTM-CFM differential (MSE/MS=0/0)

CTM-CFM differential (MSE/MS=1/1)a

CTM-CFM differential (MSE/MS=1/0)

(only for tCYCLE = 1.875us)

0.0

0.9

-0.1

1.0

0.1 tCYCLE Figure43

Figure56

tDCW Domain crossing window -0.1 0.1 tCYCLE Figure62

tDR, tDF DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the

minimum value of these parameters during testing. 0.2 0.45 ns Figure57

tS, tH

DQA/DQB/ROW/COL-to-CFM set/hold @ t CYCLE=1.875ns 0.160b-ns Figure57

DQA/DQB/ROW/COL-to-CFM set/hold @ t CYCLE=2.50ns 0.200b.c-

tDR1, tDF1 SIO0, SIO1 input rise and fall times -5.0 ns Figure59

tDR2, tDF2 CMD, SCK input rise and fall times -2.0 ns Figure59

tCYCLE1

SCK cycle time - Serial control register transactions 1000 -

ns Figure59SCK cycle time - Power transitions @ t CYCLE=1.875ns 7.5 -

SCK cycle time - Power transitions @ t CYCLE=2.50ns 10 -

tCH1, tCL1

SCK high and low times @ t CYCLE=1.875ns 3.5 -ns Figure59

SCK high and low times @ t CYCLE=2.50ns 4.25 -

tS1

CMD setup time to SCK rising or falling edged @ t CYCLE=1.875ns 1.0 -ns Figure59

CMD setup time to SCK rising or falling edge d @ t CYCLE=2.50ns 1.25 -

tH1 CMD hold time to SCK rising or falling edged 1-ns Figure59

tS2 SIO0 setup time to SCK falling edge 40 -ns Figure59

tH2 SIO0 hold time to SCK falling edge 40 -ns Figure59

tS3 PDEV setup time on DQA5..0 to SCK rising edge. 0-ns Figure50

tH3 PDEV hold time on DQA5..0 to SCK rising edge. 5.5 -ns Figure60

tS4 ROW2..0, COL4..0 setup time for quiet window -1 -tCYCLE Figure50

tH4 ROW2..0, COL4..0 hold time for quiet windowe5-tCYCLE Figure50

tNPQ Quiet on ROW/COL bits during NAP/PDN entry 4-tCYCLE Figure 49

tREADTOCC Offset between read data and CC packets (same device) 12 -tCYCLE Figure54

tCCSAMTOREAD Offset between CC packet and read data (same device) 8-tCYCLE Figure54

tCE CTM/CFM stable before NAP/PDN exit 2-tCYCLE Figure50

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K4R571669A/K4R881869A

Page 13 Version 1.4 July 2002

tCD CTM/CFM stable after NAP/PDN entry 100 -tCYCLE Figure49

tFRM ROW packet to COL packet ATTN framing delay 7-tCYCLE Figure48

tNLIMIT Maximum time in NAP mode 10.0 µsFigure47

tREF Refresh interval 32 ms Figure52

tBURST Interval after PDN or NAP (with self-refresh) exit in which all

banks of the RDRAM must be refreshed at least once. 200 µsFigure53

tCCTRL Current control interval 34 tCYCLE 100ms ms/tCYCLE Figure54

tTEMP Temperature control interval 100 ms Figure55

tTCEN TCE command to TCAL command 150 -tCYCLE Figure55

tTCAL TCAL command to quiet window 2 2 tCYCLE Figure55

tTCQUIET Quiet window (no read data) 140 -tCYCLE Figure55

tPAUSE RDRAM delay (no RSL operations allowed) 200.0 µspage 37

a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.

b. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 2 specified t CYCLE values.

c. This parameter also applies to a-1066 part when operated with tCYCLE = 2.50ns

d. With VIL,CMOS=0.5VCMOS-0.4V and VIH,CMOS=0.5VCMOS+0.4V

e. Effective hold becomes tH4’=tH4+[PDNXA•64•tSCYCLE+tPDNXB,MAX]-[PDNX•256•tSCYCLE]

if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE+tPDNXB,MAX]. See Figure49.

Table 11: Timing Conditions

Symbol Parameter Min Max Unit Figure(s)

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Page 14 Version 1.4 July 2002

Timing Characteristics

Table 12: Timing Characteristics

Symbol Parameter Min Max Unit Figure(s)

CTM-to-DQA/DQB output time @ tCYCLE=1.875ns -0.195a

a. tQ,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values.

b.This parameter also applies to a-1066 part when operated with tCYCLE = 2.50ns

+0.195a

ns Figure58

CTM-to-DQA/DQB output time @ tCYCLE=2.5ns -0.260a,b +0.260a,b

tQR, tQF

DQA/DQB output rise and fall times @ tCYCLE=1.875ns 0.2 0.32 ns Figure58

DQA/DQB output rise and fall times @ tCYCLE=2.5ns 0.2 0.45

tQ1 SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data valid). -10 ns Figure61

tHR SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold). 2-ns Figure61

tQR1, tQF1 SIOOUT rise/fall @ CLOAD,MAX = 20pF -12 ns Figure61

tPROP1 SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF -20 ns Figure61

tNAPXA NAP exit delay - phase A -50 ns Figure50

tNAPXB NAP exit delay - phase B -40 ns Figure50

tPDNXA PDN exit delay - phase A -4µsFigure50

tPDNXB PDN exit delay - phase B -9000 tCYCLE Figure50

tAS ATTN-to-STBY power state delay -1tCYCLE Figure48

tSA STBY-to-ATTN power state delay -0tCYCLE Figure48

tASN ATTN/STBY-to-NAP power state delay -8tCYCLE Figure49

tASP ATTN/STBY-to-PDN power state delay -8tCYCLE Figure49

Direct RDRAM™

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Page 15 Version 1.4 July 2002

Timing Parameters

Table 13: Timing Parameter Summary

Parameter Description Min

-32P

-1066

Min

-32

-1066

Min

-35

-1066

Min

-40

-800

Min

-45

-800 Max Units Figure(s)

tRC Row Cycle time of RDRAM banks -the interval between ROWA

packets with ACT commands to the same bank. 28 28 32 28 28 -tCYCLE Figure16

Figure17

tRAS

RAS-asserted time of RDRAM bank - the interval between ROWA

packet with ACT command and next ROWR packet with PRERa

command to the same bank. 20 20 22 20 20 64µsbtCYCLE Figure16

Figure17

tRP

Row Precharge time of RDRAM banks - the interval between

ROWR packet with PRERa command and next ROWA packet with

ACT command to the same bank. 8 8 10 8 8 -tCYCLE Figure16

Figure17

tPP

Precharge-to-precharge time of RDRAM device - the interval

between successive ROWR packets with PRERa commands to any

banks of the same device. 8 8 8 8 8 -tCYCLE Figure13

tRR

RAS-to-RAS time of RDRAM device - the interval between succes-

sive ROWA packets with ACT commands to any banks of the same

device. 8 8 8 8 8 -tCYCLE Figure14

tRCD

RAS-to-CAS Delay - the interval from ROWA packet with ACT

command to COLC packet with RD or WR command). Note - the

RAS-to-CAS delay seen by the RDRAM core (tRCD-C) is equal to

tRCD-C = 1 + tRCD because of differences in the row and column

paths through the RDRAM interface.

9 9 9 7 9 -tCYCLE Figure16

Figure17

tCAC CAS Access delay - the interval from RD command to Q read data.

The equation for tCAC is given in the TPARM register in Figure40. 8 9 9 8 8 12 tCYCLE Figure5

Figure40

tCWD CAS Write Delay (interval from WR command to D write data. 6 6 6 6 6 6 tCYCLE Figure5

tCC CAS-to-CAS time of RDRAM bank - the interval between succes-

sive COLC commands). 4 4 4 4 4 -tCYCLE Figure16

Figure17

tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. 4 4 4 4 4 4 tCYCLE Figure3

tRTR Interval from COLC packet with WR command to COLC packet

which causes retire, and to COLM packet with bytemask. 8 8 8 8 8 -tCYCLE Figure18

tOFFP

The interval (offset) from COLC packet with RDA command, or

from COLC packet with retire command (after WRA automatic pre-

charge), or from COLC packet with PREC command, or from

COLX packet with PREX command to the equivalent ROWR packet

with PRER. The equation for tOFFP is given in the TPARM register

in Figure40.

4 4 4 4 4 4 tCYCLE Figure15

Figure40

tRDP Interval from last COLC packet with RD command to ROWR

packet with PRER. 4 4 4 4 4 -tCYCLE Figure16

tRTP Interval from last COLC packet with automatic retire command to

ROWR packet with PRER. 4 4 4 4 4 -tCYCLE Figure17

a. Or equivalent PREC or PREX command. See Figure15.

b. This is a constraint imposed by the core, and is therefore in units of µs rather than tCYCLE.

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K4R571669A/K4R881869A

Page 16 Version 1.4 July 2002

Absolute Maximum Ratings

Note*)Component : refer to TJ,ΘJC RIMM: refre to TPLATE, MAX

IDD - Supply Current Profile

Table 14: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VI,ABS Voltage applied to any RSL or CMOS pin with respect to Gnd - 0.3 VDD+0.3 V

VDD,ABS, VDDA,ABS Voltage on VDD and VDDA with respect to Gnd - 0.5 VDD+1.0 V

TSTORE Storage temperature - 50 100 °C

TMIN Minimum operation temperature 0Note* °C

Table 15: Supply Current Profile

IDD value RDRAM Power State and Steady-State Transaction RatesaMin Max

(1066MHz, -

32P/-32/-35)

Max

(800MHz,

-40/-45) Unit

IDD,PDN Device in PDN, self-refresh enabled and INIT.LSR=0. -6000 6000 µA

IDD,NAP Device in NAP. -4 4 mA

IDD,STBY Device in STBY. This is the average for a device in STBY with (1) no

packets on the Channel, and (2) with packets sent to other devices. -135 80 mA

IDD,REFRESH Device in STBY and refreshing rows at the tREF,MAX period. -135 80 mA

IDD,ATTN Device in ATTN. This is the average for a device in ATTN with (1) no

packets on the Channel, and (2) with packets sent to other devices. -215 120 mA

IDD,ATTN-W Device in ATTN. ACT command every 8•t CYCLE, PRE command every

8•t CYCLE, WR command every 4•tCYCLE, and data is 1100..1100 -884(x18) 680(x18)

620(x16) mA

IDD,ATTN-R Device in ATTN. ACT command every 8•t CYCLE, PRE command every

8•tCYCLE, RD command every 4•tCYCLE, and data is 1111..1111b-793(x18) 610(x18)

560(x16) mA

a. CMOS interface consumes power in all power states.

b. x18/x16 RDRAM data width.

c. This does not include the IOL sink current. The RDRAM dissipates IOL•VOL in each output driver when a logic one is driven.

Table 16: Supply Current at Initialization

Symbol Parameter Allowed Range of tCYCLE VDD Min Max Unit

IDD,PWRUP,D IDD from power -on to SETR 1.875ns to 2.5ns VDD,MIN -200amA

IDD,SETR,D IDD from SETR to CLRR 1.875ns to 2.5ns VDD,MIN -332 mA

a. The supply current will be 150mA when tCYCLE is in the range 15ns to 1000ns.

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K4R571669A/K4R881869A

Page 17 Version 1.4 July 2002

Capacitance and Inductance

Table 17: RSL Pin Parasitics

Symbol Parameter and Conditions - RSL pins Min Max Unit Figure

RSL effective input inductance @ tCYCLE=1.875ns -3.5 nH Figure 63

RSL effective input inductance @ tCYCLE=2.5ns -4.0

L12

Mutual inductance between any DQA or DQB RSL signals. -0.2 nH Figure 63

Mutual inductance between any ROW or COL RSL signals. -0.6 nH

∆LI Difference in LI value between any RSL pins of a single device. -1.8 nH Figure 63

RSL effective input capacitancea @ tCYCLE=1.875ns 2.0 2.3 pF Figure 63

RSL effective input capacitancea @ tCYCLE=2.5ns 2.0 2.4

C12 Mutual capacitance between any RSL signals. -0.1 pF Figure 63

∆CI Difference in C I value between average of {CTM, CTMN,

CFM, CFMN} and any RSL pins of a single device. -0.06 pF Figure 63

RSL effective input resistance @ tCYCLE=1.875ns 410 ΩFigure 63

RSL effective input resistance @ tCYCLE=2.5ns 415

a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V.

Table 18: CMOS Pin Parasitics

Symbol Parameter and Conditions - CMOS pins Min Max Unit Figure

LI ,CMOS CMOS effective input inductance 8.0 nH

Figure 63CI ,CMOS CMOS effective input capacitance (SCK,CMD)a1.7 2.1 pF

CI ,CMOS,SIO CMOS effective input capacitance (SIO1, SIO0)a-7.0 pF

a. This value is a combination of the device IO circuitry and package capacitances.

Direct RDRAM™

K4R571669A/K4R881869A

Page 18 Version 1.4 July 2002

Center-Bonded WBGA Package

(92balls)

Figure4 shows the form and dimensions of the recom-

mended package for the 92balls center-bonded WBGA

device class.

Figure 4: Center-Bonded WBGA Package

Table19 lists the numerical values corresponding to dimen-

sions shown in Figure4. Table 19: Center-Bonded WBGA Package Dimensions

ABCDEFG H J

8e2

TopBottom

Bottom

KLMNPRSTU

Bottom

Symbol Parameter Min(256/288Mb) Max(256/288Mb) Unit

e1 Ball pitch (x-axis) 0.80 0.80 mm

e2 Ball pitch (y-axis) 0.80 0.80 mm

APackage body length 9.2/10.4 9.4/10.6 mm

DPackage body width 15.0/17.9 15.2/18.1 mm

EPackage total thickness 0.98 1.08 mm

E1 Ball height 0.30 0.40 mm

dBall diameter 0.40 0.50 mm