0
2
4
6
8
10
12
14
16
0 2 4 6 8 10 12 14 16 18 20
VGS - Gate-to- Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
TC = 25°C Id = 25A
TC = 125ºC Id = 25A
G001
0
2
4
6
8
10
0 5 10 15 20 25 30 35 40 45
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
ID = 25A
VDS = 30V
G001
1D
2D
3D
4
D
D
5
G
6S
7
S
8S
P0093-01
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18532Q5B
SLPS322D –NOVEMBER 2012–REVISED FEBRUARY 2018
CSD18532Q5B 60-V N-Channel NexFET™ Power MOSFETs
1
1 Features
1• Ultra-Low Qgand Qgd
• Low-Thermal Resistance
• Avalanche Rated
• Logic Level
• Lead-Free Terminal Plating
• RoHS Compliant
• Halogen Free
• SON 5-mm × 6-mm Plastic Package
2 Applications
• DC-DC Conversion
• Secondary Side Synchronous Rectifier
• Isolated Converter Primary Side Switch
• Motor Control
3 Description
This 2.5-mΩ, 60-V SON 5-mm × 6-mm NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
Top View
Product Summary
TA= 25°C TYPICAL VALUE UNIT
VDS Drain-to-Source Voltage 60 V
QgGate Charge Total (10 V) 44 nC
Qgd Gate Charge Gate-to-Drain 6.9 nC
RDS(on) Drain-to-Source On-Resistance VGS = 4.5 V 3.3 mΩ
VGS = 10 V 2.5
VGS(th) Threshold Voltage 1.8 V
Device Information(1)
DEVICE QTY MEDIA PACKAGE SHIP
CSD18532Q5B 2500 13-Inch Reel SON
5.00-mm × 6.00-mm
Plastic Package
Tape
and
Reel
CSD18532Q5BT 250 13-Inch Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA= 25°C VALUE UNIT
VDS Drain-to-Source Voltage 60 V
VGS Gate-to-Source Voltage ±20 V
ID
Continuous Drain Current (Package Limited) 100
A
Continuous Drain Current (Silicon Limited),
TC= 25°C 172
Continuous Drain Current(1) 23
IDM Pulsed Drain Current(2) 400 A
PDPower Dissipation(1) 3.2 W
Power Dissipation, TC= 25°C 156
TJ,
Tstg Operating Junction Temperature,
Storage Temperature –55 to 150 °C
EAS Avalanche Energy, Single Pulse
ID= 80 A, L = 0.1 mH, RG= 25 Ω320 mJ
(1) Typical RθJA = 40°C/W on a 1-in2, 2-oz Cu pad on a 0.06-in
thick FR4 PCB.
(2) Max RθJC = 0.8°C/W, pulse duration ≤100 μs, duty cycle ≤
1%.
RDS(on) vs VGS Gate Charge
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6 Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
6.2 Community Resources.............................................. 7
6.3 Trademarks............................................................... 7
6.4 Electrostatic Discharge Caution................................ 7
6.5 Glossary.................................................................... 7
7 Mechanical, Packaging, and Orderable
Information............................................................. 8
7.1 Q5B Package Dimensions........................................ 8
7.2 Recommended PCB Pattern..................................... 9
7.3 Recommended Stencil Pattern ................................. 9
7.4 Q5B Tape and Reel Information............................. 10
4 Revision History
Changes from Revision C (May 2017) to Revision D Page
• Extended the VDS on Figure 5 to 60 V.................................................................................................................................... 4
Changes from Revision B (July 2014) to Revision C Page
• Added the Receiving Notification of Documentation Updates and Community Resources sections to Device and
Documentation Support. ........................................................................................................................................................ 7
• Changed the dimension between pads 3 and 4 from 0.028 inches: to 0.050 inches in the Recommended PCB
Pattern section diagram ......................................................................................................................................................... 9
Changes from Revision A (May 2014) to Revision B Page
• Changed "7-Inch Reel" to state "13-Inch Reel". .................................................................................................................... 1
Changes from Original (Nov 2012) to Revision A Page
• Updated the device description. ............................................................................................................................................ 1
• Specified Qgat 10 V. ............................................................................................................................................................. 1
• Added small reel option. ........................................................................................................................................................ 1
• Increased pulsed drain current to 400 A. .............................................................................................................................. 1
• Added line for max power dissipation with case temperature held to 25°C. ......................................................................... 1
• Updated the pulsed drain current conditions. ........................................................................................................................ 1
• Eliminated Qgat 4.5 V. .......................................................................................................................................................... 3
• Changed Figure 1 from a normalized RθJA curve to a RθJC curve........................................................................................... 4
• Updated the safe operating area in Figure 10. ...................................................................................................................... 6
• Updated the mechanical drawing. ......................................................................................................................................... 8
3
CSD18532Q5B
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5 Specifications
5.1 Electrical Characteristics
TA= 25°C unless otherwise stated
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID= 250 μA 60 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 48 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID= 250 μA 1.5 1.8 2.2 V
RDS(on) Drain-to-source on-resistance VGS = 4.5 V, ID= 25 A 3.3 4.3 mΩ
VGS = 10 V, ID= 25 A 2.5 3.2
gfs Transconductance VDS = 30 V, ID= 25 A 143 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 30 V, ƒ = 1 MHz 3900 5070 pF
Coss Output capacitance 470 611 pF
Crss Reverse transfer capacitance 13 17 pF
RGSeries gate resistance 1.2 2.4 Ω
QgGate charge total (10 V)
VDS = 30 V, ID= 25 A
44 58 nC
Qgd Gate charge gate-to-drain 6.9 nC
Qgs Gate charge gate-to-source 10 nC
Qg(th) Gate charge at Vth 6.3 nC
Qoss Output charge VDS = 30 V, VGS = 0 V 52 nC
td(on) Turnon delay time
VDS = 30 V, VGS = 10 V,
IDS = 25 A, RG= 0 Ω
5.8 ns
trRise time 7.2 ns
td(off) Turnoff delay time 22 ns
tfFall time 3.1 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 25 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge VDS = 30 V, IF= 25 A,
di/dt = 300 A/μs111 nC
trr Reverse recovery time 49 ns
(1) RθJC is determined with the device mounted on a 1-in2(6.45-cm2), 2-oz. (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2(6.45-cm2), 2-oz (0.071-mm) thick Cu.
5.2 Thermal Information
TA= 25°C unless otherwise stated THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 0.8 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 50 °C/W
GATE Source
DRAIN
N-Chan5x6QFNTTAMAXRev3
M0137-01
GATE Source
DRAIN
N-Chan5x6QFNTTAMINRev3
M0137-02
4
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SLPS322D –NOVEMBER 2012–REVISED FEBRUARY 2018
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Max RθJA = 50°C/W
when mounted on 1 in2
(6.45 cm2) of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
5.3 Typical MOSFET Characteristics
TA= 25°C unless otherwise stated
Figure 1. Transient Thermal Impedance
0
2
4
6
8
10
0 5 10 15 20 25 30 35 40 45
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
ID = 25A
VDS = 30V
G001
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
0 6 12 18 24 30 36 42 48 54 60
10
100
1000
10000
100000
D005
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
5
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Typical MOSFET Characteristics (continued)
TA= 25°C unless otherwise stated
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
6
CSD18532Q5B
SLPS322D –NOVEMBER 2012–REVISED FEBRUARY 2018
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Typical MOSFET Characteristics (continued)
TA= 25°C unless otherwise stated
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
7
CSD18532Q5B
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Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
D1
Top View
E
c1
•
E1
4
1 2 3
Side View Bottom View
Front View
14
b (8x)
3
2
e
L
K
H
D2
8
5 6 7
•
8
5 6 7
D3
d1
d2
8
CSD18532Q5B
SLPS322D –NOVEMBER 2012–REVISED FEBRUARY 2018
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Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q5B Package Dimensions
DIM MILLIMETERS
MIN NOM MAX
A 0.80 1.00 1.05
b 0.36 0.41 0.46
c 0.15 0.20 0.25
c1 0.15 0.20 0.25
c2 0.20 0.25 0.30
D1 4.90 5.00 5.10
D2 4.12 4.22 4.32
D3 3.90 4.00 4.10
d 0.20 0.25 0.30
d1 0.085 TYP
d2 0.319 0.369 0.419
E 4.90 5.00 5.10
E1 5.90 6.00 6.10
E2 3.48 3.58 3.68
e 1.27 TYP
H 0.36 0.46 0.56
L 0.46 0.56 0.66
L1 0.57 0.67 0.77
θ0° — —
K 1.40 TYP
4.318 (0.170)
2.186
6.586
0.350
(0.014)
1.294
x 8
(0.051)
0.746 x 8
(0.029)
(0.259)
1.072
(0.042)
1.270
0.562 x 4
(0.022)
0.300
(0.012)
(0.086)
(0.050)
1.525
(0.060)
0.508
x4
(0.020)
1.270 (0.050)
0.286
(0.011)
0.766
(0.030)
9
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7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Recommended Stencil Pattern
Ø 1.50 +0.10
–0.00
4.00 ±0.10 (See Note 1)
1.75 ±0.10
R 0.30 TYP
Ø 1.50 MIN
A0
K0
0.30 ±0.05
R 0.30 MAX
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
M0138-01
2.00 ±0.05
8.00 ±0.10
B0
12.00 ±0.30
5.50 ±0.05
10
CSD18532Q5B
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7.4 Q5B Tape and Reel Information
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jun-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD18532Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHS
Exempt) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 150 CSD18532
CSD18532Q5BT ACTIVE VSON-CLIP DNK 8 250 Pb-Free (RoHS
Exempt) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 150 CSD18532
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
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Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
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