VCC GND
0.1 µF
5.0 V
RI+
RI-
RO
DO+
DO-
DI
Product
Folder
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Tools &
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DS8921x Differential Line Driver and Receiver Pair
1 Features 3 Description
The DS8921, DS8921A, and DS8921AT devices are
1• 12-ns Typical Propagation Delay differential line driver and receiver pairs designed
• Output Skew: 0.5 ns Typical specifically for applications meeting the ST506,
• Meets the Requirements of EIA Standard RS-422 ST412, and ESDI disk drive standards. In addition,
these devices meet the requirements of the EIA
• Complementary Driver Outputs standard RS-422.
• High Differential or Common-Mode Input Voltage
Ranges of ±7 V The DS8921x receivers offer an input sensitivity of
200 mV over a ±7 V common mode operating range.
• ±0.2 V Receiver Sensitivity Over the Input Voltage Hysteresis is incorporated (typically 70 mV) to
Range improve noise margin for slowly changing input
• Receiver Input Hysteresis: 70 mV Typical waveforms.
• DS8921AT Industrial Temperature Operation: The DS8921x drivers are designed to provide
(−40°C to +85°C) unipolar differential drive to twisted-pair or parallel
wire transmission lines. Complementary outputs are
2 Applications logically ANDed and provide an output skew of 0.5 ns
(typical) with propagation delays of 12 ns.
• Differential Line Driver and Receiver for:
– ST506 Disk Drive Standard The DS8921x devices are designed to be compatible
with TTL and CMOS.
– ST412 Disk Drive Standard
– ESDI Disk Drive Standard Device Information(1)
– RS-422 Interface PART NUMBER PACKAGE BODY SIZE (NOM)
DS8921 SOIC (8) 4.90 mm x 3.91 mm
DS8921A PDIP (8) 9.81 mm x 6.35 mm
DS8921AT
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE Typical Application Block Diagram Simplified Functional Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS8921
,
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,
DS8921AT
SNLS374D –MAY 1998–REVISED JANUARY 2015
www.ti.com
Table of Contents
8.1 Overview................................................................... 8
1 Features.................................................................. 18.2 Functional Block Diagram......................................... 8
2 Applications ........................................................... 18.3 Feature Description................................................... 8
3 Description............................................................. 18.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 29 Application and Implementation .......................... 9
5 Pin Configuration and Functions......................... 39.1 Application Information.............................................. 9
6 Specifications......................................................... 39.2 Typical Application.................................................... 9
6.1 Absolute Maximum Ratings ...................................... 310 Power Supply Recommendations ..................... 12
6.2 ESD Ratings.............................................................. 411 Layout................................................................... 12
6.3 Recommended Operating Conditions....................... 411.1 Layout Guidelines ................................................. 12
6.4 Electrical Characteristics........................................... 411.2 Layout Example .................................................... 12
6.5 Receiver Switching Characteristics .......................... 512 Device and Documentation Support................. 13
6.6 Driver Switching Characteristics: Single-Ended
Characteristics ........................................................... 512.1 Related Links ........................................................ 13
6.7 Driver Switching Characteristics: Differential 12.2 Trademarks........................................................... 13
Characteristics ........................................................... 512.3 Electrostatic Discharge Caution............................ 13
6.8 Typical Characteristics.............................................. 612.4 Glossary................................................................ 13
7 Parameter Measurement Information .................. 613 Mechanical, Packaging, and Orderable
7.1 AC Test Circuits and Switching Diagrams................ 6Information ........................................................... 13
8 Detailed Description.............................................. 8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision B (November 2004) to Revision C Page
• Changed layout of National Data Sheet to TI format. ........................................................................................................... 1
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5 Pin Configuration and Functions
D, P Package
8 Pins
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DIFFERENTIAL SIGNALING I/O
DI 3 I TTL/CMOS Compatible Driver Input
DO+, DO– 6, 5 O Inverting and non-inverting differential driver outputs
RI+, RI– 8, 7 I Inverting and non-inverting differential receiver inputs
RO 2 O Receiver Output Pin
POWER
GND 4 Power Ground Pin
VCC 1 Power Supply pin, provide 5-V supply
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN MAX UNIT
Supply Voltage 7 V
Driver Input Voltage −0.5 7 V
Output Voltage 5.5 V
Receiver Output Sink Current 50 mA
Receiver Input Voltage –10 10 V
Differential Input Voltage –12 12 V
Maximum Package Power Dissipation at 25°C: D Package 730 mW
Maximum Package Power Dissipation at 25°C: P Package 1160 mW
Derate D Package, above 25°C 9.3 mW/°C
Derate P Package, above 25°C 5.8 mW/°C
Lead Temperature 260 °C
(Soldering, 4 sec.) 260 °C
Maximum Junction Temperature 150 °C
Storage Temperature, Tstg −65 165 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instrument Sales Office/ Distributors for availability and
specifications.
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6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN MAX UNIT
Supply Voltage 4.5 5.5 V
Temperature (TA): DS8921/DS8921A 0 70 °C
Temperature (TA): DS8921AT −40 85 °C
6.4 Electrical Characteristics
Over operating free-air temperature range unless otherwise noted.(1)(2)(3)
TEST CONDITIONS MIN TYP MAX UNIT
RECEIVER
VTH −7 V ≤VCM ≤+7 V −200 ±35 +200 mV
VHYST −7 V ≤VCM ≤+7 V 15 70 mV
RIN VIN =−7 V, +7 V, (Other Input = GND) 4.0 6.0 kΩ
VIN = 10 V 3.25 mA
IIN VIN =−10 V −3.25 mA
VOH IOH =−400 μA 2.5 V
VOL IOL = 8 mA 0.5 V
ISC VCC = MAX, VOUT = 0 V −15 −100 mA
DRIVER
VIH 2.0 V
VIL 0.8 V
IIL VCC = MAX, VIN = 0.4 V −40 −200 μA
IIH VCC = MAX, VIN = 2.7 V 20 μA
IIVCC = MAX, VIN = 7.0 V 100 μA
VCL VCC = MIN, IIN =−18 mA −1.5 V
VOH VCC = MIN, IOH =−20 mA 2.5 V
VOL VCC = MIN, IOL = +20 mA 0.5 V
IOFF VCC = 0V, V OUT = 5.5 V 100 μA
|VT| – |VT| 0.4 V
VT2.0 V
|VOS – VOS| 0.4 V
ISC VCC = MAX, VOUT = 0 V −30 −150 mA
DRIVER AND RECEIVER
ICC VCC = MAX, VOUT = Logic 0 35 mA
(1) All currents into device pins are shown as positive values; all currents out of the device are shown as negative; all voltages are
referenced to ground unless otherwise specified. All values shown as max or min are classified on absolute value basis.
(2) All typical values are VCC = 5 V, TA= 25°C.
(3) Only one output at a time should be shorted.
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results assume a linear transition between measurement points and are a result of the following equations: Where:
DS8921
,
DS8921A
,
DS8921AT
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SNLS374D –MAY 1998–REVISED JANUARY 2015
6.5 Receiver Switching Characteristics MAX MAX MAX
TEST CONDITIONS MIN TYP UNIT
8921 8921A 8921AT
tpLH CL= 30 pF 14 22.5 20 20 ns
(Figure 3 and Figure 4)
tpHL CL= 30 pF 14 22.5 20 20 ns
(Figure 3 and Figure 4)
|tpLH–t pHL| CL= 30 pF 0.5 5 3.5 5 ns
(Figure 3 and Figure 4)
6.6 Driver Switching Characteristics: Single-Ended Characteristics
MAX MAX MAX
TEST CONDITIONS MIN TYP UNIT
8921 8921A 8921AT
tpLH CL= 30 pF 10 15 15 15 ns
(Figure 5 and Figure 6)
tpHL CL= 30 pF 10 15 15 15 ns
(Figure 5 and Figure 6)
tTLH CL= 30 pF 5 8 8 9.5 ns
(Figure 9 and Figure 10)
tTHL CL= 30 pF 5 8 8 9.5 ns
(Figure 9 and Figure 10)
Skew CL = 30 pF(1) 1 5 3.5 3.5 ns
(Figure 5 and Figure 6)
(1) Difference between complementary outputs at the 50% point.
6.7 Driver Switching Characteristics: Differential Characteristics(1)
MAX MAX MAX
TEST CONDITIONS MIN TYP UNIT
8921 8921A 8921AT
tpLH CL= 30 pF 10 15 15 15 ns
(Figure 5,Figure 7, and Figure 8)
tpHL CL= 30 pF 10 15 15 15 ns
(Figure 5,Figure 7, and Figure 8)
|tpLH–t pHL| CL= 30 pF 0.5 6 2.75 2.75 ns
(Figure 5,Figure 7, and Figure 8)
(1) Differential Delays are defined as calculated results from single ended rise and fall time measurements. This approach in establishing
AC performance specifications has been taken due to limitations of available Automatic Test Equipment (ATE). The calculated ATE
Tcr = Crossing Point Tra, Trb, Tfa and T fb are time measurements with respect to the input. See Figure 8.
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NOTE:R1= 100 Ohms, C1 = C2 = C3 = 30 pF
R1
C1 C2
C3
D
4.4
4.6
4.8
5.0
5.2
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Low to High Transition Time (ns)
Supply Voltage (V)
T(TLH)
C004
C005
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,
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,
DS8921AT
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6.8 Typical Characteristics
Test Setup: Figure 5. Data Rate, Test Pattern: 2 Mbps, 1010 Pattern. T: 25°C
Figure 1. Typical Driver Output Low to High Transition Time Figure 2. Typical Driver Output High to Low Transition Time
vs Supply Voltage vs Supply Voltage
7 Parameter Measurement Information
7.1 AC Test Circuits and Switching Diagrams
Figure 3. Test Circuit for Receiver Output
Figure 4. Receiver Propagation Delay
Figure 5. Driver Test Circuit
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AC Test Circuits and Switching Diagrams (continued)
Figure 6. Driver Single-Ended Propagation Delay
Figure 7. Driver Differential Propagation Delay
Figure 8. Driver Delay ATE Testing
Figure 9. Driver Output Transition Time
Figure 10. Driver Output Transition Time
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VCC GND
0.1 µF
5.0 V
RI+
RI-
RO
DO+
DO-
DI
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DS8921AT
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8 Detailed Description
8.1 Overview
The DS8921x devices are each a differential line driver and receiver pair in a single package. The devices are
designed specifically for ST506, ST412, and ESDI disk drive standards, as well as RS-422 interface applications.
The DS8921 and DS8921A are rated at a commercial temperature range of 0°C to 70°C, whereas the
DS8921AT is rated at an extended temperature range of -40°C to +85°C.
8.2 Functional Block Diagram
8.3 Feature Description
The DS8921x devices each contain a differential driver and receiver.
The driver converts a TTL or CMOS input to complementary outputs that provide differential drive to a twisted-
pair or parallel wire transmission line. The receiver converts the differential signals at its input pins to a TTL
output. The receiver offers an input sensitivity of ±200 mV and supports a common-mode input voltage of ±7 V.
8.4 Device Functional Modes
Table 1. Function Table
RECEIVER DRIVER
INPUT OUTPUT INPUT OUTPUT
RI+, RI- RO DI DO+ DO-
VID(1) ≥VTH (MAX) 1 1 1 0
VID(1) ≤VTH (MIN) 0 0 0 1
Open 1
(1) VID is the input differential voltage between RI+ and RI–.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS8921 is a differential line driver and receiver pair in a single package, designed for applications for the
ST506, ST412, and ESDI Disk Drive Standards. The DS8921 is compatible to EIA RS-422 signaling standards,
supporting 200-mV input sensitivity across a ±7-V common mode operating range. This transceiver is intended
for driving differential signal across long transmission lines and translating received differential signals into their
CMOS/TTL single-ended equivalence. The DS8921 transmits and reproduces received data in communications
links where ground reference difference, or noisy environment are common.
9.2 Typical Application
Figure 11 shows a typical implementation of the DS8921x device in a ST506 and ST412 disk drive application.
The differential outputs of the driver are connected to a twisted-pair transmission line, carrying data from the
driver to the differential receiver at the other end of the cable. A differential termination resistor should be
connected across the input pins of the receiver.
Figure 11. ST506 and ST412 Application
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Time (400 ns/DIV)
Data Signal (2 V/DIV)
0 V
Time (400 ns/DIV)
Data Signal (2 V/DIV)
0 V
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,
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,
DS8921AT
SNLS374D –MAY 1998–REVISED JANUARY 2015
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Typical Application (continued)
9.2.1 Design Requirements
• Apply TTL or LVCMOS signal to driver input at DI
• Transmit complementary outputs at DO+ and DO-
• Receive complimentary input signals at RI+ and RI-
• Receive TTL output signal at RO
• Use controlled-impedance transmission lines such as printed circuit board traces, twisted-pair wires or parallel
wire cable
• Place terminating resistor at the far end of the differential pair
9.2.2 Detailed Design Procedure
• Connect VCC and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass
capacitor
• Use TTL/LVCMOS logic levels at DI and RO
• Use controlled-impedance transmission media for the differential signals DI+- and RO+-
• Place a terminating resistor at the far-end of the differential pair to avoid reflection
• Ensure the received complimentary signals at RO+ and RO- are within the signal threshold of ±200 mV
9.2.3 Application Curves
2.0 Mbps Single-Ended 1010 Data Pattern 2.0 Mbps Differential Data Pattern
Note: The input for the driver is Figure 12
Figure 12. Driver Single-Ended Input Signal Figure 13. Driver Differential Output Signal
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Time (400 ns/DIV)
Data Signal (2 V/DIV)
0 V
Time (400 ns/DIV)
Data Signal (2 V/DIV)
0 V
DS8921
,
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,
DS8921AT
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SNLS374D –MAY 1998–REVISED JANUARY 2015
Typical Application (continued)
2.0 Mbps Differential Data Pattern 2.0 Mbps Single-Ended 1010 Data Pattern
Note: The input for the receiver is Figure 14
Figure 14. Receiver Differential Input Signal Figure 15. Receiver Single-Ended Output Signal
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DS8921/DS8921A/DS8921AT
1
2
3
4
5
6
7
8
Via to VCC
Plane
Via to GND
Plane
Via to GND
Plane
RX Differential Pair
TX Differential Pair
Termination
Resistor
Bypass Capacitor
DS8921
,
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,
DS8921AT
SNLS374D –MAY 1998–REVISED JANUARY 2015
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10 Power Supply Recommendations
TI recommends connecting the supply (VCC) and ground (GND) pins to power planes that are routed on
adjacent layers of the PCB. Additionally, careful attention should be paid to bypassing the supply using a
capacitor. A 0.1-µF bypass capacitor should be connected to the VCC pin such that the capacitor is as close as
possible to the device.
11 Layout
11.1 Layout Guidelines
High-speed interconnects should be treated as transmission lines with a controlled impedance. The differential
interconnect can be a pair of printed-circuit board (PCB) traces, twisted-pair wires, or a parallel wire cable. A
termination resistor should be placed at the differential input, and the resistor value should be approximately the
same as the differential impedance of the transmission line to minimize reflections.
It is preferable to connect the VCC and GND pins to the power and ground planes using plated-through-holes.
Additionally, a 0.1-µF bypass capacitor should be placed close to the VCC pin across VCC and GND.
Place a terminating resistor at the receiving end of the interconnect transmission line, as close as possible to the
input pins of the receiver. The terminating resistor value should be approximately the same as the differential pair
impedance to minimize reflection, and the transmission line should have a controlled impedance with minimum
impedance discontinuities.
The input and output differential signals of the device should have traces that are routed exclusively on one layer
of the board, and the differential pairs should also be routed away from other differential pairs in order to
minimize crosstalk between transmission lines. Additionally, the differential pairs should have a controlled
impedance with minimum impedance discontinuities and be terminated with a resistor that is closely matched to
the differential pair impedance in order to minimize transmission line reflections. The differential pairs should be
routed with uniform trace width and spacing to minimize impedance mismatch.
11.2 Layout Example
Figure 16. DS8921 Example Layout
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
DS8921 Click here Click here Click here Click here Click here
DS8921A Click here Click here Click here Click here Click here
DS8921AT Click here Click here Click here Click here Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DS8921 DS8921A DS8921AT
PACKAGE OPTION ADDENDUM
www.ti.com 9-Jul-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS8921AM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 DS89
21AM
DS8921AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 DS89
21AM
DS8921ATM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 DS892
1ATM
DS8921ATMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 DS892
1ATM
DS8921M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 DS892
1M
DS8921MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 DS892
1M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Jul-2020
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS8921AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
DS8921MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS8921AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
DS8921MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 2
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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