DATA SHEET O K I A S I C P R O D U C T S MG87P3/87P4/87P5 0.25m Standard Cell August 2002 ------------------------------------------------------------------------------------------- CONTENTS Description ................................................................................................................................................................1 Features .....................................................................................................................................................................1 Array Architecture ...................................................................................................................................................2 MG87P3/87P4/87P5 SC Layout Methodology .............................................................................................3 Electrical Characteristics .........................................................................................................................................5 Macro Library ...........................................................................................................................................................7 Macrocells for Driving Clock Trees ................................................................................................................8 OKI Advanced Design Center Cad Tools .............................................................................................................9 Design Process .................................................................................................................................................10 Automatic Test Pattern Generation ..............................................................................................................11 Floorplanning Design Flow ...........................................................................................................................11 IEEE JTAG Boundary Scan .............................................................................................................................13 Package Options .....................................................................................................................................................13 Oki Semiconductor MG87P3/87P4/87P5 0.25m Standard Cell DESCRIPTION Oki's 0.25m Application-Specific Integrated Circuit (ASIC) products are available in Standard Cell (SC) architectures. The SC-based MG87P3/87P4/87P5 series uses 0.25m drawn (0.18m L-effective) CMOS technology. The MG87P3/87P4/87P5 series uses three, four and five metal, respectively. The semiconductor process is adapted from Oki's production-proven 64Mbit DRAM manufacturing process. The 0.25m SC family provides significant performance, density, and power improvement over previous 0.25m SOG/EA technologies. The Cell library is optimized for synthesis-based design and is designed for low power and high speed by improving transistor architecture. The 0.25m SC Cell library structure provides 5 to 10% less power and 18% faster than previous 0.25m SOG/EA technologies. The 0.25m SC family operates using 2.5-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal MG87P3/87P4/87P5 series contains 21 array bases, offering up to 868 I/O pads and over 5.5M raw gates. These SC sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), plastic ball grid array (PBGA), and metal ball grid array (MBGA) packages. Oki uses the Artisan Components memory compiler for SC designs. As such, the MG87P3/87P4/87P5 series is suited for memory-intensive ASICs and high volume designs where fine tuning of package size produces significant cost or real-estate savings. FEATURES * * * * * * * * * 0.25m drawn 3-, 4-, and 5-layer metal CMOS Optimized 2.5-V core Optimized 3-V I/O Optimized 5-V Tolerant I/O 48-ps typical gate propagation delay (for a 4xdrive inverter gate with a fanout of 2 and 0 mm of wire, operating at 2.5 V) Over 5.5M raw gates and 868 I/O pads using 60 staggered I/O User-configurable I/O with VSS, VDD, TTL, 3-state, and 1- to 24-mA options Slew-rate-controlled outputs for low-radiated noise Clock tree cells which reduces the maximum skew for clock signals * Low power design method * Low 0.2W/MHz/gate power dissipation * User-configurable single- and dual-port memories * Specialized IP cores and macrocells including 32-bit ARM7TDMI CPU, phase-locked loop (PLL), and peripheral component interconnect (PCI) cells * Floorplanning for front-end simulation, backend layout controls, and link to synthesis * Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG) * Built-in Self Test (BIST) for memory testing * Support for popular CAE systems including Cadence, Model Technology, Inc. (MTI), and Oki Semiconductor 1 MG87P3/87P4/87P5 --------------------------------------------------------------------------- MG87P3/87P4/87P5 Family Listing No of Pads MG87P3 Family 3LM Usable Gate MG87P4 Family 4LM Usable Gate MG87P5 Family 5LM Usable Gate MG87PxB02 68 22,000 24,000 24,000 MG87PxB04 108 63,000 72,000 72,000 MG87PxB06 148 117,000 144,000 144,000 MG87PxB08 188 184,000 241,000 243,000 MG87PxB10 228 259,000 344,000 367,000 MG87PxB12 268 342,000 456,000 515,000 MG87PxB14 308 428,000 574,000 676,000 MG87PxB16 348 524,000 702,000 824,000 MG87PxB18 388 633,000 844,000 997,000 MG87PxB20 428 717,000 976,000 1,135,000 MG87PxB22 468 810,000 1,086,000 1,277,000 MG87PxB24 508 938,000 1,225,000 1,450,000 MG87PxB26 548 1,072,000 1,382,000 1,621,000 MG87PxB28 588 1,211,000 1,542,000 1,817,000 MG87PxB30 628 1,354,000 1,700,000 2,016,000 MG87PxB32 668 1,499,000 1,857,000 2,214,000 MG87PxB34 708 1,648,000 2,010,000 2,412,000 MG87PxB36 748 1,798,000 2,158,000 2,607,000 MG87PxB38 788 1,949,000 2,299,000 2,799,000 MG87PxB40 828 2,100,000 2,432,000 2,985,000 MG87PxB42 868 2,250,000 2,554,000 3,162,000 SC Base Array ARRAY ARCHITECTURE The primary components of a 0.25m MG87P3/87P4/87P5 circuit include: * * * * * * * * * I/O base cells 60m pad pitch Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility Innovative 4-transistor core cell architecture, licensed from In-Chip Systems, Inc Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO). 2 Oki Semiconductor -------------------------------------------------------------------------- MG87P3/87P4/87P5 I/O base cells Separate power bus (VDDC, VSSC) for internal core logic (2nd metal/3rd metal) Configurable I/O pads for VDD, VSS, or I/O 1, 2, 3, 4, or 5 layer metal interconnection in core area Core library cell VDD, VSS pads (4) in each corner for wafer probing only Separate power bus (VDDO, VSSO) over I/O cell for output buffers (2nd metal/3rd metal) Figure 1. MG87P5 Array Architecture MG87P3/87P4/87P5 SC Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify macrocell functions required and minimum array size to hold macrocell functions. - Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design's megacells. - Oki Design Center engineers verify the master slice and review simulation. - Oki Design Center or customer engineers floorplan the array using Oki's supported floorplanner or Cadence DP3 and customer performance specifications. Oki Semiconductor 3 MG87P3/87P4/87P5 --------------------------------------------------------------------------- Figure 2 shows an array base after placement of the optimized memory macrocells. High-density RAM Mega macrocells Figure 2. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 3 marks the area in which placement and routing is performed with cross hatching. Figure 3. Random Logic Place and Route 4 Oki Semiconductor -------------------------------------------------------------------------- MG87P3/87P4/87P5 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0 V, TJ = 25C) [1] Symbol Rated Value Unit VDD Core (2.5 V) -0.3 to +3.6 V Parameter Power supply voltage VDD I/O (3.3 V) -0.3 to +4.6 Input voltage (Input Buffer) VI -0.3 to VDDIO +0.3 Output voltage (Output Buffer) VO -0.3 to VDDIO +0.3 II -10 to +10 Input current (Input Buffer) Output current per I/O (Output Buffer) Storage temperature IO -24 to +24 TSTG -65 to +150 mA C 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (VSS = 0 V) Parameter Power supply voltage Junction temperature Symbol Rated Value Unit VDD Core (2.5 V) +2.25 to +2.75 V VDD I/O (3.3 V) +3.0 to +3.6 Tj -40 to +85 Oki Semiconductor C 5 MG87P3/87P4/87P5 --------------------------------------------------------------------------- DC Characteristics (VDD Core = 2.25 to 2.75 V, VDDI/O = 3.0 to 3.6 V, VSS = 0 V, Tj = -40 to +85C) Rated Value Parameter High-level input voltage Min. VIH TTL input (normal), VDD = VDD I/O 2.0 -0.0 - 0.8 - 1.5 2.0 0.7 1.0 - 0.4 0.5 - Low-level input voltage VIL TTL input (normal) Vt+ TTL input High-level output voltage (Normal buffer) VtVt VOH Vt+ - VtIOH = -100 A High-level input current (Normal buffer) Low-level input current (Normal buffer) 3-state output leakage current (Normal input buffer) Stand-by current [2] VOL IIH IIL - - - - IOL = 100 A - - 0.2 IOL = 1, 2, 4, 6, 8, 12, 24 mA - - 0.4 VIH = VDDIO - - 10 VIH = VDD (50-k pull-down) 10 66 200 VIL = VSS -10 - VIL = VSS (50-k pull-up) -200 -66 -10 VIL = VSS (3-k pull-up) -3.3 -1.1 -0.3 - 10 200 Oki Semiconductor V A IOZH VOH = VDD VOH = VDD (50-k pull-down) 10 66 IOZL VOL = VSS -10 - VOL = VSS (50-k pull-up) -200 -66 -10 VOL = VSS (3-k pull-up) -3.3 -1.1 -0.3 IDDQ Unit VDDIO +0.3 2.4 mA A Output open, VIH = VDDIO, VIL = VSS Design Dependent 1. VDDCORE = 2.5 V, VDDIO = 3.3 V, and Tj = 25C on a typical process. 2. RAM/ROM should be in powerdown mode. 6 - VDDIO -0.2 IOH = -1, -2, -4, -6, -8, -12, -24 mA Low-level output voltage (Normal buffer) Max. Conditions TTL- level Schmitt Trigger input buffer Threshold voltage Typ. [1] Symbol mA A -------------------------------------------------------------------------- MG87P3/87P4/87P5 AC Characteristics (Core VDD = 2.5 V, VSS = 0 V, Tj = 25C) Parameter Internal gate propagation delay Driving Type Inverter Conditions [1] [2] Rated Value 1X 0.082 2X 0.065 4X 2-input NAND Unit 0.048 F/O = 2, L = 0 mm VDD = 2.5 V 1X 2X 2-input NOR [3] 0.097 0.078 1X 0.096 2X 0.075 1X 0.296 2X 0.179 ns Inverter 4X 2-input NAND F/O = 2, L = standard wire length VDD = 2.5 V 1X 2X 2-input NOR 0.109 0.340 0.205 1X 0.304 2X 0.186 Toggle frequency F/O = 1, L = 0 mm 1422 MHz 1. Input transition time in 0.15 ns / 2.5 V. 2. Typical condition is VDDCORE = 2.5 V, VDDIO = 3.3 V and Tj = 25 oC for a typical process. 3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. AC Characteristics (I/O VDD = 3.3 V, VSS = 0 V, Tj = 25C) Conditions [1] [2] Parameter Input buffer propagation delay Output buffer propagation delay Output buffer transition time 1. 2. 3. 4. [4] Push-pull Normal output buffer Push-pull Normal output buffer 4 mA Rated Value [3] Unit F/O = 2, L = standard wire length 0.311 ns CL = 20 pF 1.783 ns 8 mA CL = 50 pF 2.011 ns 12mA CL = 100 pF 2.562 ns 12 mA CL = 100 pF 3.325 (r) ns 12 mA CL = 100 pF 3.043 (f) ns Input transition time in 0.15 ns / 2.5 V. Typical condition is VDDCORE = 2.5 V, VDDIO = 3.3 V and Tj = 25 oC for a typical process. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. Output rising and falling times are both specified over a 10 to 90% range. MACRO LIBRARY Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available. Oki Semiconductor 7 MG87P3/87P4/87P5 --------------------------------------------------------------------------- Examples Basic Macrocells NANDs NORs Basic Macrocells with Scan Test Flip-Flops EXORs Latches Flip-Flops Combinational Logic Clock Tree Driver Macrocells Macrocells 3-V Output Macrocells MSI Macrocells Mega/Special Macrocells [1] 3-State Outputs Push-Pull Outputs Open Drain Outputs Slew Rate Control Outputs PCI Outputs Counters Shift Registers ARM7TDMI PLL Macro Library 3-V Input Macrocells 3-V Bi-Directional Macrocells Macrofunctions Inputs Inputs with Pull-Downs Inputs with Pull-Ups I/O PCI I/O Oscillator Macrocells Gated Oscillators Memory Macrocells SOG RAMs: Single-Port RAMs Dual-Port RAMs MSI Macrofunctions I/O with Pull-Downs I/O with Pull-Ups Optimized Diffused RAMs: Single-Port RAMs Dual-Port RAMs 4-Bit Register/Latches [1] Under development Figure 4. Oki Macrocell and Macrofunction Library Macrocells for Driving Clock Trees Oki offers the EnvisiaTM clock-tree clock tree generator (CT-Gen). The CT-Gen generates post placement buffered clock trees that help minimize problems associated with clock skew. CT-Gen optimizes the following when it generates clock trees: * * * * * 8 Maximum load, maximum transition, wire self-heat, and hot electron constraints Maximum insertion delay Maximum skew Clock tree size (if the above constraints are met) Minimum insertion delay (satisfied by padding the root) Oki Semiconductor -------------------------------------------------------------------------- MG87P3/87P4/87P5 OKI ADVANCED DESIGN CENTER CAD TOOLS Oki's advanced design center CAD tools include support for the following: * * * * Floorplanning for front-end simulation and back-end layout control Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements Vendor Platform Operating System [1] Vendor Software/Revision [1] Description Ambit Buildgates NC-VerilogTM Verilog XL Design Synthesis Design Simulation Design Simulation Cadence Sun(R) [2] Solaris Syntest Sun(R) [2] Solaris Turbo Fault Fault Simulation Design synthesis Test Synthesis Static Timing Analysis (STA) Test synthesis RTL check Design Simulation Synopsys Sun(R) [2] Solaris Design Compiler Ultra + Tetramax/ATPG Primetime DFT Compiler/Test Compiler RTL Analyzer VCS Model Technology Inc. (MTI) Sun(R) [2] NT Solaris WinNT4.0 MTI-VHDL MTI-Verilog Design Simulation Design Simulation Oki Sun(R) [2] Solaris Floorplanner Floor planning (R) [2] Solaris Conformal Formal Verification Verplex Sun 1. Contact Oki Application Engineering for current software versions. 2. Sun or Sun-compatible. Oki Semiconductor 9 MG87P3/87P4/87P5 --------------------------------------------------------------------------- Design Process The following figure illustrates the overall IC design process, also indicating the three main interface points between external design houses and Oki ASIC Application Engineering. Level 1 [4] VHDL/HDL Description Synopsys Timing Script (optional) Functional Test Vectors Synthesis / Power Synthesis CAE Front-End Floorplanning Gate-Level Simulation Level 2 Netlist Conversion (EDIF 200) Test Vector Conversion (Oki TPL [3]) Scan Insertion (Optional) TDC [2] CDC [1] Formal Verification Floorplanning Pre-Layout Simulation Level 2.5 [4] Layout / Timing Driven Layout (optional) [6] Static Timing Analysis Fault Simulation [5] Oki Interface Automatic Test Pattern Generation Verification (Design Rule Check/Formal Verification) Post-Layout Simulation Level 3 [4] Manufacturing Prototype Test Program Conversion [1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data Check program (TDC) verifies test vector rules [3] Oki's Test Pattern Language (TPL) [4] Alternate Customer-Oki design interfaces available in addition to standard level 2 [5] Standard design process includes fault simulation [6] Requires Synopsys timing script for Oki timing driven layout Figure 5. Oki's Design Process 10 Oki Semiconductor -------------------------------------------------------------------------- MG87P3/87P4/87P5 Automatic Test Pattern Generation Oki's 0.25m ASIC technologies support ATPG using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler and Tetramax Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction ATPG methodology is described in detail in Oki's Scan Path Application Note. Combinational Logic A FD1AS Scan Data In D C SD SS B FD1AS Q QN D C SD SS Q Scan Data Out QN Scan Select Figure 6. Full Scan Path Configuration Floorplanning Design Flow Oki offers the floorplanning tool (OKI FP) for high-density ASIC design. The three main purposes for Oki's floorplanning tool is to: * Ensure conformance of critical circuit performance specifications * Shorten overall design TAT * Hierarchical Layout In a traditional design approach with synthesis tools, timing violations after pre layout simulation are fixed by manual editing of the net list. This process is difficult and time consuming. Also, there is no physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using predicted interconnection delay due to wire length. Synthesis tools may therefore create over-optimized result Floorplanning allows designers to control parasitic capacitance in a circuit by participating in the physical design process. Designers can partition their ASIC circuit in the most efficient hierarchical manner, and/or specify the exact placement of critical timing paths to guarantee high-speed performance. Floorplanning also allows the reduction of layout iterations, minimizing a design is overall TAT. As parasitic capacitance dominates a circuits timing in sub-micron technologies, an accurate capacitance estimation is crucial for accurate pre-layout timing simulation. Quite often, designers have to iterate the Oki Semiconductor 11 MG87P3/87P4/87P5 --------------------------------------------------------------------------- circuit layout because unexpected post-layout capacitance causes unacceptable circuit performance. More information on OKI's floorplanning capabilities is available in Oki's Application Note, Using Oki's Floorplanner: Standalone Operation and Links to Synopsys. HDL Entry Synthesis (Initial) Constraints Chip Level Netlist (1) Floor Plan (1) RC* Synthesis (Detail) Chip Level Netlist (2) Floor Plan (2) RC* DEF Delay Calculation STA SDF Block level Netlist NO Met Spec? YES Block-level Layout Chip-level Layout DSPF DSPF Delay Calculation Delay Calculation SDF SDF STA NO Block level STA Block Level Optimization (Option) Met Spec? YES Sign Off RC* - Supports SPEF and DSPF Figure 7. Design Flow 12 Oki Semiconductor -------------------------------------------------------------------------- MG87P3/87P4/87P5 IEEE JTAG Boundary Scan Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: * * * * * * Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register Oki's boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki supports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technologies. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki's JTAG Boundary Scan Application Note. (Contact the Oki Application Engineering Department for interface options.) PACKAGE OPTIONS TQFP, LQFP and QFP Package Menu TQFP Product Name I/O Pads MG87PxB02 68 MG87PxB04 108 [1] LQFP 100 128 QFP 144 176 208 208 MG87PxB06 148 MG87PxB08 188 MG87PxB10 228 MG87PxB12 268 MG87PxB14 308 MG87PxB16 348 MG87PxB18 388 MG87PxB20 428 MG87PxB22 468 MG87PxB24 508 MG87PxB26 548 MG87PxB28 588 MG87PxB30 628 MG87PxB32 668 MG87PxB34 708 MG87PxB36 748 MG87PxB38 788 MG87PxB40 828 Oki Semiconductor 13 MG87P3/87P4/87P5 --------------------------------------------------------------------------- TQFP, LQFP and QFP Package Menu (Continued) TQFP Product Name MG87PxB42 I/O Pads [1] 100 LQFP 128 144 176 QFP 208 208 868 Body Size (mm) 14x14 14x14 20x20 24x24 28x28 28x28 Lead Pitch (mm) 0.5 0.4 0.5 0.5 0.5 0.5 1. I/O Pads can be used for input, output, bi-directional, power, or ground. = Available now 14 Oki Semiconductor -------------------------------------------------------------------------- MG87P3/87P4/87P5 BGA Package Menu BGA Product Name I/O Pads [1] 256 352 420 MG87PxB02 68 MG87PxB04 108 MG87PxB06 148 MG87PxB08 188 MG87PxB10 228 MG87PxB12 268 MG87PxB14 308 MG87PxB16 348 MG87PxB18 388 MG87PxB20 428 MG87PxB22 468 MG87PxB24 508 MG87PxB26 548 MG87PxB28 588 MG87PxB30 628 MG87PxB32 668 MG87PxB34 708 MG87PxB36 748 MG87PxB38 788 MG87PxB40 828 MG87PxB42 868 560 Body Size (mm) 27x27 35x35 35x35 35x35 Ball Pitch (mm) 1.27 1.27 1.27 1.00 Ball Count 256 352 420 560 Signal I/O 231 304 352 400 Power Balls 12 16 32 80 GND Balls 13 32 36 80 1. I/O Pads can be used for input, output, bi-directional, power, or ground. = Available now Oki Semiconductor 15 MG87P3/87P4/87P5 --------------------------------------------------------------------------- NOTES: 16 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 2002 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki. Oki Semiconductor Oki REGIONAL SALES OFFICES Silicon Solutions Northwest Area Southwest Area 785 N. Mary Avenue Sunnyvale, CA 94085 Tel: 408/720-8940 Fax:408/720-8965 San Diego, CA Tel: 760/214-6512 760/214-6414 Fax:408/737-6568 408/737-6567 Northeast Area South Central Area Shattuck Office Center 138 River Road Andover, MA 01810 Tel: 978/688-8687 Fax:978/688-8896 Park Creek II 2007 N. Collins Blvd., Suite 305 Richardson, TX 75080 Tel: 972/238-5450 Fax:972/238-0268 Oki Web Site: http://www.okisemi.com/us Oki Oki Stock Stock No: No: 320283-002 Corporate Headquarters 785 N. Mary Avenue Sunnyvale, CA 94085-2909 Tel: 408/720-1900 Fax:408/720-1918