MG87P3B16 - OKI Electronic Components

MG87P3/87P4/87P5

0.25µm Standard Cell

August 2002

OKI ASIC PRODUCTS

D

ATA

S

HEET

Oki Semiconductor

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CONTENTS

Description ................................................................................................................................................................1

Features .....................................................................................................................................................................1

Array Architecture ...................................................................................................................................................2

MG87P3/87P4/87P5 SC Layout Methodology .............................................................................................3

Electrical Characteristics .........................................................................................................................................5

Macro Library ...........................................................................................................................................................7

Macrocells for Driving Clock Trees ................................................................................................................8

OKI Advanced Design Center Cad Tools .............................................................................................................9

Design Process .................................................................................................................................................10

Automatic Test Pattern Generation ..............................................................................................................11

Floorplanning Design Flow ...........................................................................................................................11

IEEE JTAG Boundary Scan .............................................................................................................................13

Package Options .....................................................................................................................................................13

1Oki Semiconductor

MG87P3/87P4/87P5

0.25µm Standard Cell

DESCRIPTION

Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in Standard Cell (SC)

architectures. The SC-based MG87P3/87P4/87P5 series uses 0.25µm drawn (0.18µm L-effective) CMOS

technology. The MG87P3/87P4/87P5 series uses three, four and five metal, respectively. The semicon-

ductor process is adapted from Oki’s production-proven 64Mbit DRAM manufacturing process.

The 0.25µm SC family provides significant performance, density, and power improvement over previous

0.25µm SOG/EA technologies. The Cell library is optimized for synthesis-based design and is designed

for low power and high speed by improving transistor architecture. The 0.25µm SC Cell library structure

provides 5 to 10% less power and 18% faster than previous 0.25µm SOG/EA technologies. The 0.25µm

SC family operates using 2.5-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal

MG87P3/87P4/87P5 series contains 21 array bases, offering up to 868 I/O pads and over 5.5M raw gates.

These SC sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin

QFPs (TQFPs), plastic ball grid array (PBGA), and metal ball grid array (MBGA) packages.

Oki uses the Artisan Components memory compiler for SC designs. As such, the MG87P3/87P4/87P5

series is suited for memory-intensive ASICs and high volume designs where fine tuning of package size

produces significant cost or real-estate savings.

FEATURES

• 0.25µm drawn 3-, 4-, and 5-layer metal CMOS

• Optimized 2.5-V core

• Optimized 3-V I/O

• Optimized 5-V Tolerant I/O

• 48-ps typical gate propagation delay (for a 4x-

drive inverter gate with a fanout of 2 and 0 mm

of wire, operating at 2.5 V)

• Over 5.5M raw gates and 868 I/O pads using

60µ staggered I/O

• User-configurable I/O with VSS, VDD, TTL,

3-state, and 1- to 24-mA options

• Slew-rate-controlled outputs for low-radiated

noise

• Clock tree cells which reduces the maximum

skew for clock signals

• Low power design method

• Low 0.2µW/MHz/gate power dissipation

• User-configurable single- and dual-port

memories

• Specialized IP cores and macrocells including

32-bit ARM7TDMI CPU, phase-locked loop

(PLL), and peripheral component interconnect

(PCI) cells

• Floorplanning for front-end simulation, back-

end layout controls, and link to synthesis

• Joint Test Action Group (JTAG) boundary scan

and scan path Automatic Test Pattern

Generation (ATPG)

• Built-in Self Test (BIST) for memory testing

• Support for popular CAE systems including

Cadence, Model Technology, Inc. (MTI), and

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ARRAY ARCHITECTURE

The primary components of a 0.25µm MG87P3/87P4/87P5 circuit include:

• I/O base cells

• 60µm pad pitch

• Configurable I/O pads for V

DD

, V

SS

, or I/O (optimized 3-V I/O)

•V

DD

and V

SS

pads dedicated to wafer probing

• Separate power bus for output buffers

• Separate power bus for internal core logic and input buffers

• Core base cells containing N-channel and P-channel pairs, arranged in column of gates

• Isolated gate structure for reduced input capacitance and increased routing flexibility

• Innovative 4-transistor core cell architecture, licensed from In-Chip Systems, Inc

Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads

per corner. The arrays also have separate power rings for the internal core functions (V

DDC

and V

SSC

)

and output drive transistors (V

DDO

and V

SSO

).

MG87P3/87P4/87P5 Family Listing

SC Base Array No of Pads

MG87P3 Family 3LM Usable

Gate

MG87P4 Family 4LM Usable

Gate

MG87P5 Family 5LM Usable

Gate

MG87PxB02 68 22,000 24,000 24,000

MG87PxB04 108 63,000 72,000 72,000

MG87PxB06 148 117,000 144,000 144,000

MG87PxB08 188 184,000 241,000 243,000

MG87PxB10 228 259,000 344,000 367,000

MG87PxB12 268 342,000 456,000 515,000

MG87PxB14 308 428,000 574,000 676,000

MG87PxB16 348 524,000 702,000 824,000

MG87PxB18 388 633,000 844,000 997,000

MG87PxB20 428 717,000 976,000 1,135,000

MG87PxB22 468 810,000 1,086,000 1,277,000

MG87PxB24 508 938,000 1,225,000 1,450,000

MG87PxB26 548 1,072,000 1,382,000 1,621,000

MG87PxB28 588 1,211,000 1,542,000 1,817,000

MG87PxB30 628 1,354,000 1,700,000 2,016,000

MG87PxB32 668 1,499,000 1,857,000 2,214,000

MG87PxB34 708 1,648,000 2,010,000 2,412,000

MG87PxB36 748 1,798,000 2,158,000 2,607,000

MG87PxB38 788 1,949,000 2,299,000 2,799,000

MG87PxB40 828 2,100,000 2,432,000 2,985,000

MG87PxB42 868 2,250,000 2,554,000 3,162,000

3Oki Semiconductor

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MG87P3/87P4/87P5 SC Layout Methodology

The procedure to design, place, and route a CSA follows.

1. Select suitable base array frame from the available predefined sizes. To select an array size:

- Identify macrocell functions required and minimum array size to hold macrocell functions.

- Add together all the area occupied by the required random logic and macrocells and select

the optimum array.

2. Make a floor plan for the design’s megacells.

- Oki Design Center engineers verify the master slice and review simulation.

- Oki Design Center or customer engineers floorplan the array using Oki’s supported floor-

planner or Cadence DP3 and customer performance specifications.

Core library cell

Separate power bus (VDDO, VSSO) over I/O cell

for output buffers (2nd metal/3rd metal)

VDD, VSS pads (4) in each

corner for wafer probing only

Configurable I/O pads

for VDD, VSS, or I/O

Separate power bus (VDDC, VSSC) for

internal core logic (2nd metal/3rd metal)

I/O base cells

1, 2, 3, 4, or 5 layer

metal

interconnection in

core area

Figure 1. MG87P5 Array Architecture

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Figure 2

shows an array base after placement of the optimized memory macrocells.

3. Place and route logic into the array transistors.

- Oki Design Center engineers use layout software and customer performance specifications

to connect the random logic and optimized memory macrocells.

Figure 3

marks the area in which placement and routing is performed with cross hatching.

Figure 2. Optimized Memory Macrocell Floor Plan

Mega macrocells

High-density RAM

Figure 3. Random Logic Place and Route

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ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (V

SS

= 0 V, T

J

= 25°C)

[1]

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be

restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Parameter Symbol Rated Value Unit

Power supply voltage V

DD

Core (2.5 V) -0.3 to +3.6 V

V

DD

I/O (3.3 V) -0.3 to +4.6

Input voltage (Input Buffer) V

I

-0.3 to V

DDIO

+0.3

Output voltage (Output Buffer) V

O

-0.3 to V

DDIO

+0.3

Input current (Input Buffer) I

I

-10 to +10 mA

Output current per I/O (Output Buffer) I

O

-24 to +24

Storage temperature T

STG

-65 to +150 °C

Recommended Operating Conditions (V

SS

= 0 V)

Parameter Symbol Rated Value Unit

Power supply voltage V

DD

Core (2.5 V) +2.25 to +2.75 V

V

DD

I/O (3.3 V) +3.0 to +3.6

Junction temperature T

j

-40 to +85 °C

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DC Characteristics (V

DD

Core = 2.25 to 2.75 V, V

DDI/O

= 3.0 to 3.6 V, V

SS

= 0 V, T

j

= -40° to +85°C)

Parameter Symbol Conditions

Rated Value

UnitMin. Typ.

[1]

1. V

DDCORE

= 2.5 V, V

DDIO

= 3.3 V, and T

j

= 25°C on a typical process.

Max.

High-level input voltage V

IH

TTL input (normal), V

DD

= V

DD

I/O

2.0 – V

DDIO

+0.3

V

Low-level input voltage V

IL

TTL input (normal) -0.0 – 0.8

TTL- level Schmitt

Trigger input buffer

Threshold voltage

V

t+

TTL input – 1.5 2.0

V

t-

0.7 1.0 –

∆

V

t

V

t+

- Vt- 0.4 0.5 –

High-level output voltage (Normal buffer) V

OH

I

OH

= -100 µA V

DDIO

-0.2 – –

I

OH

= -1, -2, -4, -6, -8, -12, -24 mA

2.4 – –

Low-level output voltage (Normal buffer) V

OL

I

OL

= 100

µ

A – – 0.2

I

OL

= 1, 2, 4, 6, 8, 12, 24 mA – – 0.4

High-level input current (Normal buffer) I

IH

V

IH

= V

DDIO

––10

µA

V

IH

= V

DD

(50-k

Ω

pull-down) 10 66 200

Low-level input current (Normal buffer) I

IL

V

IL

= V

SS

-10 –

V

IL

= V

SS

(50-k

Ω

pull-up) -200 -66 -10

V

IL

= V

SS

(3-k

Ω

pull-up) -3.3 -1.1 -0.3 mA

3-state output leakage current

(Normal input buffer)

I

OZH

V

OH

= V

DD

–10

µA

V

OH

= V

DD

(50-k

Ω

pull-down) 10 66 200

I

OZL

V

OL

= V

SS

-10 –

V

OL

= V

SS

(50-k

Ω

pull-up) -200 -66 -10

V

OL

= V

SS

(3-k

Ω

pull-up) -3.3 -1.1 -0.3 mA

Stand-by current

[2]

2. RAM/ROM should be in powerdown mode.

I

DDQ

Output open, V

IH

= V

DDIO

, V

IL

= V

SS

Design Dependent µA

7Oki Semiconductor

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MACRO LIBRARY

Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard

macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following

figure illustrates the main classes of macrocells and macrofunctions available.

AC Characteristics (Core VDD = 2.5 V, VSS = 0 V, Tj = 25°C)

Parameter Driving Type Conditions [1] [2]

1. Input transition time in 0.15 ns / 2.5 V.

2. Typical condition is VDDCORE = 2.5 V, VDDIO = 3.3 V and Tj = 25 oC for a typical process.

Rated Value [3]

3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.

Unit

Internal gate

propagation delay

Inverter 1X

F/O = 2, L = 0 mm

VDD = 2.5 V

0.082

ns

2X 0.065

4X 0.048

2-input NAND 1X 0.097

2X 0.078

2-input NOR 1X 0.096

2X 0.075

Inverter 1X

F/O = 2, L =

standard wire length

VDD = 2.5 V

0.296

2X 0.179

4X 0.109

2-input NAND 1X 0.340

2X 0.205

2-input NOR 1X 0.304

2X 0.186

Toggle frequency F/O = 1, L = 0 mm 1422 MHz

AC Characteristics (I/O VDD = 3.3 V, VSS = 0 V, Tj = 25°C)

Parameter Conditions [1] [2]

1. Input transition time in 0.15 ns / 2.5 V.

2. Typical condition is VDDCORE = 2.5 V, VDDIO = 3.3 V and Tj = 25 oC for a typical process.

Rated Value [3]

3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.

Unit

Input buffer propagation delay F/O = 2, L = standard wire length 0.311 ns

Output buffer

propagation delay

Push-pull

Normal output buffer

4 mA CL = 20 pF 1.783 ns

8 mA CL = 50 pF 2.011 ns

12mA CL = 100 pF 2.562 ns

Output buffer

transition time [4]

4. Output rising and falling times are both specified over a 10 to 90% range.

Push-pull

Normal output buffer

12 mA CL = 100 pF 3.325 (r) ns

12 mA CL = 100 pF 3.043 (f) ns

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Macrocells for Driving Clock Trees

Oki offers the Envisia™ clock-tree clock tree generator (CT-Gen). The CT-Gen generates post placement

buffered clock trees that help minimize problems associated with clock skew. CT-Gen optimizes the fol-

lowing when it generates clock trees:

• Maximum load, maximum transition, wire self-heat, and hot electron constraints

• Maximum insertion delay

• Maximum skew

• Clock tree size (if the above constraints are met)

• Minimum insertion delay (satisfied by padding the root)

Macro Library

Macrocells

Basic Macrocells

with Scan Test

Clock Tree Driver

Macrocells

3-V Output

Macrocells

MSI Macrocells

Mega/Special

Macrocells [1]

3-V

Input Macrocells

3-V

Bi-Directional

Macrocells

Oscillator

Macrocells

Memory

Macrocells

Macrofunctions

Examples

NANDs

NORs

EXORs

Latches

Flip-Flops

3-State Outputs

Push-Pull Outputs

Counters

Shift Registers

ARM7TDMI

PLL

Inputs

Inputs with Pull-Ups

Gated Oscillators

Open Drain Outputs

Slew Rate Control Outputs

PCI Outputs

Inputs with Pull-Downs

I/O

PCI I/O

I/O with Pull-Downs

I/O with Pull-Ups

SOG RAMs:

Single-Port RAMs

Dual-Port RAMs

MSI

Macrofunctions

Flip-Flops

Combinational Logic

[1] Under development

Optimized Diffused RAMs:

Single-Port RAMs

Dual-Port RAMs

4-Bit Register/Latches

Figure 4. Oki Macrocell and Macrofunction Library

9Oki Semiconductor

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OKI ADVANCED DESIGN CENTER CAD TOOLS

Oki’s advanced design center CAD tools include support for the following:

• Floorplanning for front-end simulation and back-end layout control

• Clock tree structures improve first-time silicon success by eliminating clock skew problems

• JTAG Boundary scan support

• Power calculation which predicts circuit power under simulation conditions to accurately model

package requirements

Vendor Platform Operating System [1]

1. Contact Oki Application Engineering for current software versions.

Vendor Software/Revision [1] Description

Cadence Sun® [2]

2. Sun or Sun-compatible.

Solaris

Ambit Buildgates

NC-Verilog™

Verilog XL

Design Synthesis

Design Simulation

Syntest Sun® [2] Solaris Turbo Fault Fault Simulation

Synopsys Sun® [2] Solaris

Design Compiler Ultra +

Tetramax/ATPG

Primetime

DFT Compiler/Test Compiler

RTL Analyzer

VCS

Design synthesis

Test Synthesis

Static Timing Analysis (STA)

Test synthesis

RTL check

Design Simulation

Model

Technology Inc.

(MTI)

Sun® [2]

NT

Solaris

WinNT4.0

MTI-VHDL

MTI-Verilog

Design Simulation

Oki Sun® [2] Solaris Floorplanner Floor planning

Verplex Sun® [2] Solaris Conformal Formal Verification

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Design Process

The following figure illustrates the overall IC design process, also indicating the three main interface

points between external design houses and Oki ASIC Application Engineering.

Floorplanning

Scan Insertion (Optional)

CDC [1]

Functional Test Vectors

VHDL/HDL Description

Test Vector Conversion

(Oki TPL [3])

Netlist Conversion

(EDIF 200)

TDC [2]

Pre-Layout Simulation

Layout / Timing Driven

Layout (optional) [6] Automatic Test

Pattern Generation

Static Timing Analysis

Post-Layout Simulation

Manufacturing

Prototype

Test Program

Conversion

Level 1 [4]

Level 2

Level 2.5 [4]

Level 3 [4]

CAE Front-End

Oki Interface

[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules

[2] Oki’s Test Data Check program (TDC) verifies test vector rules

[3] Oki’s Test Pattern Language (TPL)

[4] Alternate Customer-Oki design interfaces available in addition to standard level 2

[5] Standard design process includes fault simulation

[6] Requires Synopsys timing script for Oki timing driven layout

Gate-Level Simulation

Floorplanning

Synthesis / Power Synthesis

Fault Simulation [5]

Figure 5. Oki’s Design Process

Synopsys Timing Script

(optional)

Formal Verification

Verification (Design Rule

Check/Formal Verification)

11Oki Semiconductor

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Automatic Test Pattern Generation

Oki’s 0.25µm ASIC technologies support ATPG using full scan-path design techniques, including the fol-

lowing:

• Increases fault coverage ≥ 95%

• Uses Synopsys Test Compiler and Tetramax

• Automatically inserts scan structures

• Connects scan chains

• Traces and reports scan chains

• Checks for rule violations

• Generates complete fault reports

• Allows multiple scan chains

• Supports vector compaction

ATPG methodology is described in detail in Oki’s Scan Path Application Note.

Floorplanning Design Flow

Oki offers the floorplanning tool (OKI FP) for high-density ASIC design. The three main purposes for

Oki’s floorplanning tool is to:

• Ensure conformance of critical circuit performance specifications

• Shorten overall design TAT

• Hierarchical Layout

In a traditional design approach with synthesis tools, timing violations after pre layout simulation are

fixed by manual editing of the net list. This process is difficult and time consuming. Also, there is no

physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using

predicted interconnection delay due to wire length. Synthesis tools may therefore create over-optimized

result

Floorplanning allows designers to control parasitic capacitance in a circuit by participating in the physi-

cal design process. Designers can partition their ASIC circuit in the most efficient hierarchical manner,

and/or specify the exact placement of critical timing paths to guarantee high-speed performance.

Floorplanning also allows the reduction of layout iterations, minimizing a design ís overall TAT. As par-

asitic capacitance dominates a circuits timing in sub-micron technologies, an accurate capacitance esti-

mation is crucial for accurate pre-layout timing simulation. Quite often, designers have to iterate the

Scan Data In

Scan Select

D

C

SD

SS

Q

QN

D

C

SD

SS

A B

Combinational Logic

FD1AS FD1AS

Scan Data OutQ

QN

Figure 6. Full Scan Path Conﬁguration

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circuit layout because unexpected post-layout capacitance causes unacceptable circuit performance.

More information on OKI’s floorplanning capabilities is available in Oki’s Application Note, Using Oki’s

Floorplanner: Standalone Operation and Links to Synopsys.

Figure 7. Design Flow

HDL Entry

Synthesis (Initial)

Floor Plan (1)

Chip Level

Netlist (1)

Constraints

RC*

Chip Level

Netlist (2)

Synthesis (Detail)

Floor Plan (2)

Delay Calculation

STA

Met Spec?

RC* DEF

SDF

NO

YES

Chip-level Layout

Delay Calculation

STA

Met Spec?

DSPF

SDF

Block level

Netlist

Block-level Layout

Delay Calculation

Block level STA

DSPF

SDF

Block Level Optimization (Option)

NO

Sign Off RC* - Supports SPEF and DSPF

13Oki Semiconductor

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IEEE JTAG Boundary Scan

Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from

incorporating boundary-scan logic into a design include:

• Improved chip-level and board-level testing and failure diagnostic capabilities

• Support for testing of components with limited probe access

• Easy-to-maintain testability and system self-test capability with on-board software

• Capability to fully isolate and test components on the scan path

• Built-in test logic that can be activated and monitored

• An optional Boundary Scan Identification (ID) Register

Oki’s boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki sup-

ports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technolo-

gies. Either the customer or Oki can perform boundary-scan insertion. More information is available in

Oki’s JTAG Boundary Scan Application Note. (Contact the Oki Application Engineering Department for

interface options.)

PACKAGE OPTIONS

TQFP, LQFP and QFP Package Menu

Product Name I/O Pads [1]

TQFP LQFP QFP

100 128 144 176 208 208

MG87PxB02 68

MG87PxB04 108

MG87PxB06 148 ●●

MG87PxB08 188 ●●

MG87PxB10 228 ●●●●●●

MG87PxB12 268 ●●●●●●

MG87PxB14 308 ●●●●●●

MG87PxB16 348 ●●●●●

MG87PxB18 388 ●●●●●

MG87PxB20 428 ●●●

MG87PxB22 468 ●●●●

MG87PxB24 508 ●●●●

MG87PxB26 548 ●●●●

MG87PxB28 588 ●●●

MG87PxB30 628 ●●●

MG87PxB32 668 ●●●

MG87PxB34 708 ●●●

MG87PxB36 748 ●●●

MG87PxB38 788 ●

MG87PxB40 828 ●

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MG87PxB42 868 ●

Body Size (mm) 14x14 14x14 20x20 24x24 28x28 28x28

Lead Pitch (mm) 0.5 0.4 0.5 0.5 0.5 0.5

1. I/O Pads can be used for input, output, bi-directional, power, or ground.

● = Available now

TQFP, LQFP and QFP Package Menu (Continued)

Product Name I/O Pads [1]

TQFP LQFP QFP

100 128 144 176 208 208

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BGA Package Menu

Product Name I/O Pads [1]

1. I/O Pads can be used for input, output, bi-directional, power, or ground.

● = Available now

BGA

256 352 420 560

MG87PxB02 68

MG87PxB04 108

MG87PxB06 148

MG87PxB08 188

MG87PxB10 228

MG87PxB12 268 ●

MG87PxB14 308 ●

MG87PxB16 348 ●●

MG87PxB18 388 ●●●

MG87PxB20 428 ●●●

MG87PxB22 468 ●●●

MG87PxB24 508 ●●●

MG87PxB26 548 ●●●

MG87PxB28 588 ●●●

MG87PxB30 628 ●●●

MG87PxB32 668 ●●●

MG87PxB34 708 ●●

MG87PxB36 748 ●

MG87PxB38 788 ●

MG87PxB40 828 ●●

MG87PxB42 868 ●●

Body Size (mm) 27x27 35x35 35x35 35x35

Ball Pitch (mm) 1.27 1.27 1.27 1.00

Ball Count 256 352 420 560

Signal I/O 231 304 352 400

Power Balls 12 16 32 80

GND Balls 13 32 36 80

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NOTES:

Oki Semiconductor

The information contained herein can change without notice owing to product and/or technical improvements.

Please make sure before using the product that the information you are referring to is up-to-date.

The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action

and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in

the actual circuit and assembly designs.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect,

improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited

to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with

the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a

third party's right which may result from the use thereof.

When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges,

including but not limited to operating voltage, power dissipation, and operating temperature.

The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office

automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for

use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application

where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such

applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including

life support and maintenance.

Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser

assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their

own expense, for export to another country.

Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by

Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki

Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is

granted under any patents or patent rights of Oki.

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Oki Stock No: 320283-002