fax id: 7056 1CY 74FCT1 635 00 CY74FCT163500 18-Bit Registered Transceiver Features Functional Description * 5V tolerant Inputs and Outputs * 24 mA balanced drive outputs * Low power, pin-compatible replacement for LCX, LPT, LVC, LVCH & LVT families * FCT-C speed at 4.6 ns * Power-off disable outputs permits live insertion * Edge-rate control circuitry for significantly improved noise characteristics * Typical output skew < 250 ps * ESD > 2000V * TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages * Extended commercial temperature range of -40C to +85C * VCC = 2.7V to 3.6V * Typical VOLP (ground bounce) <0.6V at VCC = 3.3V, TA= 25C The CY74FCT163500 is an 18-bit universal bus transceiver that can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. The CY74FCT163500 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce.The inputs and outputs are capable of being driven by 5.0V busses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power off disable feature enabling them to be used in applications requiring live insertion. Logic Block Diagram Pin Configuration SSOP/TSSOP Top View OEAB LEAB 1 56 2 55 GND CLKAB A1 3 54 B1 GND 4 53 GND A2 5 52 A3 6 51 B2 B3 VCC 7 50 VCC A4 49 B4 OEBA 8 A5 9 48 B5 CLKAB A6 10 47 B6 GND 11 46 GND A7 12 13 45 B7 44 B8 A9 A 10 14 43 B9 15 42 B10 A 11 16 41 B11 A 12 17 40 B12 GND 18 39 OEAB CLKBA LEBA LEAB C A8 C B1 D A1 D C C A 13 19 38 GND B13 D D A 14 20 A 15 21 37 36 B15 VCC 22 35 VCC A 16 A 17 23 34 B16 24 25 33 B17 32 GND 26 31 B18 27 30 CLKBA 28 29 GND TO 17 OTHER CHANNELS GND A 18 OEBA LEBA Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * B14 408-943-2600 June 3, 1997 CY74FCT163500 Maximum Ratings[5, 6] Pin Summary Name Description (Above which the useful life may be impaired. For user guidelines, not tested.) OEAB A-to-B Output Enable Input OEBA B-to-A Output Enable Input (Active LOW) Storage Temperature ................................ -55C to +125C -55C to +125C LEAB A-to-B Latch Enable Input Ambient Temperature with Power Applied................................................. LEBA B-to-A Latch Enable Input Supply Voltage Range......................................0.5V to +4.6V CLKAB A-to-B Clock Input (Active LOW) DC Input Voltage ................................................. -0.5V to +7.0V CLKBA B-to-A Clock Input (Active LOW) DC Output Voltage .............................................. -0.5V to +7.0V A A-to-B Data Inputs or B-to-A Three-State Outputs B B-to-A Data Inputs or A-to-B Three-State Outputs DC Output Current (Maximum Sink Current/Pin) ........................... -60 to +120 mA Power Dissipation.......................................................... 1.0W Function Table[1, 2] Inputs Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Outputs Operating Range OEAB LEAB CLKAB A B L X X X Z H H X L L Range Ambient Temperature VCC H H X H H Commercial -40C to +85C 2.7V to 3.6V H L L L H L H H H L H X B[3] H L L X B[4] Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. Z = HIGH Impedance. = HIGH-to-LOW Transition. 2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 5. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range. 6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 2 CY74FCT163500 Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions VIH Input HIGH Voltage All Inputs VIL Input LOW Voltage 4 Min. Typ.[7] 2.0 [8] VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA IIH Input HIGH Current IIL Input LOW Current IOZH Max. Unit 5.5 V 0.8 V 100 -1.2 V VCC=Max., VI=5.5V 1 A VCC=Max., VI=GND. 1 A High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V 1 A IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND 1 A IODL Output LOW Current[9] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 50 90 200 mA IODH Output HIGH Current[9] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V -36 -60 -110 mA VOH Output HIGH Voltage VCC=Min., IOH= -0.1 mA VOL Output LOW Voltage -0.7 mV VCC-0.2 VCC=3.0V, IOH= -8 mA 2.4 3.0 VCC=3.0V, IOH= -24 mA 2.0 3.0 VCC=Min., IOL= 0.1mA IOS Short Circuit IOFF Power-Off Disable VCC=Max., VOUT=GND V V 0.2 VCC=Min., IOL= 24 mA Current [9] V -60 V 0.3 0.5 -135 -240 mA 100 A Typ.[7] Max. Unit VCC=0V, VOUT4.5V Capacitance[8] (TA = +25C, f = 1.0 MHz) Parameter Description Test Conditions CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Notes: 7. Typical values are at V CC= 3.3V, TA= +25C ambient. 8. This parameter is guaranteed but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY74FCT163500 Power Supply Characteristics Parameter Description Test Conditions Typ.[7] Max. Unit ICC Quiescent Power Supply Current VCC=Max. VIN0.2V, VINVCC-0.2V 0.1 10 A ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max. VIN=VCC-0.6V[10] 2.0 30 A ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, VIN=VCC or 50% Duty Cycle, Outputs Open, VIN=GND OEAB=OEBA=VCC or GND 50 75 A/MHz IC Total Power Supply Current[12] VCC=Max., f0=10 MHz (CLKAB), f1=5 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling, OEAB=OEBA=VCC LEAB=GND VIN=VCC or VIN=GND 0.5 0.8 mA VIN=VCC-0.6V or VIN=GND 0.5 0.8 mA VCC=Max., f0=10 MHz, f1=2.5 MHz, 50% Duty Cycle, Outputs Open, Eighteen Bits Toggling, OEAB=OEBA=VCC LEAB=GND VIN=VCC or VIN=GND 2.5 3.8[13] mA VIN=VCC-0.6V or VIN=GND 2.6 4.1[13] mA Notes: 10. Per TTL driven input; all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+ICCDHNT +ICCD(f0NC /2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 NC = Number of clock inputs changing at f1 f1 = Input signal frequency = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 4 CY74FCT163500 Switching Characteristics Over the Operating Range[14,17] CY74FCT163500A Parameter Description Min. Max. CY74FCT163500C Min. 150 Max. Unit 150 MHz Fig. No.[15] fMAX CLKAB or CLKBA frequency tPLH tPHL Propagation Delay A to B or B to A 1.5 5.1 1.5 4.6 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 1.5 5.6 1.5 5.3 ns 1, 5 tPLH tPHL Propagation Delay CLKBA to A, CLKAB to B 1.5 5.6 1.5 5.3 ns 1, 5 tPZH tPZL Output Enable Time OEBA to A, OEAB to B 1.5 6.0 1.5 5.4 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA to A, OEAB to B 1.5 5.6 1.5 5.2 ns 1, 7, 8 tSU Set-Up Time, HIGH or LOW A to CLKAB, B to CLKBA 3.0 3.0 ns 9 tH Hold Time, HIGH or LOW A to CLKAB, B to CLKBA 0 0 ns 9 tSU Set-Up Time, HIGH or LOW A to LEAB, B to LEBA Clock HIGH 3.0 3.0 ns 4 Clock LOW 1.5 1.5 ns 4 tH Hold Time, HIGH or LOW A to LEAB, B to LEBA 1.5 1.5 ns 4 tW LEAB or LEBA Pulse Width HIGH 3.0 2.5 ns 5 tW CLKAB or CLKBA Pulse Width HIGH or LOW 3.0 3.0 ns 5 tSK(O) Output Skew[16] 0.5 0.5 ns Ordering Information CY74FCT163500 Speed (ns) 4.6 5.1 Ordering Code Package Name Package Type CY74FCT163500CPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT163500CPVC O56 56-Lead (300-Mil) SSOP CY74FCT163500APAC Z56 56-Lead (240-Mil) TSSOP CY74FCT163500APVC O56 56-Lead (300-Mil) SSOP Notes: 14. Minimum limits are guaranteed but not tested on Propagation Delays. 15. See "Parameter Measurement Information" in the General Information section. 16. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 17. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. Document #: 38-00624 5 Operating Range Commercial Commercial CY74FCT163500 Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.