High Performance SA eto) CMOS SRAM ) a AS7C2 561, AS7C256L1. Low power 32KX8 CMOS SRAM Advance information Features * Organization: 32,768 words x 8 bits High speed - 55/70 ns address access time - 30/35 ns output enable access time * Low power consumption - Active: 385 mW max (10 ns cycle) - Standby: 550 pW max, CMOS I/O, L version 138 pW max, CMOS I/O, LL version - Very low DC component in active power * 2.0V data retention * Ultra low power in standby mode * Equal access and cycle times Logic block diagram A Veo GND + Input buffer * Easy memory expansion with CE and OE inputs * TTL-compatible, three-state [/O * 28-pin JEDEC standard packages - 600 mil PDIP - 330 mil SOIC - 8X13.4 TSOP * 5V power supply Pin arrangement DIP TSOP SOIC &x13.4 5 B sf al > 23 2) CE AU 3 a faery ae [07 4 28 E95 On At ! 3 : e 3 a of trey ros Al 3 2S6v [28x & 6 3 2 tof Hos AQ a z . 705 ox Jog 159 Vos vi 3 Array Py : a 1 AS7C256L WES ND : z 1 BO? AS z 1262144) B : 9 @ : ES wo z K 46 4 HES von ae von \ 5 we ow aAl4 I ; =i q- 1a ? * 42 ! Column decoder Control [ We . OF. circuit _ Ik- CE AAAAAAA Tey Wil 1213 Selection guide 7C256L-55 7C256L-70 Unit Maximum address access time 55 70 ns Maximum output enable access time 30 35 ns Maximum operating current 70 70 mA Maximum CMOS standby current 100 100 BA ALLIANCE SEMICONDUCTORyee wis AS7C256L Advance information AS7C256LL i or Functional description The AS7C256L is a low power CMOS 262, 144-bit Static Random Access Mentory (SRAM) organized as 32,768 words x 8 bits. Equal address access and cycle times (tay, tac. Gy) Of $5776 os with output enable access umes (tgp) of 30/35 ns are ideal for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. When CE is HIGH the device enters standby mode. The standard AS7C256L 1s guaranteed not to exceed $50 uW, and typically requires only 300 uW Ir also offers 2.0V data retention, with maximum power consumption in this mode of 100 pW. A write cycle is accomplished by asserung chip enable (CE} and write enable (WE} LOW. Data on the input pins [/00-1/O7 1s written on the rising edge ot WE (write cycle 1) or CE fwrite cycle 2) To avoid bus contention, external devices should drive I/O pins omly after outputs have been disabled with output enable (OE) or write enable (WE) A read cycle is accomplished by asserung chip enable (CE) and output enable (OE) LOW. with write enable (WE) HIGH. The chip drives [O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, ourput drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single $V supply. The AS7C256L 1s packaged in high volume industry standard packages Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on any pin relative to GND Vv, -0.5 +7.0 v Power dissipation Ph - 1.0 WwW Storage temperature (plastic) Tag 55 +150 C Temperature under bias Thias -10 +85 C DC output current Tout - 20 mA Stresses greater than these lated under Absolute Musimum Ratings may cause permanent damage to the device This 1s a stress rating only and functional operation af the device at these or any other conditions autide those indicated in the operational sections of this specification 1s not implied. Exposure to absolute max- imum rating conditions tor extended periods may aftect relrability Truth table CE WE OF Duta Mode H X xX High Z Standby (Isp, Isp} L H H High Z Output disable L H L Dont Read L L x Din Write key X = Don't Care. 1 = LOW. H = HIGH Recommended operating conditions (T, = 0C to +70C) Parameter Symbol Min Typ Max Unit Voe 4.5 5.0 5.5 Supply voltage GND 0.0 00 00 Vv Vin 22 - Voc +0.3 Vv Input voltage Vin ~pat _ 08 v = ye min = -3 GV for pulse width less than t,.-2Advance information AS7C256L i AS7C256LL hi DC operating characteristics! (Veo = SV + 0.5V, GND = OV, T, = 0C to +70C) L versions LL versions Parameter Symbol Test conditions Min Max Min Max Unit Voc = May Input leakage current Eel cc an, - 1 - ] LA Vin = GND to Vee = VY Vv, = Output leakage current rol CE in. Veo = Max, - I - l uA Vour = GND to Vee CE= Vin. f= fmax, lec] - 70 - 70 mA . Igu = 9 mA Operating power supply current = , CE < 0.2V, f= IMHz Vy $0.2, _ is _ is | ma CCl Vie Vee - 0-24, Tou, = O MA Isp CE = Vyy. f = fax - 3 - 2 mA Standby power supply current CE > ---0.2V, f= YE Pply Ise1 CE > Vee 0.2V.f o _ 100 _ 15 BA Vig $0.2V or Vi, 2 Vec-0.2V Vv, Io, = 2.L mA, Vee = Min - 0.4 - 0.4 Vv Ourput voltage OL OL ce - Vou Ioy = -!.0 mA, Vec = Min 2.4 - 2.4 - v Capacitance? (f = 1 MHz, T, = Room temperature, Vec = 5V) Parameter Symbol Signals Test conditions Max Unit Input capacitance Cin A, CE, WE, OE Vin = OV 5 pF I/O capacitance Chap Vo Vin = Your = OV 7 pF 43SRAM AS7C256L Advance information AS7C256LL i e Key to switching waveforms L._] Rising input {1} Falling input Undefined output/dont care Read cycle3.? (Vee = SVEO.5, GND = OV, T, = 0C to ~70C) 55 -70 Parameter Symbol Min Max Min Max Unit Notes Read cycle time tre 55 - 70 - ns Address access time tag 55 - 70 - ns 3 Chip enable (CE) access time LACE 55 - 70 - ns 3 Output enable (OE) access time log 30 - 35 ~ ns Output hold from address change lon 5 - 5 - ns 5 CE LOW to output in Low Z cLz 10 - 10 - ns 4.5 CE HIGH to output in High Z tcHz 20 - 25 - ns 4,5 OE LOW to output in Low Z oz 5 - 5 ~ ns 4.5 OE HIGH to output in High Z tonz 20 - 25 - ns 4,5 Read waveform 13679 (Address controlled) tre | Address \ | ou Dout Data valid Read waveform 236.89 (CE controlled) Dou Data valid | Supply x 50% 50% Isp current 44Advance information AS7C256L de AS7C2S6LL & Write cycle (Vee = 5VEO.5V, GND = OV, T, = 0C to +70C} -55 -70 Parameter Symbol Min Max Min Max Unit Notes Write cycle time twe 58 - 70 - ns Chip enable to write end tow 55 - 60 - ns Address setup to write end tw 50 - 60 - ns Address setup time Tas 0 - 0 - ns Write pulse width twp 40 - 50 - ns Address hold from end of write lay Q - 0 - ns Data valid to write end tow 25 - 30 ~ ns Data hold time tou 0 - 0 - ns 4.5 Write enable to output in High Z lwz - 25 - 30 ns 4,5 Output active from write end low 35 - 5 - ns 4,5 Write waveform ] 144 (WE controlled) twe , law t AW i AH Address / _ twp WE q H a fas [= } tow oH D,, | Data valid |. twa, 7 | ony D, tie | [S Write waveform 2/61! (CE controlled) Address Al WE tow Da Data valid D AS7O2566- 45AS7C256L Advance information AS7C256LL j Data retention characteristics Parameter Symbol Test conditions Min Max Unit Vec for data retention Vor Veo = 2.0V 2.0 5.5 v L lec - 50 A Data retention current _CEDR __ CE 2 Vope0.2V . LL re - 10 wad Chip enable to data retention time tepr Vin 2 Vec70.2V or 0 - ns : Vin 2 0.2V Operation recovery ume te wn 5 ~ ms Data retention waveform }__. Data retention mode , ey te . a Vee A5V Vor 2 2.0V Jt ASV 'cDR R _ OOOO oo Vor + CE A Vin Vin AC test conditions ~ Output load: see Figure B. Thevenin Equivalent: except for te_z and tcyz see Figure C. 639Q ~ Input pulse tevel: GND to 3.0V. See Figure A. Dou 41 Input rise and fall times: 5 ny. See Figure A. +5V +5V Input and output timing reference levels: 1.5V puraneow? oe 18002 18002 +3.0V Dau Dout 99002 30 pF* 990Q 5 pF* *including scope and jig capacitance GND GND GND Figure A: Input waveform Figure B: Output load Figure C: Output load for toyz. tcyz Notes During V..- power-up, a pull-up resistor to Voge on CE ts required to meet ip speciticanion. I 2 This parameter ts sampled and nor 100". tested 3. For test condanons, see AC Test Conditions, Figures A, B,C. + tepz and teyy are specified with CL = SpF as in Figure C. Transition ts measured +500m trom steady-state voltage. 5 This parameter is guaranteed but not tested 6 WEis HIGH for read cycle 7 CE and OF are LOW for read cycle 8 Address valid prier to or coincident with CE wansition LOW 9 Allread cycle umings are referenced fram the last valid address to the first transitioning address 10) CE or WE must be HIGH during address transiuiens LL All write cycle timings are referenced trom the last valid address to the first transinoning address 46Advance information \ ow: AS7C256L AS7C256LL AS7C256L(L) ordering codes Package Access time Plastic DIP, 600 mil Plastic SOIC, 330 mil TSOP 8x13.4 Shaded areas indicate advance information AS7C256L(L) part numbering system AS?C 256 x XX x c L =Low 4 SRAM prefix Device number Ow power Access time LL = Very low power Package: P = PDIP 300 mil $ = SOIC 330 mil T = TSOP 8x14 Commercial temperature range, 0C ta 70 C 47