Rev. 1.7 November 2010 www.aosmd.com Page 1 of 15
AOZ1021
EZBuck™ 3A Synchronous Buck Regulator
General Description
The AOZ1021 is a synchronous high efficiency, simple
to use, 3A buck regulator. The AOZ1021 works from a
4.5V to 16V input voltage range, and provides up to 3A
of continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1021 comes in an SO-8 packages and is rated
over a -40°C to +85°C ambient temperature range.
Features
●4.5V to 16V operating input voltage range
●Synchronous rectification: 100mΩ internal high-side
switch and 20mΩ Internal low-side switch
●High efficiency: up to 95%
●Internal soft start
●1.5% initial output accuracy
●Output voltage adjustable to 0.8V
●3A continuous output current
●Fixed 500kHz PWM opera tio n
●Cycle-by-cycle current limit
●Pre-bias start-up
●Short-circuit protection
●Thermal shutdown
●Small size SO-8 package
Applications
●Point of load DC/DC conversion
●PCIe graphics cards
●Set top boxes
●DVD drives and HDD
●LCD panels
●Cable modems
●Telecom/networking/datacom equipment
Typical Application
Figure 1. 3.3V/3A Buck Regulator
LX
VIN
VIN
VOUT
FB
PGND
EN
COMP
AGND
C2, C3
22μF Ceramic
R1
R2
CC
RC
C1
22μF
Ceramic
L1 4.7μH
AOZ1021
10kΩ
Not Recommended For New Designs
Replacement Part:
AOZ3013PI (same package)
AOZ3103DI (smaller package)
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 2 of 15
Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1021AI -40°C to +85°C SO-8 RoHS
AOZ1021AIL -40°C to +85°C SO-8 Green Product
LX
LX
EN
COMP
1
2
3
4
PGND
VIN
AGND
FB
SO-8
(Top View)
8
7
6
5
Pin Number Pin Name Pin Function
1 PGND Power ground. Electrically need s to be connected to AGND.
2V
IN Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
3 AGND Reference connection for controller section. Also used as thermal connection for controller section.
Electrically needs to be connected to PGND.
4 FB The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
5 COMP External loop compensation pin.
6 EN The enable pin is active HIGH. Connect 10kΩ resistor between this pin and VIN if not used. Do not
leave it open.
7, 8 LX P W M outputs connection to inductor.
Not Recommended For New Designs
Rev. 1.7 November 2010 www.aosmd.com Page 3 of 15
AOZ1021
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Recommended Operating Conditions
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with
TA = 25°C. The value in any given application depends on the
user's specific board design.
Oscillator
AGND PGND
VIN
EN
FB
COMP
LX
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
Q1
Q2
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
0.2V
+
–
+
–
+
–
+
–
+
Frequency
Foldback
Comparator
Parameter Rating
Supply Voltage (VIN) 18V
LX to AGND -0.7V to VIN+0.3V
EN to AGND -0.3V to VIN+0.3V
FB to AGND -0.3V to 6V
COMP to AGND -0.3V to 6V
PGND to AGND -0.3V to 0.3V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2.0kV
Parameter Rating
Supply Voltage (VIN) 4.5V to 16V
Output Voltage Range 0.8V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Ther mal Resistance (ΘJA)(2)
SO-8 87°C/W
Package Ther mal Resistance (ΘJC)
SO-8 30°C/W
Package Power Dissipation (PD)
@ 25°C Ambient
SO-8 1.15W
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 4 of 15
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)
Note:
3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Units
VIN Supply Voltage 4.5 16 V
VUVLO Input Under-Voltage Lockout Threshold V IN Rising
VIN Falling
4.1
3.7 V
IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 1.6 2.5 mA
IOFF Shutdown Supply Current VEN = 0V 320µA
VFB Feedback Voltage TA = 25°C 0.788 0.8 0.812 V
Load Regulation 0.5 %
Line Regulation 1%
IFB Feedback Voltage Input Current 200 nA
ENABLE
VEN EN Input Threshold Off Threshold
On Threshold 2
0.6 V
VHYS EN Input Hysteresis 100 mV
MODULATOR
fOFrequency 350 500 600 kHz
DMAX Maximum Duty Cycle 100 %
DMIN Minimum Duty Cycle 6%
GVEA Error Amplifier Voltage Gain 500 V / V
GEA Error Amplifier T r ansconductance 200 µA / V
PROTECTION
ILIM Current Limit 3.5 5.0 A
Over-Temperature Shutdown Limit TJ Rising
TJ Falling 150
100 °C
tSS Soft Start Interval 3 5 6.5 ms
PWM OUTPUT STAGE
High-Side Switch On-Resistance VIN = 12V
VIN = 5V 97
166 130
200 mΩ
Low-Side Switch On-Resistance V IN = 12V
VIN = 5V 18
30 23
36 mΩ
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 5 of 15
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation Full Load (CCM) Operation
Startup to Full Load Short Circuit Protection
1s/div 1s/div
1ms/div 4ms/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo
2V/div
Vin
10V/div
lin
1A/div
Vo
2V/div
IL
2A/div
IL
1A/div
VLX
10V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
VLX
10V/div
Vo
2V/div
IL
2A/div
VLX
10V/div
50% to 100% Load Transient Short Circuit Recovery
100s/div 10ms/div
Vo ripple
100mV/div
lo
1A/div
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 6 of 15
Efficiency
Thermal Derating Curves
AOZ1021 Efficiency
Efficiency (V
IN
= 12V) vs. Load Current
75
80
70
65
85
90
95
5.0V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
1.2V OUTPUT
1.8V
3.3V OUTPUT
100
00.5 1.0 1.5 2.0 2.5 3.0
Load Current (A)
Efficieny (%)
AOZ1021 Efficiency
Efficiency (V
IN
= 5V) vs. Load Current
75
80
70
65
85
90
95
100
00.5 1.0 1.5 2.0 2.5 3.0
Load Current (A)
Efficieny (%)
Derating Curve at 5V/6V Input
1.2V OUTPUT
3.3V
OUTPUT
1.8V
OUTPUT
1.8V
OUTPUT
Ambient Temperature (T
A
)
Output Current (I
O
)
5
4
3
2
1
0
25 35 45 55 65 75 85
Derating Curve at 12 Input
1.2V, 1.8V, 3.3V, 5.0V OUTPUT
Ambient Temperature (T
A
)
Output Current (I
O
)
3.3
3.2
3.1
3.0
2.9
2.8
25 35 45 55 65 75 85
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 7 of 15
Detailed Description
The AOZ1021 is a current-mode, step down regulator with
integrated high-side PMOS switch and a low-side NMOS
switch. It operates from a 4.5V to 16V input volt age range
and supplies up to 3A of load current. The duty cycle
can be adjusted from 6% to 100% allowing a wide output
voltage range. Features include enable control, Power-On
Reset, input under voltage lockout, output over voltage
protection, active high power good state, fixed internal
soft-start and thermal shut down .
The AOZ1021 is available in an SO-8 package.
Enable and Soft Start
The AOZ1021 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 4ms.
The 4ms soft start time is set internally.
The EN pin of the AOZ1021 is active HIGH. Connect 10kΩ
resistor between this pin and VIN if not used. Pulling EN to
ground will disable the AOZ1021. Do not leave it open.
The voltage on the EN pin must be above 2V to enable
the AOZ1021. When voltage on the EN pin falls below
0.6V, the AOZ1021 is disabled. If an application circuit
requires the AOZ1021 to be disabled, an open drain or
open collector circuit should be used to interface to the
EN pin.
Steady-Sta te Operation
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1021 integrates an internal P-MOSFET as the
high-side switch. In ductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divid ed down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at the
PWM comparator input. If the current signal is less than
the error voltage, the internal high-side switch is on. The
inductor current flows from the inp ut through the in ductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current
is freewheeling throug h the inter nal low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1021 uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
The AOZ1021 uses a P-Channel MOSFET as the high-
side switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the high-side switch to achieve linear
regulation mode of operatio n. The minimum volt age drop
from VIN to VO is the load current x DC resistance of
MOSFET + DC resistance of buck inductor. It can be
calculated by the equation below:
where;
VO_MAX is the maximum output voltage,
VIN is the input voltage from 4.5V to 16V,
IO is the output current from 0A to 3A, and
RDS(ON) is the on resi stance of internal MOSFET, the value is
between 97mΩ and 200mΩ depe nding on input voltage and
junction temperature.
Switching Frequency
The AOZ1021 switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350kHz to 600kHz due to device
variation.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. See the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below:
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
VO (V) R1 (kΩ) R2 (kΩ)
0.8 1.0 open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.1 10
5.0 52.3 10
VO_MAX VIN IORDS ON()
×–=
VO0.8 1 R1
R2
-------
+
⎝⎠
⎜⎟
⎛⎞
×=
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 8 of 15
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
Protection Features
The AOZ1021 has multip le protection features to pr event
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for
over current pr ot ect i on . Sinc e the A OZ 1 02 1 em p loy s
peak current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be betwee n 0.4V and 2.5V inte rnally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle beca use of VO = 0V. To prevent cata-
strophic failure, a secondary current limit is designed
inside the AOZ1021. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 3.5A and 5.0A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter shuts down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shut s down the internal control circuit an d
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Application Information
The basic AOZ1021 application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input cap acitor must be conne cted to the VIN pin and
PGND pin of AOZ1021 to maintain steady input voltage
and filter out the pulsing inp ut cu rrent. The vo ltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by equa-
tion below:
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another conc er n wh en selectin g th e ca pacitor. For a
buck circuit, the RMS value of input capacitor current
can be calculated by:
if we let m equal the conversion ratio:
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 be low . It can be seen that when VO is half of VIN,
CIN is under the worst current stress. The worst current
stress on CIN is 0.5 x IO.
Figure 2. ICIN vs. Voltage Conversion Ratio
ΔVIN IO
fC
IN
×
----------------- 1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
VO
VIN
---------
××=
ICIN_RMS IOVO
VIN
---------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
VO
VIN
---------m=
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
I
CIN_RMS
(m)
I
O
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 9 of 15
For reliable operation and best performance, the input
capacitors must have cu rrent rating higher than I CIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When sele ctin g ce rami c capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor manu-
factures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
The peak inductor current is:
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requ ire m en ts.
Surface mount indu ctors in differ ent shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, ou tp ut ripp le vo ltage is deter m ine d by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capa citor is used as output
capacitor , the imp edance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR t antalu m are recommended to
be used as output capacitors.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by the
peak to peak inductor ripple current. It can be calculated
by:
Usually, the ripple current rating of the output cap acitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
tor ripple current is high, the output capacitor could be
overstressed.
ΔILVO
fL×
-----------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
ILpeak IO
ΔIL
2
--------
+=
ΔVOΔILESRCO 1
8fC
O
××
-------------------------
+
⎝⎠
⎛⎞
×=
ΔVOΔIL1
8fC
O
××
-------------------------
⎝⎠
⎛⎞
×=
ΔVOΔILESRCO
×=
ICO_RMS
ΔIL
12
----------
=
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 10 of 15
Loop Compensation
The AOZ1021 employs peak current mode control for
easy use and fast tr ansient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is the dominant pole can
be calculated by:
The zero is an ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get the desired
gain and phase. Several different types of compensation
network can be used for the AOZ1021. In most cases, a
series capacitor and resistor network connected to the
COMP pin set s the pole-zero and is adequa te for a stable
high-bandwidth control loop.
In the AOZ1021, FB pin and COMP pin are the inverting
input and the output of internal error amp lifier. A series R
and C compensation network connected to COMP
provides one pole and one zero. The pole is:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage; and
C2 is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. Th e system
crossover frequency is where con trol loop has unity gain.
The crossover is the also called the conve rter bandwid th.
Generally a higher bandwidth means faster response to
load transient. Howe ver, the bandwid th should not b e too
high because of system stability concern. When design-
ing the compensation loop, converter stability under all
line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1021 operates at a frequency range from 350kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
The strategy for choosing RC and CC is to set the
cross over frequency with RC and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate R3:
where;
where fC is desired crossover frequency . For best performance,
fC is set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is 6.68
A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. C2 can is selected by:
The above equation can be simplified to:
An easy-to-us e ap plic ation software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
fp11
2πCORL
××
-----------------------------------
=
fZ11
2πCOESRCO
××
------------------------------------------------
=
fp2GEA
2πCCGVEA
××
-------------------------------------------
=
fZ21
2πCCRC
××
-----------------------------------
=
fC40kHz=
RCfCVO
VFB
---------- 2πC2
×
GEA GCS
×
------------------------------
××=
CC1.5
2πRCfp1
××
-----------------------------------
=
CCCORL
×
RC
---------------------
=
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 11 of 15
Thermal Management and Layout
Consideration
In the AOZ1021 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low-side NMOSFET.
Current flows in the second loop when the low-side
NMOSFET is on.
In PCB layout, minimizing the two loops area redu ces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1021.
In the AOZ1021 buck regulator circuit, the major power
dissipating compo nent s ar e the AOZ1 021 and the outp ut
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
The actual junction temperature can be calculated with
power dissipation in the AOZ 1 02 1 and ther m al imp e d-
ance from junction to ambient.
The maximum junction temperature of AOZ1021 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1021 under different ambient
temperature.
The thermal performance of the AOZ1021 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1021A is a standa rd SO- 8 package. Layout tip s
are listed below for the best electric and thermal
performance. Figure 3 illustrates a PCB layout example
of the AOZ1021A.
1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper area
to the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected as close as
possible to the VIN pin and the PGN D pin.
3. A ground plane is suggested. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the current tr ace from the LX pin s to L to CO to
the PGND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
6. The LX pins are connected to internal PFET drain.
They are a low resistance thermal conduction path
and the most noisy switching node. Connect a
copper plane to the LX pins to help thermal
dissipation. This copper plane should not be too
large otherwise switching noise may be coupled to
other parts of the circuit.
7. Keep sensitive signal traces far away from the LX
pins.
Ptotal_loss VIN IIN VOIO
×–×=
Pinductor_loss IO2Rinductor 1.1××=
Tjunction Ptotal_loss Pinductor_loss
–()Θ×JA
=
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 12 of 15
Figure 3. AOZ1021A (SO-8) PCB Layout
PGND
VIN
AGND
FB
R2
C1
Cd
C2
Cc
Rc
C3
R1
L1
8
7
6
5
1
2
3
4
LX
LX
EN
COMP
Vo
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 13 of 15
Package Dimensions, SO-8L
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Dimensions in millimeters
Min.
1.35
0.10
1.25
0.31
0.17
4.80
3.80
5.80
0.25
0.40
0°
D
C
L
h x 45°
7° (4x)
b
2.20
5.74
0.80
Unit: mm
1.27
A1
A2 A
0.1
θ
Gauge Plane Seating Plane
0.25
e
8
1
E1E
Nom.
1.65
—
1.50
—
—
4.90
3.90
1.27 BSC
6.00
—
—
—
Max.
1.75
0.25
1.65
0.51
0.25
5.00
4.00
6.20
0.50
1.27
8°
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Dimensions in inches
Min.
0.053
0.004
0.049
0.012
0.007
0.189
0.150
0.228
0.010
0.016
0°
Nom.
0.065
—
0.059
—
—
0.193
0.154
0.050 BSC
0.236
—
—
—
Max.
0.069
0.010
0.065
0.020
0.010
0.197
0.157
0.244
0.020
0.050
8°
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 14 of 15
Tape and Reel Dimensions
SO-8 Carrier Tape
SO-8 Reel
SO-8 Tape
Leader/Trailer
& Orientation
Tape Size
12mm Reel Size
ø330 M
ø330.00
±0.50
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
N
ø97.00
±0.10
K0
Unit: mm
B0
G
M
W1
S
K
H
N
W
V
R
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket Leader Tape
500mm min. or
125 empty pockets
A0
P1
P2
See Note 5
See Note 3
See Note 3
Feeding Direction
P0
E2
E1
E
D0
TD1
W
13.00
±0.30
W1
17.40
±1.00
H
ø13.00
+0.50/-0.20
K
10.60 S
2.00
±0.50
G
—R
—V
—
Not Recommended For New Designs
AOZ1021
Rev. 1.7 November 2010 www.aosmd.com Page 15 of 15
Part Marking
Z1021AI
FAY Part Number Code
Assembly Lot Code
AOZ1021AI
AOZ1021AIL
Year & Week Code
WLT
Z1021AI
FAY Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
WLT
Underscore denotes Green Product
Fab & Assembly Location
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perfor m can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
Not Recommended For New Designs
