ICL7621DCBA-T - Intersil - Datasheet.Directory

FN3403.5

ICL7621

Dual, Low Power CMOS Operational

Amplifiers

The ICL761X/762X series is a family of monolithic CMOS

operational amplifiers. These devices provide the designer

with high performance operation at low supply voltages and

selectable quiescent currents. They are an ideal design tool

when ultra low input current and low power dissipation are

desired.

The basic amplifier will operate at supply voltages ranging

from ±1V to ±8V, and may be operated from a single Lithium

cell. The output swing ranges to within a few millivolts of the

supply voltages.

The quiescent supply current of these amplifiers is set to

100µA at the factory. This results in power consumption as

low as 200µW per amplifier.

Of particular significance is the extremely low (1pA) input

current, input noise current of 0.01pA/√Hz, and 1012Ω input

impedance. These features optimize performance in very

high source impedance applications.

The inputs are internally protected. Outputs are fully

protected against short circuits to ground or to either supply.

Because of the low power dissipation, junction temperature

rise and drift are quite low. Applications utilizing these

features may include stable instruments, extended life

designs, or high density packages.

Ordering Information

PART

NUMBER

PART

MARKING

TEMP.

RANGE

(°C) PACKAGE

PKG.

DWG. #

ICL7621DCPA 7621 DCPA 0 to +70 8 Ld PDIP -

D Grade - IQ = 100µA

E8.3

ICL7621DCPAZ*

(Note 2)

7621 DCPAZ 0 to +70 8 Ld PDIP -

D Grade - IQ = 100µA

E8.3

ICL7621DCBA

(Note 1)

7621 DCBA 0 to +70 8 Ld SOIC -

D Grade - IQ = 100µA

M8.15

ICL7621DCBAZ

(Notes 1, 2)

7621 DCBAZ 0 to +70 8 Ld SOIC -

D Grade - IQ = 100µA

M8.15

*Pb-free PDIPs can be used for through hole wave solder processing only.

They are not intended for use in Reflow solder processing applications.

NOTES:

Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel

specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-

free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS

compliant and compatible with both SnPb and Pb-free soldering

operations). Intersil Pb-free products are MSL classified at Pb-free

peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

Features

• Wide Operating Voltage Range . . . . . . . . . . . ±1V to ±8V

• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . .1012Ω

• Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ)

• Output Voltage Swing . . . . . . . . . . . . . . . . . . . . V+ and V-

• Available as Duals (Refer to ICL7611 for Singles)

• Low Power Replacement for Many Standard Op Amps

Applications

• Portable Instruments

• Telephone Headsets

• Hearing Aid/Microphone Amplifiers

• Meter Amplifiers

• Medical Instruments

• High Impedance Buffers

Pinouts ICL7621

(8 LD PDIP, SOIC)

TOP VIEW

OUTA

-INA

+INA

V-

V+

OUTB

-INB

+INB

Data Sheet March 4, 2010

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings Thermal Information

Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V

Differential Input Voltage (Note 3) . . . . . . . . . [(V+ +0.3) - (V- -0.3)]V

Duration of Output Short Circuit (Note 4). . . . . . . . . . . . . . Unlimited

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Thermal Resistance (Typical, Note 5) θJA (°C/W) θJC (°C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . .. -65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time.

4. The outputs may be shorted to ground or to either supply, for VSUPPLY ≤10V. Care must be taken to insure that the dissipation rating is not

exceeded.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

2FN3403.5

March 4, 2010

Electrical Specifications VSUPPLY = ±5V, Unless Otherwise Specified.

PARAMETER SYMBOL TEST CONDITIONS

TEMP.

(°C)

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

Input Offset Voltage VOS RS ≤ 100kΩ+25 - - 15 mV

Full - - 20 mV

Temperature Coefficient of VOS ΔVOS/ΔT RS ≤ 100kΩ- - 25 -µV/oC

Input Offset Current IOS +25 -0.5 30 pA

0 to +70 - - 300 pA

-55 to +125 -800 pA

Input Bias Current IBIAS +25 -1.0 50 pA

0 to +70 - - 400 pA

-55 to +125 - - 4000 pA

Common Mode Voltage Range VCMR IQ = 100µA +25 ±4.2 - - V

Output Voltage Swing VOUT IQ = 100µA, RL = 100kΩ +25 ±4.9 - - V

0 to +70 ±4.8 - - V

-55 to +125 ±4.5 - - V

Large Signal Voltage Gain AVOL VO = ±4.0V, RL = 100kΩ, IQ = 100µA +25 80 102 -dB

0 to +70 75 - - dB

-55 to +125 68 - - dB

Unity Gain Bandwidth GBW IQ = 100µA +25 -0.48 -MHz

Input Resistance RIN +25 -1012 -Ω

Common Mode Rejection Ratio CMRR RS ≤ 100kΩ , IQ = 100µA +25 70 91 -dB

Power Supply Rejection Ratio

(VSUPPLY = ±8V to ±2V)

PSRR RS ≤ 100kΩ , IQ = 100µA +25 80 86 -dB

Input Referred Noise Voltage eNRS = 100Ω, f = 1kHz +25 -100 -nV/√Hz

Input Referred Noise Current iNRS = 100Ω, f = 1kHz +25 -0.01 -pA/√Hz

Supply Current (Per Amplifier) ISUPPLY No Signal, No Load, IQ = 100µA +25 -0.1 0.25 mA

Channel Separation VO1/VO2 AV = 100 +25 -120 -dB

ICL7621

3FN3403.5

March 4, 2010

Schematic Diagram

INPUT STAGE SETTING STAGE

OUTPUT STAGE

V+

OUTPUT

V-

QN11

QN10

QN9

CFF = 9pF

CC = 33pF

QP9

QP8

QP7

QP6

6.3V

QN7

QN6

QN5

QN4

QN8

QN3

QN1 QN2

QP1 QP2

3k3k

100k

900k

QP5

QP4

QP3

+INPUT

-INPUT

V-

V+

V-

V+

TABLE OF JUMPERS IQ

ICL7621 C, E 100µA

6.3V

Slew Rate SR AV = 1, CL = 100pF, VIN = 8VP-P

IQ = 100µA, RL = 100kΩ

+25 -0.16 -V/µs

Rise Time tRVIN = 50mV, CL = 100pF,

IQ = 100µA, RL = 100kΩ

+25 - 2 - µs

Overshoot Factor OS VIN = 50mV, CL = 100pF,

IQ = 100µA, RL = 100kΩ

+25 -10 - %

NOTE:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

Electrical Specifications VSUPPLY = ±5V, Unless Otherwise Specified. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

TEMP.

(°C)

MIN

(Note 6) TYP

MAX

(Note 6) UNITS

ICL7621

4FN3403.5

March 4, 2010

Application Information

Static Protection

All devices are static protected by the use of input diodes.

However, strong static fields should be avoided, as it is

possible for the strong fields to cause degraded diode

junction characteristics, which may result in increased input

leakage currents.

Latchup Avoidance

Junction-isolated CMOS circuits employ configurations

which produce a parasitic 4-layer (PNPN) structure. The

4-layer structure has characteristics similar to an SCR, and

under certain circumstances may be triggered into a low

impedance state resulting in excessive supply current. To

avoid this condition, no voltage greater than 0.3V beyond the

supply rails may be applied to any pin. In general, the op

amp supplies must be established simultaneously with, or

before any input signals are applied. If this is not possible,

the drive circuits must limit input current flow to 2mA to

prevent latchup.

Choosing the Proper IQ

Each device in the ICL76XX family has a similar IQ setup

scheme, which allows the amplifier to be set to nominal

quiescent currents of 10µA, 100µA or 1mA. These current

settings change only very slightly over the entire supply voltage

range. The ICL7611/12 have an external IQ control terminal,

permitting user selection of each amplifiers’ quiescent current.

The ICL7621 has a fixed IQ setting of 100µA.

Output Stage and Load Driving Considerations

Each amplifiers’ quiescent current flows primarily in the

output stage. This is approximately 70% of the IQ settings.

This allows output swings to almost the supply rails for

output loads of 1MΩ, 100kΩ, and 10kΩ, using the output

stage in a highly linear class A mode. In this mode,

crossover distortion is avoided and the voltage gain is

maximized. However, the output stage can also be operated

in Class AB for higher output currents (see graphs in “Typical

Performance Curves” beginning on page 6). During the

transition from Class A to Class B operation, the output

transfer characteristic is nonlinear and the voltage gain

decreases.

Frequency Compensation

The ICL76XX are internally compensated, and are stable

for closed loop gains as low as unity with capacitive loads

up to 100pF.

Typical Applications

The user is cautioned that, due to extremely high input

impedances, care must be exercised in layout, construction,

board cleanliness, and supply filtering to avoid hum and

noise pickup.

FIGURE 1. SIMPLE FOLLOWER

ICL76XX

VIN

VOUT

RL ≥ 10kΩ

FIGURE 2. LEVEL DETECTOR

ICL76XX

VIN

VOUT

100kΩ

+5 +5

1MΩ

TO CMOS OR

LPTTL LOGIC

FIGURE 3.

VOUT

1µF

ICL76XX

NOTE: Low leakage currents allow integration times up to

several hours.

PHOTOCURRENT INTEGRATOR FIGURE 4.

1MΩ

DUTY CYCLE

V- V+

680kΩ

1MΩ

WAVEFORM GENERATOR

1/2

ICL7621 1/2

ICL7621

NOTE: Since the output range swings exactly from rail to rail,

frequency and duty cycle are virtually independent of power supply

variations.

TRIANGLE/SQUARE WAVE GENERATOR

ICL7621

5FN3403.5

March 4, 2010

FIGURE 5.

10µF

1/2

20kΩ

VIN

20kΩ

VOH

VOL

1MΩ

2.2MΩ

COMMON

10kΩ

0.5µF

1.8k = 5%

SCALE

ADJUST

SUCCEEDING

INPUT

STAGE

ICL7621

1/2

ICL7621

AVERAGING AC TO DC CONVERTER FOR A/D

CONVERTERS SUCH AS ICL7106, ICL7107,

ICL7109, ICL7116, ICL7117

FIGURE 6.

-V-

OUT

V+

-8V

+8V

TA = +125°C

BURN-IN AND LIFE TEST CIRCUIT

FIGURE 7.

INPUT

30kΩ160kΩ

0.2µF 0.2µF

0.2µF

0.2µF 0.1µF0.1µF

51kΩ100kΩ680kΩ

360kΩ

1MΩ

OUTPUT

1/2

ICL7621 1/2

ICL7621

NOTE 7 NOTE 7

NOTES:

7. Small capacitors (25pF to 50pF) may be needed for stability in some cases.

8. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4,

Passband ripple = 0.1dB.

FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER

ICL7621

6FN3403.5

March 4, 2010

Typical Performance Curves

FIGURE 8.

10k

100

SUPPLY CURRENT (µA)

0 2 4 6 810121416

SUPPLY VOLTAGE (V)

TA = +25°C

NO LOAD

NO SIGNAL

IQ = 100µA

SUPPLY CURRENT PER AMPLIFIER vs SUPPLY

VOLTAGE

FIGURE 9.

104

103

102

SUPPLY CURRENT (µA)

-50 -25 0 25 50 75 100 125

FREE-AIR TEMPERATURE (°C)

V+ - V- = 10V

NO LOAD

NO SIGNAL

IQ = 100µA

SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR

TEMPERATURE

FIGURE 10.

-50 -25 0 25 50 75 100 125

FREE-AIR TEMPERATURE (°C)

1000

100

1.0

0.1

INPUT BIAS CURRENT (pA)

VS = ±5V

INPUT BIAS CURRENT vs TEMPERATURE FIGURE 11.

-50 -25 0 25 50 75 100 125

FREE-AIR TEMPERATURE (°C)

-75

1000

100

DIFFERENTIAL VOLTAGE GAIN (kV/V)

VSUPPLY = 10V

VOUT = 8V

RL = 100kΩ

IQ = 100µA

LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN

vs FREE-AIR TEMPERATURE

FIGURE 12.

107

106

104

103

102

105

DIFFERENTIAL VOLTAGE GAIN (V/V)

0.1 1.0 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

TA = +25°C

VSUPPLY = 15V

IQ = 100µA

LARGE SIGNAL FREQUENCY RESPONSE FIGURE 13.

-50 -25 0 25 50 75 100 125

FREE-AIR TEMPERATURE (°C)

-75

105

100

COMMON MODE REJECTION RATIO (dB)

VSUPPLY = 10V

IQ = 100µA

COMMON MODE REJECTION RATIO vs FREE-AIR

TEMPERATURE

ICL7621

7FN3403.5

March 4, 2010

FIGURE 14.

100

SUPPLY VOLTAGE REJECTION RATIO (dB)

-50 -25 0 25 50 75 100 125-75

FREE-AIR TEMPERATURE (°C)

IQ = 100µA

VSUPPLY = 10V

POWER SUPPLY REJECTION RATIO vs FREE-AIR

TEMPERATURE

FIGURE 15.

600

500

400

300

200

100

EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz)

10 100 1k 10k 100k

FREQUENCY (Hz)

TA = +25°C

3V ≤ VSUPPLY ≤ 16V

EQUIVALENT INPUT NOISE VOLTAGE vs

FREQUENCY

FIGURE 16.

MAXIMUM PEAK-TO-PEAK

OUTPUT VOLTAGE (VP-P)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

VSUPPLY

= ±8V

VSUPPLY

= ±5V

VSUPPLY

= ±2V

IQ = 100µA

TA = +25°C

OUTPUT VOLTAGE vs FREQUENCY FIGURE 17.

0.01

0.1

1.0

MAXIMUM OUTPUT SINK CURRENT (mA)

0246810121416

SUPPLY VOLTAGE (V)

IQ = 100µA

OUTPUT SINK CURRENT vs SUPPLY VOLTAGE

FIGURE 18.

-2

-4

-6

INPUT AND OUTPUT VOLTAGE (V)

020406080100120

TIME (µs)

TA = +25°C, VSUPPLY = 10V

RL = 100kΩ, CL = 100pF

OUTPUT

INPUT

VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 100µA)

Typical Performance Curves (Continued)

ICL7621

8FN3403.5

March 4, 2010

ICL7621

Dual-In-Line Plastic Packages (PDIP)

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25) C AMBS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between

English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated

in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru-

sions. Mold flash or protrusions shall not exceed 0.010 inch

(0.25mm).

6. E and are measured with the leads constrained to be per-

pendicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon-

strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.

Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,

E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch

(0.76 - 1.14mm).

-C-

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N8 89

Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN3403.5

March 4, 2010

ICL7621

Small Outline Plastic Packages (SOIC)

INDEX

AREA

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05