N-Channel JFET Switch
J111 - J113 / SST111 – SST113
FEATURES
••Low Cost
••Automa ted Inse rtion Package
••Low I nsertion Lo ss
••No Of fset or Error Vo ltag e Gener at ed By Cl ose d Sw itch
-Purely R e s is ti v e
-High Isolation Res istance From Driver
••Fast Switching
••Sho rt Sam ple an d Hol d Ape rtur e T ime
APPLICATIONS
••An a lo g Sw it ch e s
••Choppers
••Commutators
ABSOLUTE M AXIM UM R A T INGS
(TA = 25oC unless o th erw ise specified)
Gate- Dr ain or Gate -So urce Voltage . . . . . . . . . . . . . . . . -3 5 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Stor age Temper at ure R a nge. . . . . . . . . . . . . -55oC t o +150oC
Oper at ing Temper atur e Ra nge . . . . . . . . . . . -55oC to +135oC
Lead Tem peratu re (So ld er ing, 10se c). . . . . . . . . . . . . +300oC
Power Dissipat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . 3. 3mW/oC
NOTE: Stresses above those listed under "Absolute Maxi mum
Ratings " may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating con ditions for extended per i ods may affect device reliability.
ORDERING INFORMAT ION
Part Package Temperature Range
J111-113 Plastic TO-92 -55oC to +135oC
SST111-113 Plastic SOT-23 -55oC to +135oC
For Sor ted Chips in Car rie rs see 2N4391 series.
LLC
PIN CONFIGUR ATIO N
5001
ELECTRICA L CHARACTERI STIC S (TA = 2 5oC unle ss otherwise sp ecif ie d)
SYMBOL PARAMETER 111 112 113 UNITS TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
IGSSR Gate Reverse Current (Note 1) -1 -1 -1 nA VDS = 0V, VGS = -15V
VGS(off) Gate Source Cutoff Voltage -3 -10 -1 -5 -0.5 -3 VVDS = 5V, ID = 1µA
BVGSS Gate Source Breakdown Volta ge -3 5 -35 -35 VDS = 0V, IG = -1µA
IDSS Drain Saturation Current (Note 2) 20 5 2 mA VDS = 15V, VGS = 0V
ID(off) Drain Cutoff Curren t (Note 1) 1 1 1 nA VDS = 5V, VGS = -10V
rDS(on) Drai n Source ON Resistance 30 50 100 ΩVDS = 0 .1V, VGS = 0V
Cdg(off) Drain Gate OFF Capacitance 5 5 5
pF
VDS = 0,
VGS = -10V
(Note 3) f = 1 MHz
Csg(off) Source Gate OFF Capacitance 5 5 5
Cdg(on)
+ Csg(on) Drain Gate Plus Source Gate ON
Capacitance 28 28 28 VDS = VGS = 0
(Note 3)
td(on) Turn On Delay Time 7 7 7
ns
Switchin g Time Test
Conditions (Note 3)
J111 J112 J113
VDD 10V 10V 10V
VGS(off)-12V -7V -5V
RL0.8kΩ1.6kΩ3.2kΩ
trRise T ime 6 6 6
td(off) T urn Off Delay Time 20 20 20
tfF all Time 15 15 15
NOTES: 1. A pproxi mately doubles for every 10oC increas e i n T A.
2. Pulse test duration 300µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.
SOT-23
G
S
D
TO-92
SG
DPRO DUCT MARKING (SOT-23)
SST111 111
SST112 112
SST113 113
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539. 510-656-2900 PHONE, 510-651-1076 FAX DS039 REV A
