1
LTC3440
3440fb
■
Palmtop Computers
■
Handheld Instruments
■
MP3 Players
■
Digital Cameras
Micropower Synchronous
Buck-Boost DC/DC Converter
■
Single Inductor
■
Fixed Frequency Operation with Battery Voltages
Above, Below or Equal to the Output
■
Synchronous Rectification: Up to 96% Efficiency
■
25μA Quiescent Current in Burst Mode
®
Operation
■
Up to 600mA Continuous Output Current
■
No Schottky Diodes Required (V
OUT
< 4.3V)
■
V
OUT
Disconnected from V
IN
During Shutdown
■
2.5V to 5.5V Input and Output Range
■
Programmable Oscillator Frequency
from 300kHz to 2MHz
■
Synchronizable Oscillator
■
Burst Mode Enable Control
■
<1μA Shutdown Current
■
Small Thermally Enhanced 10-Pin MSOP and
(3mm
×
3mm) DFN Packages
The LTC
®
3440 is a high efficiency, fixed frequency, Buck-
Boost DC/DC converter that operates from input voltages
above, below or equal to the output voltage. The topology
incorporated in the IC provides a continuous transfer
function through all operating modes, making the product
ideal for single lithium-ion, multicell alkaline or NiMH
applications where the output voltage is within the battery
voltage range.
The device includes two 0.19Ω N-channel MOSFET
switches and two 0.22Ω P-channel switches. Switching
frequencies up to 2MHz are programmed with an external
resistor and the oscillator can be synchronized to an
external clock. Quiescent current is only 25μA in Burst
Mode operation, maximizing battery life in portable appli-
cations. Burst Mode operation is user controlled and can
be enabled by driving the MODE/SYNC pin high. If the
MODE/SYNC pin has either a clock or is driven low, then
fixed frequency switching is enabled.
Other features include a 1μA shutdown, soft-start con-
trol, thermal shutdown and current limit. The LTC3440 is
available in the 10-pin thermally enhanced MSOP and
(3mm × 3mm) DFN packages.
Burst Mode is a registered trademark of Linear Technology Corporation.
Protected by U.S. Patents including 6404251, 6166527.
Efficiency vs VIN
Li-Ion to 3.3V at 600mA Buck-Boost Converter
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
SW1
VIN
SHDN/SS
MODE/SYNC
RT
SW2
VOUT
FB
VC
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
10μH
R1
340k
R2
200k
R3
15k
3440 TA01
RT
60.4k
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
L1: SUMIDA CDRH6D38-100
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C1
10μF
Li-Ion
VIN = 2.7V TO 4.2V
*
+
C5 1.5nF C2
22μF
VOUT
3.3V
600mA
VIN (V)
2.5
EFFICIENCY (%)
3.0 3.5 4.0 4.5
3440 TA02
5.0
100
98
96
94
92
90
88
86
84
82
80
5.5
VOUT = 3.3V
IOUT = 100mA
fOSC = 1MHz
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
2
LTC3440
3440fb
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Start-Up Voltage ●2.4 2.5 V
Input Operating Range ●2.5 5.5 V
Output Voltage Adjust Range ●2.5 5.5 V
Feedback Voltage ●1.196 1.22 1.244 V
Feedback Input Current V
FB
= 1.22V 1 50 nA
Quiescent Current, Burst Mode Operation V
C
= 0V, MODE/SYNC = 3V (Note 3) 25 40 μA
Quiescent Current, Shutdown SHDN = 0V, Not Including Switch Leakage 0.1 1 μA
Quiescent Current, Active V
C
= 0V, MODE/SYNC = 0V (Note 3) 600 1000 μA
NMOS Switch Leakage Switches B and C 0.1 5 μA
PMOS Switch Leakage Switches A and D 0.1 10 μA
NMOS Switch On Resistance Switches B and C 0.19 Ω
PMOS Switch On Resistance Switches A and D 0.22 Ω
Input Current Limit ●1A
Maximum Duty Cycle Boost (% Switch C On) ●55 75 %
Buck (% Switch A On) ●100 %
Minimum Duty Cycle ●0%
Frequency Accuracy ●0.8 1 1.2 MHz
MODE/SYNC Threshold 0.4 2 V
MODE/SYNC Input Current V
MODE/SYNC
= 5.5V 0.01 1 μA
(Note 1)
V
IN
, V
OUT
Voltage........................................ –0.3V to 6V
SW1, SW2 Voltage ..................................... –0.3V to 6V
V
C
, R
T
, FB, SHDN/SS,
MODE/SYNC Voltage .................................. –0.3V to 6V
ORDER PART
NUMBER
LTC3440EDD
T
JMAX
= 125°C,
θ
JA
= 130°C/ W 1 LAYER BOARD
θ
JA
= 100°C/ W 4 LAYER BOARD
θ
JC
= 45°C/ W
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = VOUT = 3.6V, RT = 60k, unless otherwise noted.
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
DD
PART MARKING
LBKT
1
2
3
4
5
RT
MODE/SYNC
SW1
SW2
GND
10
9
8
7
6
VC
FB
SHDN/SS
VIN
VOUT
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Operating Temperature Range (Note 2) .. –40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC3440EMS
MS
PART MARKING
LTNP
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
10
9
6
7
8
4
5
3
2
1V
C
FB
SHDN/SS
V
IN
V
OUT
R
T
MODE/SYNC
SW1
SW2
GND
11
T
JMAX
= 125°C, θ
JA
= 43°C/ W, θ
JC
= 3°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC3440
3440fb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Li-Ion to 3.3V Efficiency
(fOSC = 300kHz)
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
80
50
70
60
40
0.1 10 100 1000
3440 G02
1
Burst Mode
OPERATION
VIN = 3.3V
VIN = 2.5V
POWER LOSS (mW)
VIN = 4.2V
0.1
1
10
100
1000
fOSC = 1MHz
VIN = 3.3V
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
80
50
70
60
40
0.1 10 100 1000
3440 G03
1
Burst Mode
OPERATION
V
IN
= 2.5V
V
IN
= 3.3V
f
OSC
= 2MHz
V
IN
= 4.2V
Li-Ion to 3.3V Efficiency,
Power Loss (fOSC = 1MHz)
Li-Ion to 3.3V Efficiency
(fOSC = 2MHz)
Switch Pins During Buck/Boost
Switch Pins on the Edge of
Buck/Boost and Approaching Boost
SW1
2V/DIV
SW2
2V/DIV
V
IN
= 3.78V 50ns/DIV 3440 G04
V
OUT
= 3.3V
I
OUT
= 250mA
SW1
2V/DIV
SW2
2V/DIV
V
IN
= 3.42V 50ns/DIV 3440 G05
V
OUT
= 3.3V
I
OUT
= 250mA
Switch Pins on the Edge of
Buck/Boost and Approaching Buck
SW1
2V/DIV
SW2
2V/DIV
V
IN
= 4.15V 50ns/DIV 3440 G06
V
OUT
= 3.3V
I
OUT
= 250mA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: The LTC3440E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: Current measurements are performed when the outputs are not
switching.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amp AVOL 90 dB
Error Amp Source Current 15 μA
Error Amp Sink Current 380 μA
SHDN/SS Threshold When IC is Enabled ●0.4 1 1.5 V
When EA is at Maximum Boost Duty Cycle 2.2 V
SHDN/SS Input Current V
SHDN
= 5.5V 0.01 1 μA
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = VOUT = 3.6V, RT = 60k, unless otherwise noted.
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
80
50
70
60
40
0.1 10 100 1000
3440 G01
1
Burst Mode
OPERATION
VIN = 2.5V VIN = 3.3V
fOSC = 300kHz
VIN = 4.2V
4
LTC3440
3440fb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Active Quiescent Current Burst Mode Quiescent Current Error Amp Source Current
TEMPERATURE (°C)
–55
400
VIN + VOUT CURRENT (μA)
450
500
550
–25 5 35 65
3440 G10
95 125
VIN = VOUT = 3.6V
TEMPERATURE (°C)
–55
10
V
IN
+ V
OUT
CURRENT (μA)
20
30
40
–25 5 35 65
3440 G11
95 125
V
IN
= V
OUT
= 3.6V
TEMPERATURE (°C)
–55
5
E/A SOURCE CURRENT (μA)
10
15
20
–25 5 35 65
3440 G12
95 125
V
IN
= V
OUT
= 3.6V
Output Frequency NMOS RDS(ON) Feedback Voltage
TEMPERATURE (°C)
–55
0.90
FREQUENCY (MHz)
0.95
1.00
1.05
1.10
–25 5 35 65
3440 G13
95 125
VIN = VOUT = 3.6V
TEMPERATURE (°C)
–55
0.10
NMOS RDS(ON) (Ω)
0.15
0.20
0.25
0.30
–25 5 35 65
3440 G14
95 125
VIN = VOUT = 3.6V
SWITCHES B AND C
TEMPERATURE (°C)
–55
1.196
FEEDBACK VOLTAGE (V)
1.216
1.236
–25 5 35 65
3440 G15
95 125
V
IN
= V
OUT
= 3V
Switch Pins in Buck Mode
VOUT Ripple During Buck,
Buck/Boost and Boost Modes
SW1
2V/DIV
SW2
2V/DIV
V
IN
= 5V 250ns/DIV 3440 G07
V
OUT
= 3.3V
I
OUT
= 250mA
Switch Pins in Boost Mode
SW1
2V/DIV
SW2
2V/DIV
V
IN
= 2.5V 250ns/DIV 3440 G08
V
OUT
= 3.3V
I
OUT
= 250mA
V
OUT
10mV/DIV
AC Coupled
L = 10μH1μs/DIV 3440 G09
C
OUT
= 22μF
I
OUT
= 250mA
f
OSC
= 1MHz
Buck
V
IN
= 5V
Buck/Boost
V
IN
= 3.78V
Boost
V
IN
= 2.5V
5
LTC3440
3440fb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Boost Max Duty Cycle Minimum Start Voltage Current Limit
TEMPERATURE (°C)
–55
70
DUTY CYCLE (%)
75
80
85
90
–25 5 35 65
3440 G19
95 125
V
IN
= V
OUT
= 3.6V
R
T
= 60k
TEMPERATURE (°C)
–55
2.25
MINIMUM START VOLTAGE (V)
2.30
2.35
2.40
–25 5 35 65
3440 G20
95 125
TEMPERATURE (°C)
–55
1000
CURRENT LIMIT (A)
1500
2000
2500
3000
–25 5 35 65
3440 G21
95 125
V
IN
= V
OUT
= 3.6V
PEAK SWITCH
AVERAGE INPUT
Feedback Voltage Line Regulation Error Amp Sink Current PMOS RDS(ON)
TEMPERATURE (°C)
–55
60
LINE REGULATION (dB)
70
80
90
–25 5 35 65
3440 G16
95 125
V
IN
= V
OUT
= 2.5V TO 5.5V
TEMPERATURE (°C)
–55
350
E/A SINK CURRENT (μA)
370
390
410
430
–25 5 35 65
3440 G17
95 125
VIN = VOUT = 3.6V
TEMPERATURE (°C)
–55
0.10
PMOS RDS(ON) (Ω)
0.15
0.20
0.25
0.30
–25 5 35 65
3440 G18
95 125
VIN = VOUT = 3.6V
SWITCHES A AND D
6
LTC3440
3440fb
R
T
(Pin 1): Timing Resistor to Program the Oscillator
Frequency. The programming frequency range is 300kHz
to 2MHz.
fRHz
OSC T
=610
10
•
MODE/SYNC (Pin 2): MODE/SYNC = External CLK : Syn-
chronization of the internal oscillator. A clock frequency of
twice the desired switching frequency and with a pulse
width between 100ns and 2μs is applied. The oscillator
free running frequency is set slower than the desired
synchronized switching frequency to guarantee sync. The
oscillator R
T
component value required is given by:
Rf
T
SW
=810
10
•
where f
SW
= desired synchronized switching frequency.
SW1 (Pin 3): Switch Pin Where the Internal Switches A
and B are Connected. Connect inductor from SW1 to SW2.
An optional Schottky diode can be connected from SW1 to
ground. Minimize trace length to keep EMI down.
SW2 (Pin 4): Switch Pin Where the Internal Switches C
and D are Connected. For applications with output volt-
UU
U
PI FU CTIO S
ages over 4.3V, a Schottky diode is required from SW2 to
V
OUT
to ensure the SW pin does not exhibit excess voltage.
GND (Pin 5): Signal and Power Ground for the IC.
V
OUT
(Pin 6): Output of the Synchronous Rectifier. A filter
capacitor is placed from V
OUT
to GND.
V
IN
(Pin 7): Input Supply Pin. Internal V
CC
for the IC. A
ceramic bypass capacitor as close to the V
IN
pin and GND
(Pin 5) is required.
SHDN/SS (Pin 8): Combined Soft-Start and Shutdown.
Grounding this pin shuts down the IC. Tie to >1.5V to
enable the IC and >2.5V to ensure the error amp is not
clamped from soft-start. An RC from the shutdown com-
mand signal to this pin will provide a soft-start function by
limiting the rise time of the V
C
pin.
FB (Pin 9): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.5V to
5.5V. The feedback reference voltage is typically 1.22V.
V
C
(Pin 10): Error Amp Output. A frequency compensation
network is connected from this pin to the FB pin to
compensate the loop. See the section “Compensating the
Feedback Loop” for guidelines.
Exposed Pad (Pin 11, DFN Package Only): Ground. This
pin must be soldered to the PCB and electrically connected
to ground.
7
LTC3440
3440fb
BLOCK DIAGRA
W
–
+
–
+
–
+
–
+
–
+
–
+
7
PWM
LOGIC
AND
OUTPUT
PHASING
GATE
DRIVERS
AND
ANTICROSS
CONDUCTION
Burst Mode
OPERATION
CONTROL
5μs DELAY
GND
UVLO
2.7A
2.4V
R
T
SLEEP
MODE/SYNC
1 = Burst Mode
OPERATION
0 = FIXED FREQUENCY
R
T
OSC
SYNC
SUPPLY
CURRENT
LIMIT
SW A
SW1 SW2
V
IN
2.5V TO 5.5V SW D
I
SENSE
AMP
ERROR
AMP 1.22V
CLAMP
REVERSE
CURRENT
LIMIT
SW B SW C
–0.4A
1
2
5
8
+
3 4
V
OUT
6
FB
9
V
C
10
SHDN/SS
SHUTDOWN
R
SS
V
IN
R2
C
SS
R1
3440 BD
V
OUT
2.5V TO 5.5V
PWM
COMPARATORS
8
LTC3440
3440fb
OPERATIO
U
The LTC3440 provides high efficiency, low noise power
for applications such as portable instrumentation. The
LTC proprietary topology allows input voltages above,
below or equal to the output voltage by properly phasing
the output switches. The error amp output voltage on the
V
C
pin determines the output duty cycle of the switches.
Since the V
C
pin is a filtered signal, it provides rejection of
frequencies from well below the switching frequency. The
low R
DS(ON)
, low gate charge synchronous switches pro-
vide high frequency pulse width modulation control at
high efficiency. Schottky diodes across the synchronous
switch D and synchronous switch B are not required, but
provide a lower drop during the break-before-make time
(typically 15ns). The addition of the Schottky diodes will
improve peak efficiency by typically 1% to 2% at 600kHz.
High efficiency is achieved at light loads when Burst Mode
operation is entered and when the IC’s quiescent current
is a low 25μA.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator
The frequency of operation is user programmable and is
set through a resistor from the R
T
pin to ground where:
fe
RHz
T
=⎛
⎝
⎜⎞
⎠
⎟
610
An internally trimmed timing capacitor resides inside the
IC. The oscillator can be synchronized with an external
clock applied to the MODE/SYNC pin. A clock frequency of
twice the desired switching frequency and with a pulse
width between 100ns and 2μs is applied. The oscillator R
T
component value required is given by:
Rf
T
SW
=810
10
•
where f
SW
= desired synchronized switching frequency.
For example to achieve a 1.2MHz synchronized switching
frequency the applied clock frequency to the MODE/SYNC
pin is set to 2.4MHz and the timing resistor, R
T
, is set to
66.5k (closest 1% value).
Error Amp
The error amplifier is a voltage mode amplifier. The loop
compensation components are configured around the
amplifier to provide loop compensation for the converter.
The SHDN/SS pin will clamp the error amp output, V
C
, to
provide a soft-start function.
Supply Current Limit
The current limit amplifier will shut PMOS switch A off
once the current exceeds 2.7A typical. The current ampli-
fier delay to output is typically 50ns.
Reverse Current Limit
The reverse current limit amplifier monitors the inductor
current from the output through switch D. Once a negative
inductor current exceeds – 400mA typical, the IC will shut
off switch D.
Output Switch Control
Figure 1 shows a simplified diagram of how the four
internal switches are connected to the inductor, V
IN
, V
OUT
and GND. Figure 2 shows the regions of operation for the
LTC3440 as a function of the internal control voltage, V
CI
.
The V
CI
voltage is a level shifted voltage from the output of
the error amp (V
C
pin) (see Figure 5). The output switches
are properly phased so the transfer between operation
modes is continuous, filtered and transparent to the user.
When V
IN
approaches V
OUT
the Buck/Boost region is
reached where the conduction time of the four switch
region is typically 150ns. Referring to Figures 1 and 2, the
various regions of operation will now be described.
Figure 1. Simplified Diagram of Output Switches
3
SW1
4
SW2
PMOS A
NMOS B
7
V
IN
PMOS D
NMOS C
3440 F01
6
V
OUT
V
OUT
9
LTC3440
3440fb
OPERATIO
U
Buck Region (V
IN
> V
OUT
)
Switch D is always on and switch C is always off during this
mode. When the internal control voltage, V
CI
, is above
voltage V1, output A begins to switch. During the off time
of switch A, synchronous switch B turns on for the
remainder of the time. Switches A and B will alternate
similar to a typical synchronous buck regulator. As the
control voltage increases, the duty cycle of switch A
increases until the maximum duty cycle of the converter in
Buck mode reaches D
MAX
_
BUCK
, given by:
D
MAX
_
BUCK
= 100 – D4
SW
%
where D4
SW
= duty cycle % of the four switch range.
D4
SW
= (150ns • f) • 100 %
where f = operating frequency, Hz.
Beyond this point the “four switch,” or Buck/Boost region
is reached.
Buck/Boost or Four Switch (V
IN
~ V
OUT
)
When the internal control voltage, V
CI
, is above voltage V2,
switch pair AD remain on for duty cycle D
MAX_BUCK
, and
the switch pair AC begins to phase in. As switch pair AC
phases in, switch pair BD phases out accordingly. When
the V
CI
voltage reaches the edge of the Buck/Boost range,
at voltage V3, the AC switch pair completely phase out the
BD pair, and the boost phase begins at duty cycle D4
SW
.
Figure 2. Switch Control vs Internal Control Voltage, VCI
The input voltage, V
IN
, where the four switch region begins
is given by:
VV
ns f V
IN OUT
=1 150–( • )
The point at which the four switch region ends is given by:
V
IN
= V
OUT
(1 – D) = V
OUT
(1 – 150ns • f) V
Boost Region (V
IN
< V
OUT
)
Switch A is always on and switch B is always off during
this mode. When the internal control voltage, VCI, is above
voltage V3, switch pair CD will alternately switch to
provide a boosted output voltage. This operation is typical
to a synchronous boost regulator. The maximum duty
cycle of the converter is limited to 75% typical and is
reached when VCI is above V4.
Burst Mode Operation
Burst Mode operation is when the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
25μA. In this mode the output ripple has a variable
frequency component that depends upon load current.
During the period where the device is delivering energy to
the output, the peak current will be equal to 400mA typical
and the inductor current will terminate at zero current for
each cycle. In this mode the maximum average output
current is given by:
IV
VV
A
OUT MAX BURST IN
OUT IN
() .•
≈+
01
Burst Mode operation is user controlled, by driving the
MODE/SYNC pin high to enable and low to disable.
The peak efficiency during Burst Mode operation is less
than the peak efficiency during fixed frequency because
the part enters full-time 4-switch mode (when servicing
the output) with discontinuous inductor current as illus-
trated in Figures 3 and 4. During Burst Mode operation, the
control loop is nonlinear and cannot utilize the control
75%
D
MAX
BOOST
D
MIN
BOOST
D
MAX
BUCK
DUTY
CYCLE
0%
V4 (≈2.05V)
V3 (≈1.65V)
BOOST REGION
BUCK REGION
BUCK/BOOST REGION
V2 (≈1.55V)
V1 (≈0.9V)
3440 F02
A ON, B OFF
PWM CD SWITCHES
D ON, C OFF
PWM AB SWITCHES
FOUR SWITCH PWM
INTERNAL
CONTROL
VOLTAGE, V
CI
10
LTC3440
3440fb
voltage from the error amp to determine the control mode,
therefore full-time 4-switch mode is required to maintain
the Buck/Boost function. The efficiency below 1mA
becomes dominated primarily by the quiescent current
and not the peak efficiency. The equation is given by:
Efficiency Burst ( bm) •ILOAD
≈μ+
η
25 A ILOAD
where (ηbm) is typically 79% during Burst Mode opera-
tion for an ESR of the inductor of 50mΩ. For 200mΩ of
inductor ESR, the peak efficiency (ηbm) drops to 75%.
Burst Mode Operation to Fixed Frequency Transient
Response
When transitioning from Burst Mode operation to fixed
frequency, the system exhibits a transient since the modes
of operation have changed. For most systems this tran-
sient is acceptable, but the application may have stringent
input current and/or output voltage requirements that
dictate a broad-band voltage loop to minimize the tran-
sient. Lowering the DC gain of the loop will facilitate the
task (10M FB to V
C
) at the expense of DC load regulation.
Type 3 compensation is also recommended to broad band
the loop and roll off past the two pole response of the LC
of the converter (see Closing the Feedback Loop).
7
VIN
A
3
SW1
5
GND
4
SW2
L
+–
6
VOUT
D
C
400mA
IINDUCTOR
0mA 3440 F03
T1
B
dI
dT
VIN
L
≈
7
VIN
A
3
SW1
5
GND
4
SW2
L
–+
6
VOUT
D
C
400mA
IINDUCTOR
0mA 3440 F04
T2
B
dI
dT
VOUT
L
≈ –
Figure 3. Inductor Charge Cycle During Burst Mode Operation
Figure 4. Inductor Discharge Cycle During Burst Mode Operation
OPERATIO
U
11
LTC3440
3440fb
SOFT-START
The soft-start function is combined with shutdown. When
the SHDN/SS pin is brought above typically 1V, the IC is
enabled but the EA duty cycle is clamped from the V
C
pin.
COMPONENT SELECTION
Figure 5. Soft-Start Circuitry
–
+
9
10
V
IN
ERROR AMP
1.22V
15μA
FB R1
R2
C
P1
V
C
V
OUT
8
SHDN/SS
C
SS
1V
ENABLE SIGNAL
R
SS
SOFT-START
CLAMP
TO PWM
COMPARATORS
CHIP
ENABLE
3440 F05
–
+
V
CI
Inductor Selection
The high frequency operation of the LTC3440 allows the
use of small surface mount inductors. The inductor cur-
rent ripple is typically set to 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
LVVV
f I Ripple V H
LVV V
f I Ripple V H
IN MIN OUT IN MIN
OUT MAX OUT
OUT IN MAX OUT
OUT MAX IN MAX
>
()
μ
>
()
μ
() ()
()
()
() ()
•–
•••,
•–
•••
where f = operating frequency, MHz
A detailed diagram of this function is shown in Figure 5.
The components R
SS
and C
SS
provide a slow ramping
voltage on the SHDN/SS pin to provide a soft-start
function.
OPERATIO
U
APPLICATIO S I FOR ATIO
WUUU
Figure 6. Recommended Component Placement. Traces Carrying
High Current are Direct. Trace Area at FB and VC Pins are Kept
Low. Lead Length to Battery Should be Kept Short
3440 F06
GND
C2
D2
LTC3440
MULTIPLE
VIAS
L1
R
T
V
C
FB
SHDN/SS
V
IN
V
OUT
MODE/SYNC
SW1
GND
SW2
D1
V
IN
R1 R2
V
OUT
C1
1
2
3
4
5
10
9
8
7
6
12
LTC3440
3440fb
The output capacitance is usually many times larger in
order to handle the transient response of the converter.
For a rule of thumb, the ratio of the operating frequency to
the unity-gain bandwidth of the converter is the amount
the output capacitance will have to increase from the
above calculations in order to maintain the desired tran-
sient response.
The other component of ripple is due to the ESR (equiva-
lent series resistance) of the output capacitor. Low ESR
capacitors should be used to minimize output voltage
ripple. For surface mount applications, Taiyo Yuden ce-
ramic capacitors, AVX TPS series tantalum capacitors or
Sanyo POSCAP are recommended.
Input Capacitor Selection
Since the V
IN
pin is the supply voltage for the IC it is
recommended to place at least a 4.7μF, low ESR bypass
capacitor.
Table 2. Capacitor Vendor Information
SUPPLIER PHONE FAX WEB SITE
AVX (803) 448-9411 (803) 448-1943 www.avxcorp.com
Sanyo (619) 661-6322 (619) 661-1055 www.sanyovideo.com
Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com
Optional Schottky Diodes
To achieve a 1%-2% efficiency improvement above 50mW,
Schottky diodes can be added across synchronous switches
B (SW1 to GND) and D (SW2 to V
OUT
). The Schottky
diodes will provide a lower voltage drop during the break-
before-make time (typically 15ns) of the NMOS to PMOS
transition. General purpose diodes such as a 1N914 are
not recommended due to the slow recovery times and will
compromise efficiency. If desired a large Schottky diode,
such as an MBRM120T3, can be used from SW2 to V
OUT
.
A low capacitance Schottky diode is recommended
from GND to SW1 such as a Phillips PMEG2010EA or
equivalent.
Ripple = allowable inductor current ripple
(e.g., 0.2 = 20%)
V
IN(MIN)
= minimum input voltage, V
V
IN(MAX)
= maximum input voltage, V
V
OUT
= output voltage, V
I
OUT(MAX)
= maximum output load current
For high efficiency, choose an inductor with a high fre-
quency core material, such as ferrite, to reduce core loses.
The inductor should have low ESR (equivalent series
resistance) to reduce the I
2
R losses, and must be able to
handle the peak inductor current without saturating. Molded
chokes or chip inductors usually do not have enough core
to support the peak inductor currents in the 1A to 2A
region. To minimize radiated noise, use a toroid, pot core
or shielded bobbin inductor. See Table 1 for suggested
components and Table 2 for a list of component suppliers.
Table 1. Inductor Vendor Information
SUPPLIER PHONE FAX WEB SITE
Coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com
Coiltronics (561) 241-7876 (561) 241-9339 www.coiltronics.com
Murata USA: USA: www.murata.com
(814) 237-1431 (814) 238-0490
(800) 831-9172
Sumida USA: www.japanlink.com/
(847) 956-0666 (847) 956-0702 sumida
Japan:
81(3) 3607-5111 81(3) 3607-5144
Output Capacitor Selection
The bulk value of the capacitor is set to reduce the ripple
due to charge into the capacitor each cycle. The steady
state ripple due to charge is given by:
%_ •– •
•• %
%_ •–•
•••
%
() ()
() ()
()
Ripple Boost IVV
CV f
Ripple Buck IVV
CV Vf
OUT MAX OUT IN MIN
OUT OUT
OUT MAX IN MAX OUT
OUT IN MAX OUT
=
()
=
()
100
100
2
where C
OUT
= output filter capacitor, F
APPLICATIO S I FOR ATIO
WUUU
13
LTC3440
3440fb
APPLICATIO S I FOR ATIO
WUUU
Output Voltage > 4.3V
A Schottky diode from SW to V
OUT
is required for output
voltages over 4.3V. The diode must be located as close to
the pins as possible in order to reduce the peak voltage on
SW2 due to the parasitic lead and trace inductance.
Input Voltage > 4.5V
For applications with input voltages above 4.5V which
could exhibit an overload or short-circuit condition, a 2Ω/
1nF series snubber is required between the SW1 pin and
GND. A Schottky diode such as the Phillips PMEG2010EA
or equivalent from SW1 to V
IN
should also be added as
close to the pins as possible. For the higher input voltages
V
IN
bypassing becomes more critical, therefore, a ceramic
bypass capacitor as close to the V
IN
and GND pins as
possible is also required.
Operating Frequency Selection
There are several considerations in selecting the operating
frequency of the converter. The first is, what are the
sensitive frequency bands that cannot tolerate any spec-
tral noise? For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz and in
that case a 2MHz converter frequency may be employed.
Other considerations are the physical size of the converter
and efficiency. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade off is in efficiency since the switching losses due
to gate charge are going up proportional with frequency.
Additional quiescent current due to the output switches
GATE charge is given by:
Buck: 500e
–12
• V
IN
• F
Boost: 250e
–12
• (V
IN
+ V
OUT
) • F
Buck/Boost: F • (750e
–12
• V
IN
+ 250e
–12
• V
OUT
)
where F = switching frequency
Closing the Feedback Loop
The LTC3440 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(Buck, Boost, Buck-Boost), but is usually no greater than
15. The output filter exhibits a double pole response is
given by:
fLC Hz in Buck e
FILTER POLE
OUT
_
•• • mod=π
1
2()
fV
LV Hz in Boost e
FILTER POLE IN
OUT
_•• mod=π2()
where C
OUT
is the output filter capacitor.
The output filter zero is given by:
fRC
Hz
FILTER ZERO ESR OUT
_
•• •
=π
1
2
where R
ESR
is the capacitor equivalent series resistance.
A troublesome feature in Boost mode is the right-half
plane zero (RHP), and is given by:
fV
ILV
Hz
RHPZ IN
OUT OUT
=π
2
2• • • •
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorpo-
rated to stabilize the loop but at a cost of reduced band-
width and slower transient response. To ensure proper
phase margin, the loop requires to be crossed over a
decade before the LC double pole.
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
fRCP
Hz
UG =π
1
211•• •
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a
higher bandwidth, Type III compensation is required. Two
zeros are required to compensate for the double-pole
response.
14
LTC3440
3440fb
APPLICATIO S I FOR ATIO
WUUU
Short-Circuit Improvements
The LTC3440 is current limited to 2.7A peak to protect the
IC from damage. At input voltages above 4.5V a current
limit condition may produce undesirable voltages to the IC
due to the series inductance of the package, as well as the
Figure 8. Error Amplifier with Type III Compensation
1.22V R1
R2
3440 F08
FB
9
V
C
C
P1
C
Z1
R
Z
V
OUT
10
C
P2
–
+
ERROR
AMP
Figure 7. Error Amplifier with Type I Compensation
1.22V
R1
R2
3440 F07
FB
9
V
C
C
P1
V
OUT
10
–
+
ERROR
AMP
feRCHz
Which is extremely close to DC
fRC
Hz
fRC
Hz
fRCHz
POLE
P
ZERO ZP
ZERO Z
POLE ZP
131
11
21
22
1
232 1
1
2
1
21
1
2
≈π
=π
=π
=π
•• • •
•• •
•• •
•• •
traces and external components. Following the recom-
mendations for output voltage >4.3V and input voltage
>4.5V will improve this condition. Additional short-circuit
protection can be accomplished with some external cir-
cuitry.
In an overload or short-circuit condition the LTC3440
voltage loop opens and the error amp control voltage on
the V
C
pin slams to the upper clamp level. This condition
forces boost mode operation in order to attempt to provide
more output voltage and the IC hits a peak switch current
limit of 2.7A. When switch current limit is reached switches
B and D turn on for the remainder of the cycle to reverse
the volts • seconds on the inductor. Although this prevents
current run away, this condition produces four switch
operation producing a current foldback characteristic and
the average input current drops. The IC is trimmed to
guarantee greater than 1A average input current to meet
the maximum load demand, but in a short-circuit or
overload condition the foldback characteristic will occur
producing higher peak switch currents. To minimize this
affect during this condition the following circuits can be
utilized.
Restart Circuit
For a sustained short-circuit the circuit in Figure 9 will
force a soft-start condition. The only design constraint is
that R2/C2 time constant must be longer than the soft-
start components R1/C1 to ensure start-up.
Figure 9. Soft-Start Reset Circuitry for a Sustained Short-Circuit
C2
10nF
C1
4.7nF
R2
1M
R1
1M
VOUT
VIN
SOFT-START
SO/SS
M2
NMOS
VN2222 M1
NMOS
VN2222
D1
1N4148
3440 F09
15
LTC3440
3440fb
Figure 10. Simple Input Current Control
Utilizing the Voltage Loop
APPLICATIO S I FOR ATIO
WUUU
TYPICAL APPLICATIO S
U
3-Cell to 3.3V at 600mA Converter
SW1
VIN
SHDN/SS
MODE/SYNC
RT
SW2
VOUT
FB
VC
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
4.7μH
D1
R3 15k
R5
10k
R1
340k
R2
200k
3440 TA03a
RT
45.3k fOSC = 1.5MHz
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
D1, D2: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: SUMIDA CDR43-4R7M
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C1
10μF
3 CELLS
VIN = 2.7V TO 4.5V
*
C4 150pF
C3
33pF
D2
C5 10pF
C2
22μF
VOUT
3.3V
600mA
+
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.1 10 100 1000
3440 TA03b
0
1
Burst Mode
OPERATION
V
IN
= 2.7V
V
IN
= 3.3V
f
OSC
= 1.5MHz
V
IN
= 4.5V
3-Cell to 3.3V Efficiency
INPUT_VOLTAGE
FB_PIN
VIN_PIN
Q1
2N3906
R1
0.5Ω
C1
10μF
V1
Simple Average Input Current Control
A simple average current limit circuit is shown in
Figure 10. Once the input current of the IC is above
approximately 1A, Q1 will start sourcing current into the
FB pin and lower the output voltage to maintain the
average input current. Since the voltage loop is utilized to
perform average current limit, the voltage control loop is
maintained and the V
C
voltage does not slam. The averag-
ing function of current comes from the fact that voltage
loop compensation is also used with this circuit.
16
LTC3440
3440fb
TYPICAL APPLICATIO S
U
Low Profile (<1.1mm) Li-Ion to 3.3V at 200mA Converter
SW1
V
IN
SHDN/SS
MODE/SYNC
R
T
SW2
V
OUT
FB
V
C
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
4.7μH
R1
340k
R2
200k
R3
15k
3440 TA04a
R
T
30.1k
C1: TAIYO YUDEN JMK212BJ475MG
C2: TAIYO YUDEN JMK212BJ475MG
L1: COILCRAFT LPO1704-472M
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
f
OSC
= 2MHz
C1
4.7μF
Li-Ion
V
IN
= 2.5V TO 4.2V
*
+
C4
1.5nF
C2
4.7μF
V
OUT
3.3V
200mA
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.1 10 100 1000
3440 TA04b
0
1
Burst Mode
OPERATION
V
IN
= 2.5V
V
IN
= 3.3V
V
IN
= 4.2V
Efficiency
3-Cell to 5V Boost Converter with Output Disconnect
SW1
VIN
SHDN/SS
MODE/SYNC
RT
SW2
VOUT
FB
VC
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
10μH
R1
619k
R2
200k
3440 TA06a
RT
60.4k
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120T3
L1: SUMIDA CDRH4D28-100
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
** LOCATE COMPONENTS AS
CLOSE TO IC AS POSSIBLE
C1
10μF
C3
0.1μF
3
CELLS
R4 1M
VIN = 2.7V TO 4.5V
*
SD
C4
1.5nF
15k
fOSC = 1MHz
C2**
22μF
VOUT
5V
300mA
+
D1**
OUTPUT CURRENT (mA)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.1 10 100 1000
3440 TA06b
0
1
Burst Mode
OPERATION
V
IN
= 2.7V
f
OSC
= 1MHz
V
IN
= 3.6V
V
IN
= 4.5V
3-Cell to 5V Boost Efficiency
17
LTC3440
3440fb
SW1
V
IN
SHDN/SS
MODE/SYNC
R
T
SW2
V
OUT
FB
V
C
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
3.3μH
R1
340k
R5
10k
R2
200k
R3 15k
D1**
3440 TA07a
R
T
30.1k
C1, C2: TAIYO YUDEN JMK212BJ106MM
D1: ON SEMICONDUCTOR MBRM120T3
L1: SUMIDA CDRH4D28-3R3
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
** LOCATE COMPONENTS AS
CLOSE TO IC AS POSSIBLE
C1
10μF
f
OSC
= 2MHz
Li-Ion
V
IN
=
2.5V TO 4.2V
*
+
C4 150pF
C5 10pF
C2**
10μF
V
OUT
0.4V TO 5V
C3
33pF
V
OUT
= 3.3V – 1.7V • (V
DAC
– 1.22V)
R6
200k
DAC
WCDMA Power Amp Power Supply with Dynamic Voltage Control
Efficiency of the WCDMA
Power Amp Power Supply
INPUT VOLTAGE (V)
2.5
EFFICIENCY (%)
92
96
100
4.5
3440 TA07b
88
84
90
94
98
86
82
80 33.5 45
V
OUT
= 3.4V
I
OUT
= 100mA
I
OUT
= 250mA
I
OUT
= 600mA
TYPICAL APPLICATIO S
U
SW1
VIN
SHDN/SS
MODE/SYNC
RT
SW2
VOUT
FB
VC
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
10μH
R5
24k
3440 TA08
RT
60.4k
RS
0.1Ω
R4
1k
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
L1: SUMIDA CDRH-4D28-100
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C1
10μF
VIN
2.5V TO 5.5V
USB/PCMCIA POWER
500mA MAX
*
VOUT
3.6V
2A
(PULSED)
C5
10nF
R6
130k
R1
392k
R2
200k
–
+
1/2 LT1490A 2N3906
–
+
1/2 LT1490A
1N914 C6 TO C9
470μF
×4
1.22 • R4
R5 • RS
ICURRENTLIMIT =
GSM Modem Powered from USB or PCMCIA with 500mA Input Current Limit
18
LTC3440
3440fb
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
19
LTC3440
3440fb
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
MSOP (MS) 0603
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20
LTC3440
3440fb
© LINEAR TECHNOLOGY CORPORATION 2001
LT 0507 REV B • PRINTED IN USA
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SD
= <1μA, TSSOP16 Package
LT1961 1.5A(I
SW
), 1.25MHz, High Efficiency Step-Up 90% Efficiency, V
IN
: 3V to 25V, V
OUT(MIN)
= 35V, I
Q
= 0.9mA,
DC/DC Converter I
SD
= 6μA, MS8E Package
LTC3400/LTC3400B 600mA(I
SW
), 1.2MHz, Synchronous Step-Up 92% Efficiency, V
IN
: 0.85V to 5V, V
OUT(MIN)
= 5V, I
Q
= 19μA/300μA,
DC/DC Converter I
SD
= <1μA, ThinSOT Package
LTC3401 1A(I
SW
), 3MHz, Synchronous Step-Up 97% Efficiency, V
IN
: 0.5V to 5V, V
OUT(MIN)
= 6V, I
Q
= 38μA,
DC/DC Converter I
SD
= <1μA, MS10 Package
LTC3402 2A(I
SW
), 3MHz, Synchronous Step-Up 97% Efficiency, V
IN
: 0.5V to 5V, V
OUT(MIN)
= 6V, I
Q
= 38μA,
DC/DC Converter I
SD
= <1μA, MS10 Package
LTC3405/LTC3405A 300mA(I
OUT
), 1.5MHz, Synchronous Step-Down 95% Efficiency, V
IN
: 2.7V to 6V, V
OUT(MIN)
= 0.8V, I
Q
= 20μA,
DC/DC Converter I
SD
= <1μA, ThinSOT Package
LTC3406/LTC3406B 600mA(I
OUT
), 1.5MHz, Synchronous Step-Down 95% Efficiency, V
IN
: 2.5V to 5.5V, V
OUT(MIN)
= 0.6V, I
Q
= 20μA,
DC/DC Converter I
SD
= <1μA, ThinSOT Package
LTC3411 1.25A(I
OUT
), 4MHz, Synchronous Step-Down 95% Efficiency, V
IN
: 2.5V to 5.5V, V
OUT(MIN)
= 0.8V, I
Q
= 60μA,
DC/DC Converter I
SD
= <1μA, MS10 Package
LTC3412 2.5A(I
OUT
), 4MHz, Synchronous Step-Down 95% Efficiency, V
IN
: 2.5V to 5.5V, V
OUT(MIN)
= 0.8V, I
Q
= 60μA,
DC/DC Converter I
SD
= <1μA, TSSOP16E Package
LTC3441/LTC3443 1.2A(I
OUT
), 1MHz/0.6MHz, Micropower Synchronous 95% Efficiency, V
IN
: 2.4V to 5.5V, V
OUT(MIN)
: 2.4V to 5.25V,
Buck-Boost DC/DC Converter I
Q
= 25μA, I
SD
= <1μA, DFN Package
ThinSOT is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
Efficiency
3440 TA05
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
00.1 10 100 10001.0
VIN = 4.2V
VIN = 3.3V
Burst Mode
OPERATION
Li-Ion to 3.3V at 600mA Buck-Boost Converter
SW1
V
IN
SHDN/SS
MODE/SYNC
R
T
SW2
V
OUT
FB
V
C
GND
3
7
8
2
1
4
6
9
10
5
LTC3440
L1
10μH
R1
340k
R2
200k
R3
15k
3440 TA01
R
T
60.4k
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
L1: SUMIDA CDRH4D28-100
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C1
10μF
Li-Ion
V
IN
=
2.8V TO 4.2V
*
+
C5 300pF C2
22μF
V
OUT
3.3V
600mA
220pF
2.2k