SO16 narrow
Features
• Smart stand-by architecture using the zero-power mode (ZPM)
• ZPM management by MCU easily realizable
• 800 V avalanche-rugged power MOSFET allowing ultra wide VAC input range to
be covered
• Embedded HV startup and sense-FET
• Current mode PWM controller
• Drain current limit protection (OCP)
• Wide supply voltage range: 4.5 V to 30 V
• Self-supply option allows to remove the auxiliary winding or bias components
• Minimized system input power consumption:
– Less than 4 mW @ 230 VAC in ZPM
– Less than 10 mW @ 230 VAC in no-load condition
– Less than 400 mW @ 230 VAC with 250 mW load
• Jittered switching frequency reduces the EMI filter cost
– 60 kHz ± 7% (type L)
– 120 kHz ± 7% (type H)
• Embedded E/A with 1.2 V reference and separate ground for easy negative
voltage setting
• Protections with automatic restart: overload/short circuit (OLP), max. duty cycle
counter, VCC clamp
• Pulse-skip protection to prevent flux-runaway
• Embedded thermal shutdown
• Built in soft start for improved system reliability
Applications
• SMPS for home appliances, home automation, industrial, lighting and
consumers
Figure 1. Basic application schematic
~ AC
Cs
Cin
Din
T
Dout
Rin
COMP FB
DRAIN
PGND
SGND
ON
OFF
VCC
EAGND
VIPER0P
Rcl
C1
R2
R1
Ccl
Tactile
switch MCU
Vout
Cout
GND
Product status link
VIPer0P
Zero-power off-line high voltage converter
VIPer0P
Datasheet
DS11301 - Rev 3 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1Description
The device is a high-voltage converter that smartly integrates an 800 V avalanche rugged power MOSFET with
PWM current-mode control. The power MOSFET with 800 V breakdown voltage allows extended input voltage
range to be applied, as well as to reduce the size of the DRAIN snubber circuit. This IC is capable of meeting the
most stringent energy-saving standards as it has very low consumption and operates in pulse frequency
modulation under light load. The zero-power mode (ZPM) feature enables the IC to work in an idle state, where
the system is totally shutdown. An MCU can be easily connected to the IC for smart ZPM management and it can
be supplied by the IC itself during the idle state. The design of flyback, buck and buck boost converters is
supported. The integrated HV startup, sense FET, error amplifier and oscillator with jitter allow a complete
application to be designed with a minimum component count. In flyback non isolated topology, a negative output
voltage is easily set thanks to the integrated error amplifier with separate ground.
VIPer0P
Description
DS11301 - Rev 3 page 2/36
2Pin setting
Figure 2. Connection diagram
PGND DRAIN
DRAIN
SGND
COMP
EAGND
FB
ON
OFF
DRAIN
DRAIN
N.C.
N.C.
N.C.
N.C.
VCC
VIPer0P
GIPD210420151108MT
Note: The PCB copper area for heat dissipation has to be provided under the DRAIN pins.
Table 1. Pin description
SO16N Name Function
1 PGND Power ground and MOSFET source. The pulsed current flowing through the Power MOSFET must be closed on this pin.
The pin must be connected to the same ground plan of SGND with the shortest track.
2 EAGND Error amplifier ground reference. In case of non-isolated flyback converter with negative output voltage, this pin can be
connected directly to the negative rail. Otherwise, in case of positive output voltage, the pin must be shorted to SGND.
3 VCC
Controller supply. An external storage capacitor has to be connected across this pin and SGND. The pin, internally
connected to the high-voltage current source, provides the VCC capacitor charging current at startup and, if self-supply
mode is selected, also during steady-state operation. A small bypass capacitor (0.1 μF typ.) in parallel, placed as close as
possible to the IC, is also recommended, for noise filtering purpose.
4 SGND Signal ground. All of the groundings of bias components must be tied to a trace going to this pin and kept separate from
the pulsed current return.
5 FB
Direct feedback. It is the inverting input of the internal transconductance E/A, which is internally referenced to 1.2 V with
respect to EAGND. In case of non-isolated converter, the output voltage information is directly fed into the pin through a
voltage divider. In case of primary regulation, the FB voltage divider is connected to the VCC. The E/A is disabled
soldering FB to EAGND.
6 COMP
Compensation. It is the output of the internal E/A. A compensation network is placed between this pin and SGND to
achieve stability and good dynamic performance of the control loop. In case of secondary feedback, the internal E/A must
be disabled and the COMP directly driven by the optocoupler to control the DRAIN peak current setpoint.
7 ON
ZPM exit. When the device is in ZPM, the IC is reactivated by forcing this pin to SGND for a debounce time, tDEB_ON.
Due to the extremely low level of energy available while in ZPM, the pin can be noise sensitive. A film-type bypass
capacitor from the pin to SGND is therefore recommended in a noisy environment to prevent improper startup of the
device. An internal pull-up resistor keeps the pin voltage at VON level during normal operation.
8 OFF ZPM enter. To enter ZPM this pin has to be forced to SGND, for a debounce time tDEB_OFF. An internal pull-up resistor
keeps the pin voltage at VOFF level during normal operation.
9 to12 N.C. These pins are not internally connected and must be left floating in order to get a safe clearance distance.
13 to 16 DRAIN
MOSFET drain. The internal high-voltage current source sinks current from this pin to charge the VCC capacitor at startup
and during steady-state operation.
These pins are mechanically connected to the internal metal PAD of the MOSFET in order to facilitate heat dissipation. On
the PCB, some copper area must be placed under these pins in order to decrease the total junction-to-ambient thermal
resistance thus facilitating the power dissipation.
VIPer0P
Pin setting
DS11301 - Rev 3 page 3/36
3Electrical and thermal ratings
Table 2. Absolute maximum ratings
Symbol Pin Parameter (1) Min. Max. Unit
VDS 13 to 16 Drain-to-source (ground) voltage -0.3 800 V
IDRAIN 13 to 16 Pulsed drain current (pulse-width limited by SOA) 2 A
VEAGND 2
EAGND voltage (referred to VCC) -35 (2) 0.3 V
EAGND voltage (referred to SGND) 0.3 V
VCC 3
VCC voltage (referred to EAGND) -0.3 35 (2) V
VCC voltage (referred to SGND) -0.3 35 V
ICC 3 VCC internal Zener current 30 mA
VFB 5
FB voltage (referred to EAGND) -0.3 5 (2) V
FB voltage (referred to VCC) -35 0.3 V
VCOMP 6
COMP voltage (referred to SGND) -0.3 5 (2) V
COMP voltage (referred to VCC) -35 0.3 V
VON 7
ON voltage (referred to SGND) -0.3 5.5 V
ON voltage (referred to VCC) -35 0.3 V
VOFF 8
OFF voltage (referred to SGND) -0.3 5.5 V
OFF voltage (referred to VCC) -35 0.3 V
PTOT Power dissipation @ Tamb < 50 °C 1 W
TjJunction temperature operating range -40 150 °C
TSTG Storage temperature -55 150 °C
1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Voltage is internally limited.
Table 3. Thermal data
Symbol Parameter
Max. value
Unit
SO16N
RthJP Thermal resistance junction-pin (dissipated power 1 W) 35
°C/W
RthJA (1) Thermal resistance junction-ambient (dissipated power 1 W) 110
Thermal resistance junction-ambient (dissipated power 1 W) (2) 80
1. Derived by characterization.
2. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 µm thick).
Table 4. Avalanche characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
IAR Avalanche current
Pulse-width limited by TJmax
Repetitive and non-repetitive
0.8 A
EAS Single pulse avalanche energy(1)
Starting TJ = 25 °C
IAS = IAR; VDS = 100 V 0.5 mJ
VIPer0P
Electrical and thermal ratings
DS11301 - Rev 3 page 4/36
1. Parameter derived by characterization.
3.1 Electrical characteristics
Tj = -40 to 125 °C, VCC = 9 V (unless otherwise specified).
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VBVDSS Breakdown voltage
IDRAIN = 1 mA,
VCOMP = SGND, TJ = 25 °C 800 V
IDSS Drain-source leakage current VDS = 400 V, VCOMP = SGND, TJ = 25 °C 1 µA
RDS(on) Static drain-source on-resistance
IDRAIN = 200 mA, TJ = 25 °C 20
Ω
IDRAIN = 200 mA, TJ = 125 °C 40
COSS EQ Equivalent output capacitance
VGS = 0; VDS = 0 to 640 V,
TJ = 25 °C 10 pF
VIPer0P
Electrical characteristics
DS11301 - Rev 3 page 5/36
Table 6. Supply section
Symbol Parameter Test conditions Min. Typ. Max. Unit
High voltage startup current source
VBVDSS_SU Breakdown voltage of startup MOSFET 800 V
VHV_START Drain-source start up voltage 40 80 V
RGStartup resistor
VDRAIN = 400 V, VDRAIN = 600 V
VFB > VFB_REF,28 34 40 MΩ
ICH1 VCC charging current at startup
VCC = 0 V, TJ = 25 °C
VFB > VFB_REF, VDRAIN = 100 V 0.7 1 1.3
mA
ICH2 VCC charging current at startup
VCC = 1 V, TJ = 25 °C
VFB > VFB_REF, VDRAIN = 100 V 2.3 3.2 4.1
ICH3 (1) Max. VCC charging current in self-
supply
VCC = 6 V, TJ = 25 °C
VFB > VFB_REF, VDRAIN = 100 V 6.4 7.8 9.2
IC supply and consumptions
VCC Operating voltage range
referred to SGND, VEAGND = 0
4.5 30 V
referred to EAGND, VEAGND < 0
VCCclamp Clamp voltage ICC = Iclamp_max 30 32.5 35 V
Iclamp max Clamp shutdown current VCC > VCCclamp 29 35 41 mA
tclamp max Clamp time before shutdown 5 ms
VCCon VCC startup threshold VFB = 1.2 V,VDRAIN = 400 V 7.5 8 8.5 V
VCSon HV current source turn-on threshold VCC falling 4 4.25 4.5 V
VCCoff UVLO VFB = 1.2 V,VDRAIN = 400 V 3.75 4 4.25 V
IqQuiescent current Not switching, VFB > VFB_REF 0.25 0.35 mA
Iq_ZPM Quiescent current in ZPM Not switching, VFB > VFB_REF, VDRAIN = 325 V 20 µA
ICC Operating supply current, switching
FOSC = 60 kHz, VDS = 150 V, VCOMP =1.2 V 0.6 0.9 1.2
mA
FOSC = 120 kHz, VDS = 150 V, VCOMP =1.2 V 0.9 1.2 1.5
1. Current supplied only during the main MOSFET OFF time.
Table 7. Controller section
Symbol Parameter Test conditions Min. Typ. Max. Unit
E/A
VEAGND E/A ground reference voltage Referred to SGND -20 0 V
VFB_REF E/A reference voltage Referred to EAGND 1.175 1.2 1.225 V
VFB_DIS E/A disable voltage Referred to EAGND 150 250 350 mV
IFB PULL UP Pull-up current 0.5 1 1.5 µA
GMTrans conductance VCOMP = 1.5 V, VFB > VFB_REF 300 550 700 µA/V
ICOMP1 Max. source current VFB = 0.5 V, VCOMP = 1.5 V 75 100 125 µA
ICOMP2 Max. sink current VFB = 2 V, VCOMP = 1.5 V 75 100 125 µA
RCOMP(DYN) Dynamic resistance VCOMP = 2.7 V, VFB = EAGND 55 65 75 kΩ
VIPer0P
Electrical characteristics
DS11301 - Rev 3 page 6/36
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCOMPH Current limitation threshold Referred to SGND 2.65 3.2 3.75 V
VCOMPL PFM threshold Referred to SGND 0.7 0.9 1.1 V
OLP and timing
IDLIM Drain current limitation TJ = 25 °C 380 400 420 mA
I2fPower coefficient
VIPER0PL
-10%
9.6
+10% A2·kHz
VIPER0PH 19.2
IDLIM_PFM Drain current limitation at light load
TJ = 25 °C
VCOMP = VCOMPL (1) 60 95 130 mA
tOVL Overload delay time
FOSC = 60 kHz (VIPER0PL)
FOSC = 120 kHz (VIPER0PH) 45 50 55 ms
tOVL_MAX Max. overload delay time
FOSC = FOSC_MIN (VIPER0PL) 180 200 220
ms
FOSC = FOSC_MIN (VIPER0PH) 360 400 440
tSS Soft-start time 8 ms
tON_MIN Minimum turn-on time
VFB = VFB_REF
VCC = 9 V, VCOMP = 1 V, 230 350 ns
tRESTART Restart time after fault 1 s
ZPM
VOFFth ZPM entering threshold During normal operation VCC= 7 V 0.75 1 1.25 V
VOFF Operating voltage level Pin floating 3.75 4.75 V
ROFF Pull-up resistor on OFF pin 32 41 50 kΩ
tDEB_OFF OFF debounce time 10 16 ms
VONth ZPM exiting threshold During ZPM 0.75 1 1.25 V
VON Operating voltage level Pin floating 3.75 4.75 V
RON Pull-up resistor on ON pin 32 41 50 kΩ
tDEB_ON (2) ON debounce time 20 35 µs
Oscillator
FOSC Switching frequency
VIPER0PL 54 60 66
kHz
VIPER0PH 108 120 132
FOSC_MIN Minimum switching frequency (3) 13.5 15 16.5 kHz
FDModulation depht ±7% FOSC kHz
FMModulation frequency 260 Hz
DMAX Max. duty cycle 70 80 %
Thermal shutdown
TSD Thermal shutdown temperature (2) 150 160 °C
1. See Section 5.10 Pulse frequency modulation.
2. Parameter assured by design, characterization, and statistical correlation.
3. See Section 5.7 Pulse skipping.
VIPer0P
Electrical characteristics
DS11301 - Rev 3 page 7/36
4Typical electrical characteristics
Figure 3. IDLIM vs TJ
0.9
1
1.1
-50 0 50 100 150
IDLIM/(IDLIM@25°C)
Tj(°C)
GIPD160720151000MT
Figure 4. ION vs VON
GIPD160720151001MT
0
5
10
15
20
25
30
2.75 3.25 3.75 4.25
ION (µA)
VON (V)
Figure 5. FOSC vs TJ
GIPD160720151002MT
0.95
1
1.05
-50 0 50 100 150
FOSC /(FOSC @25°C)
Tj(°C)
Figure 6. VHV_START vs TJ
0.5
0.75
1
1.25
1.5
-50 0 50 100 150
VHV_START/(VHV_START@25°C)
Tj(°C)
GIPD160720151004MT
Figure 7. VFB_REF vs TJ
GIPD160720151005MT
0.95
1
1.05
-50 0 50 100 150
Tj(°C)
VFB_REF / (VFB_REF @ 25
°
C)
Figure 8. Quiescent current Iq vs TJ
GIPD160720151006MT
0.8
0.9
1
1.1
1.2
-50 0 50 100 150
Iq/(Iq@25°C)
Tj(°C)
VIPer0P
Typical electrical characteristics
DS11301 - Rev 3 page 8/36
Figure 9. Operating current ICC vs TJ
GIPD160720151007MT
0.9
1
1.1
-50 0 50 100 150
Tj(°C)
ICC/(ICC@25°C)
Figure 10. ICOMP vs TJ
GIPD160720151015MT
0.9
1
1.1
-50 0 50 100 150
ICOMP/(ICOMP@25°C)
Tj(°C)
Figure 11. ICH1 vs TJ
GIPD160720151008MT
0.5
0.75
1
1.25
1.5
-50 0 50 100 150
ICH1/(ICH1@25°C)
Tj(°C)
Figure 12. ICH1 vs VDRAIN
GIPD160720151009MT
0.8
0.9
1
1.1
1.2
50 100 150 200 250 300 350 400
VDRAIN [V]
ICH1/(ICH1@VDRAIN=100V)
Figure 13. ICH2 vs TJ
GIPD160720151010MT
0.8
1
1.2
-50 0 50 100 150
ICH2/(ICH2@25°C)
Tj(°C)
Figure 14. ICH2 vs VDRAIN
GIPD160720151011MT
0.8
0.9
1
1.1
1.2
50 100 150 200 250 300 350 400
VDRAIN [V]
ICH2/(ICH2@VDRAIN=100V)
VIPer0P
Typical electrical characteristics
DS11301 - Rev 3 page 9/36
Figure 15. ICH3 vs TJ
GIPD160720151012MT
0.8
1
1.2
-50 0 50 100 150
ICH3/(ICH3@25°C)
Tj(°C)
Figure 16. ICH3 vs VDRAIN
GIPD160720151013MT
0.8
0.9
1
1.1
1.2
50 100 150 200 250 300 350 400
VDRAIN [V]
ICH3/(ICH3@VDRAIN=100V)
Figure 17. GM vs TJ
GIPD160720151014MT
0.8
1
1.2
-50 0 50 100 150
GM/(GM@25°C)
Tj(°C)
Figure 18. RDS(on) vs TJ
GIPD160720151016MT
0.5
1.5
2.5
-50 0 50 100 150
RDS(on)/(RDS(on)@25°C)
Tj(°C)
Figure 19. Static drain source on resistance
GIPD160720151017MT
0.8
1
0
1.2
0.9
1.1
100 200 300 400 500
RDS(on) /(RDS(on)@IDRAIN=200mA)
IDRAIN [mA]
T= 25°C
Figure 20. Output characteristic
GIPD160720151018M
T
0
100
200
300
400
500
600
700
800
900
0 1 2 3 4 5 6 7 8
IDRAIN [mA]
VD-S [V]
T= 50°C
T= 25°C
T= 125°C
VIPer0P
Typical electrical characteristics
DS11301 - Rev 3 page 10/36
Figure 21. VBVDSS vs TJ
GIPD160720151019MT
0.9
1
1.1
-50 0 50 100 150
VBVDSS/(VBVDSS@25°C)
Tj(°C)
Figure 22. Max avalache energy vs TJ
GIPD200820151330MT
0
0.2
1
0 15
1.2
0.4
0.6
0.8
30 45 60 75 90 105 120 135 150
EAS/(EAS@ 25°C)
T
j(°C)
Figure 23. SOA SO16N package
GIPD160720151020MT
1ms
10ms
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
0 1 10 100 1,000
IDRAIN [A]
VD-S [V]
Tj=150°
Tc=25°C
Single pulse
100µs
10µs
C
Operation in this area is
limited by Max RDS(on)
VIPer0P
Typical electrical characteristics
DS11301 - Rev 3 page 11/36
5General description
5.1 Block diagram
Figure 24. Block diagram
5.2 Typical power capability
Table 8. Typical power
Vin: 230 VAC Vin: 85-265 VAC
Adapter (1) Open frame (2) Adapter (1) Open frame (2)
10 W 12 W 6 W 7 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking.
5.3 Primary MOSFET
The primary switch is implemented with an avalanche rugged N-channel MOSFET with minimum breakdown
voltage 800 V, VBVDSS, and maximum on-resistance of 20 Ω, RDS(on). The sense-FET is embedded and it allows
a virtually lossless current sensing. The startup-MOSFET is embedded and it allows the HV voltage startup
operation.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize EMI.
5.4 High voltage startup
The embedded high voltage startup includes both the 800 V startup FET, whose gate is biased through the
resistor RG, and the switchable HV current source, delivering the current IHV. The major portion of IHV, (ICH),
charges the capacitor connected to VCC. A minor portion is sunk by the controller block.
At start up, as the voltage across the DRAIN pin exceeds the VHV_START threshold, the HV current source is
turned on, charging linearly the Cs capacitor. At the very beginning of the start-up, when Cs is fully discharged,
the charging current is low (ICH1 = 1 mA typ.) in order to avoid IC damaging in case VCC is accidentally shorted to
SGND. As VCC exceeds 1 V, ICH is increased to ICH2 (3.2 mA, typ.) in order to speed up the charging of CS.
VIPer0P
General description
DS11301 - Rev 3 page 12/36
As VCC reaches the startup threshold VCCon (8 V typ.) the chip starts operating, the primary MOSFET is enabled
to switch, the HV current source is disabled and the device is powered by the energy stored in the CS capacitor.
In steady-state the IC supports two different kind of supplies: self-supply and external supply, as shown in
Figure 25. IC supply modes: self-supply and external supply.
Figure 25. IC supply modes: self-supply and external supply
GIPD160720151024MT
ICH
VCC
Self-supply External supply
from the output from auxiliary winding
VOUT
ICH VCC ICH VCC
VAux
CSCSCS
In self-supply only a capacitor CS is connected to the VCC and the device is supplied by the energy stored in CS.
After the IC startup, due to its internal consumption, the VCC decays to VCson (4.25 V, typ.) and the HV current
source is turned on delivering the current ICH3 (7.8 mA typ.) until VCC is recharged to VCCon. The HV current
source is reactivated when VCC decays to VCSon again. The ICH3 is supplied during the switching OFF time only.
In external supply the HV current source is always kept off by maintaining the VCC above VCSon. This can be
obtained through a transformer auxiliary winding or a connection from the output, the latter only in case of non-
isolated topology. In this case the residual consumption is given by the power dissipated on RG, calculated as
follows:
G
INDC
dR
V
P
2
=
At the nominal input voltage, 230 VAC, the typical consumption (RG = 34 MΩ) is 3.2 mW and the worst-case
consumption (RG = 28 MΩ) is 3.9 mW.
When the IC is disconnected from the mains, or there is a mains interruption, for some time the converter will
keep on working, powered by the energy stored in the input bulk capacitor. When this is discharged below a
critical value, the converter is no longer able to keep the output voltage regulated. During the power down, when
the DRAIN voltage becomes too low, the HV current source (IHV) remains off and the IC is stopped as soon as the
VCC drops below the UVLO threshold, VCCoff.
VIPer0P
High voltage startup
DS11301 - Rev 3 page 13/36
Figure 26. Power-ON and power-OFF
5.5 Soft start up
The internal soft-start function of VIPer0P progressively increases the cycle-by-cycle current limitation set point
from zero up to IDLIM in 8 steps of 50 mA each. The soft-start time, tSS, is internally set at 8 ms. This function is
activated at any attempt of converter start-up and at any restart after a fault event. The feature protects the
system at the startup when the output load presents itself like a short-circuit and the converter would work at its
maximum drain current limitation.
Figure 27. Soft startup
VIPer0P
Soft start up
DS11301 - Rev 3 page 14/36
5.6 Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by
approximately ±7% kHz FOSC at 260 Hz rate. The purpose of the jittering is to get a spread-spectrum action that
distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the
same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially
when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter
of smaller size with respect to the one that should be needed in absence of jittering feature. Two options with
different switching frequencies, FOSC, are available: 60 kHz (L type) and 120 kHz (H type).
5.7 Pulse skipping
The IC embeds a pulse skip circuit that operates in the following way:
• each time the DRAIN peak current exceeds IDLIM level within tON_MIN, the switching cycle is skipped. The
cycles can be skipped until the minimum switching frequency is reached, FOSC_MIN (15 kHz, typ.).
• each time the DRAIN peak current does not exceed IDLIM within tON_MIN, a switching cycle is restored. The
cycles can be restored until the nominal switching frequency is reached, FOSC (60 or 120 kHz, typ.)
If the converter is indefinitely operated at FOSC_MIN, the IC is turned off after the time tOVL_MAX (200 ms or 400 ms
typ., depending on FOSC) and then automatically restarted with soft start phase, after the time tRESTART (1 sec,
typ.).
The protection is intended in order to avoid the so called "flux runaway" condition often present at converter
startup or in case of a dead-short at converter output and due to the fact that the primary MOSFET, which is
turned on by the internal oscillator, cannot be turned off before the minimum on-time.
During the on-time, the inductor is charged through the input voltage and if it cannot be discharged by the same
amount during the off-time, in every switching cycle there is a net increase of the average inductor current, that
can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor
discharge rate needed for the volt-second balance. This condition is common at converter startup, because of the
low output voltage.
In the following Figure 28. Pulse skipping during start-up for FOSC = 60 kHz the effect of pulse skipping feature on
the DRAIN peak current shape is shown (solid line), compared with the DRAIN peak current shape when pulse
skipping feature is not implemented (dashed line). Providing more time for cycle-by-cycle inductor discharge when
needed, this feature is effective in keeping low the maximum DRAIN peak current avoiding the flux runaway
condition.
VIPer0P
Oscillator
DS11301 - Rev 3 page 15/36
Figure 28. Pulse skipping during start-up for FOSC = 60 kHz
5.8 Direct feedback
The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground reference and output
are FB, EAGND and COMP, respectively. The internal reference voltage of the E/A is VFB_REF (1.2 V typical value
referred to EAGND). In non-isolated topologies this makes it possible to tightly regulate positive output voltages
through a simple voltage divider applied among the output voltage terminal, FB and EAGND, and soldering SGND
to EAGND. Since EAGND can float down to -12.5 V with respect to the ground of the IC (SGND), negative output
voltages can be regulated as well, connecting EAGND to the negative rail, and the voltage divider among FB,
EAGND and SGND, as shown in Figure 34. Negative output flyback converter (non-isolated).
The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the
sense resistor in series to the sense-FET, thus setting the cycle-by-cycle drain current limitation.
An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left
floating.
5.9 Secondary feedback
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to EAGND (VFB <
VFB_DIS). With this setting COMP is internally connected to a pre-regulated voltage through the pull-up resistor
RCOMP(DYN), (65 kΩ, typ.) and the voltage across COMP is set by the current sunk.
This allows the output voltage value to be set through an external error amplifier (TL431 or similar) placed on the
secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output
power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the
phototransistor collector connected across COMP and SGND.
5.10 Pulse frequency modulation
If the output load is decreased, the feedback loop reacts lowering the VCOMP voltage, which reduces the DRAIN
peak current setpoint, down to the minimum value of IDLIM_PFM when the VCOMPL threshold is reached.
If the load is further decreased, the DRAIN peak current value is maintained at IDLIM_PFM and some PWM cycles
are skipped. This mode of operation is referred to as “pulse frequency modulation” (PFM), the number of the
skipped cycles depends on the balance between the output power demand and the power transferred from the
VIPer0P
Direct feedback
DS11301 - Rev 3 page 16/36
input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all
the frequency-related losses.
This kind of operation, together with the extremely low IC quiescent current, allows very low input power
consumption in no load and light load, while the low DRAIN peak current value, IDLIM_PFM, prevents any audible
noise which could arise from low switching frequency values. When the load is increased, VCOMP increases and
PFM is exited. VCOMP reaches its maximum at VCOMPH and corresponding to that value, the DRAIN current
limitation (IDLIM) is reached.
5.11 Zero power mode
The zero-power mode (ZPM) is a special idle state of VIPer0P, characterized by the following features:
• there is no switching activity, then neither voltage nor power, available at the output
• the HV current source charges VCC at 13 V and does not perform its usual functions
• all IC circuits, except the ones needed to exit ZPM, are turned off, reducing the controller consumption to
very low values
The IC enters ZPM if OFF is forced to SGND for more than tDEB_OFF (10 ms, typ.), the IC exits ZPM if ON is
forced to SGND for a more than tDEB_ON (20 μs, typ.).
The ZPM can be managed manually or by a microcontroller (MCU) or in mixed mode. In case of mixed ZPM
management (see Figure 29. ZPM managed in mixed mode) the MCU supervising the operation of the appliance
shuts down the SMPS by pulling low OFF through one of its GPIOs, cutting also its own supply voltage. The
restart is commanded by a pushbutton or a tactile switch pressed by the user that directly operates pin ON. For
safety reasons, this switch should operate at low voltage (SELV level). The MCU wakes up after the SMPS is
again up and running. This arrangement provides the minimum consumption from the power line.
In case of ZPM management by MCU only (see Figure 30. ZPM fully managed by MCU) the MCU shuts down the
SMPS by pulling low OFF and wakes it up as well by pulling low ON. Two of its GPIOs are used. The MCU is
powered also during ZPM using the resistive pull-up available at ON (RON, 45 kΩ typical), provided that it is rated
for 3.3 V supply voltage, and equipped with an ultra-low consumption Standby Mode.
Since in ZPM the device is supplied with extremely low current, it is naturally prone to pick up noise. If the device
is required to work in a noisy environment, it is recommended to connect a film capacitor (tens to some hundreds
pF) across ON and OFF versus SGND. If the device is disconnected from the mains or there is a mains
interruption while in ZPM, the information in the logic is lost. When the input source is applied again, the IC will be
restarted in normal mode.
The ultimate aim of ZPM function is to enable the realization of PSUs able to comply with the European regulation
1275/2008 as far as the standby and off-mode power consumption of appliances is concerned. To meet this target
a careful system-level design is required.
The total input consumption is therefore reduced to the residual consumption lower than 4 mW at 230 VAC that
can be rounded to zero based on the IEC62301 that sets to 10 mW the minimum accuracy of the standby power
measurements.
VIPer0P
Zero power mode
DS11301 - Rev 3 page 17/36
Figure 29. ZPM managed in mixed mode
VIPer0P
OFF
MCU
VAUX
GPIO
ON
Power-ON
Active low output
CB
GIPD280420151131MT
Figure 30. ZPM fully managed by MCU
VIPer0P
Active low
outputs
ON VAUX
OFF
Power-ON/OFF
45 kW
4 V
MCU
GPIO
GPIO
CB
GIPD250820151513FSR
5.12 Overload protection (OLP)
In order to manage the overload condition the IC embeds the following main blocks: the OCP comparator to turn
off the power MOSFET when the drain current reaches its limit (IDLIM), the up and down OCP counter to define
the turn off delay time in case of continuous overload (tOVL = 50 ms typ.) and the timer to define the restart time
after protection tripping (tRESTART = 1 sec, typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than
the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn off of
the power switch will be triggered by the OCP comparator instead of by the PWM comparator. Every cycle this
condition is met, the OCP counter is incremented and if the fault condition persists for a time greater than tOVL
(corresponding to the counter end-of-count), the protection is tripped, the PWM is disabled for tRESTART, then it
resumes switching with soft-start and, if the fault is still present, it is disabled again after tOVL. The OLP
management prevents that the IC could be indefinitely operated at IDLIM and the low repetition rate of the restart
attempts of the converter avoids overheating the IC in case of repeated fault events.
After the fault removal, the IC resumes working normally. If the fault is removed before the protection tripping
(before tOVL), the tOVL-counter is decremented on a cycle-by-cycle basis down to zero and the protection is not
tripped. If the fault is removed during tRESTART, the IC waits for that the tRESTART period has elapsed before
resuming switching.
In fault condition the VCC ranges between VCSon and VCCon levels, due to the periodical activation of the HV
current source recharging the VCC capacitor.
VIPer0P
Overload protection (OLP)
DS11301 - Rev 3 page 18/36
Figure 31. Overload condition
time
VCC
VCCon
VCSon
IDRAIN
IDLIM
tOVL
tRESTART
tSS
tOVL
Overload occurs
tSS
time
Overload removed
tRESTART
GIPD270420151208MT
5.13 Max. duty cycle counter protection
The IC embeds a max duty-cycle counter, which disables the PWM if the MOSFET is turned off by max duty cycle
(70% min, 80% max) for ten consecutive switching cycles. After protection tripping, the PWM is stopped for
tRESTART and then activated again with soft-start phase until the fault condition is removed.
In some cases (i.e. breaking of the loop) even if VCOMP is saturated high, the OLP cannot be triggered because at
every switching cycle the PWM is turned off by maximum duty cycle before the DRAIN peak current can reach the
IDLIM setpoint. As a result, the output voltage VOUT could increases out of control and be maintained indefinitely at
much higher value than nominal one with risk for the output capacitor, the output diode and the IC itself. The max
duty cycle counter protection prevents this kind of failures.
5.14 VCC clamp protection
This protection can be invoked when the IC is supplied by auxiliary winding or diode from the output voltage,
when an output over-voltage produces an increase of VCC.
If VCC reaches the clamp level VCCclamp (30 V, min. referred to EAGND) the current injected into the pin is
monitored and if it exceeds the internal threshold Iclamp_max (30 mA, typ.) for more than tclamp_max (5 ms, typ.), the
PWM is disabled for tRESTART (1 sec, typ.) and then activated again with soft-start phase. The protection is
disabled during the soft-start time.
5.15 Thermal shutdown
If the junction temperature becomes higher than the internal threshold TSD (160 °C, typ.), the PWM is disabled.
After tRESTART time, a single switching cycle is performed, during which the temperature sensor embedded in the
Power MOSFET section is checked. If a junction temperature above TSD is still measured, the PWM is maintained
disabled for tRESTART time, otherwise it resumes switching with soft-start phase.
During tRESTART VCC is maintained between VCSon and VCCon levels by the HV current source periodical
activation. Such a behavior is summarized in Figure 32. Thermal shutdown timing diagram.
VIPer0P
Max. duty cycle counter protection
DS11301 - Rev 3 page 19/36
Figure 32. Thermal shutdown timing diagram
time
time
VCC
VCCon
VCS on
I
DRAIN
IDLIM
tRES TART
TJ> TS D TJ< TSD
IP EAK
tRES TART
tSS
GIPD270420151404MT
VIPer0P
Thermal shutdown
DS11301 - Rev 3 page 20/36
6Application information
6.1 Typical schematics
Figure 33. Flyback converter (non-isolated)
optional if Vout >= 5V
Vout
GND
~ AC
Cout
Da ux
T
Rin
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
Rcl
C1
Din
Cs
Cin
Ccl
R2
R1
Dout
GIPD030920151438MT1609
Figure 34. Negative output flyback converter (non-isolated)
optiona l
nega tive rail
Vout (< 0V)
GND
~ AC
R1
Cin
Din
Cs
Ccl
T
Rcl
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
C1
Dout
R2
Cout
Rin
Daux
GIPD030620151439MT
VIPer0P
Application information
DS11301 - Rev 3 page 21/36
Figure 35. Isolated flyback converter with secondary feedback
optiona l
Vout
GND
~ AC Dout
R1
Rin
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0 P
OPTO
C1
Rcl
Ccl
OPTO
Da u x
Cs
T
Cout
Cin
R2
Din
GIPD150920151017MT
Figure 36. Primary side regulation isolated flyback converter
~ AC Vout
GND
Cin
Din
R1
Rcl
R2 C1
T
Ccl
Cs
Cout
Daux
Rin
Dout
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
GIPD030920151441MT
VIPer0P
Typical schematics
DS11301 - Rev 3 page 22/36
Figure 37. Buck converter (positive output)
optional if Vout >= 5V
~ AC
Vout
Din
Cin
Lout
Daux
C2
R2
Cout
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
R1
D
C1
Dout
Rin
Cs
GIPD030920151442MT
Figure 38. Buck-boost converter (negative output)
optiona l if IVoutI >= 5V
~ AC
Vout (< 0V)
Din
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
C2
Cin
Rin
Daux
D
C1
Lout
R1
Dout
Cs
R2
Cout
GIPD030920151443MT
6.2 Example of ZPM management using MCU
Sometimes the SMPS provides a -5 V bus for instance to enable triac driving to control the motor of a washing
machine. In this case, not to generate an additional +5 V bus, the ground of the MCU can be connected to the -5
V bus and its positive supply voltage to the ground of SMPS and VIPer0P. This connection requires an interface
circuit realizing a level shifting to properly drive ON and OFF, like the one shown in the Figure 39. Example of
interfacing the VIPer0P to a MCU supplied from a negative rail . During ZPM the MCU is supplied through ON, but
a linear regulator is needed in between, in order to avoid that during normal operation the AMR of the MCU is
exceeded.
VIPer0P
Example of ZPM management using MCU
DS11301 - Rev 3 page 23/36
Figure 39. Example of interfacing the VIPer0P to a MCU supplied from a negative rail
0 V
-5 V
EAGND GND
ON OFF
VCC
GND
GPIO
220 pF
56 kW
MCU
VIPer0P
220 pF
GPIO
56 kW
LDO
GIPD250820151541FSR
6.3 Energy saving performances
VIPer0P allows designing applications compliant with the most stringent energy saving regulations. In order to
show the typical performances achievable, the active mode average efficiency and the efficiency at 10% of the
rated output power of a single output flyback converter using VIPer0P have been measured and are reported in
Table 9. In addition, ZPM, no-load and light load consumptions are shown in the below tables and Figure 40. PIN
versus VIN in ZPM and no load and Figure 41. PIN versus VIN in light load.
Table 9. Power supply efficiency, VOUT = 12 V
VIN 10% output load efficiency [%] Active mode average efficiency [%]
115 VAC 78.0 80.9
230 VAC 71.1 81.0
Table 10. Input power consumption
VIN PIN in ZPM [mW] PIN @ no-load [mW]
115 VAC 0.8 6.5
230 VAC 3.3 9.0
VIPer0P
Energy saving performances
DS11301 - Rev 3 page 24/36
Figure 40. PIN versus VIN in ZPM and no load
GIPD160720151022MT
0
2
4
6
8
10
12
14
90 115 150 180 230 265
PIN [ mW]
VIN [VAC]
no load
ZPM
Figure 41. PIN versus VIN in light load
GIPD160720151023MT
0
50
100
150
200
250
300
350
400
90 115 150 180 230 265
PIN [ mW]
VIN [VAC]
POUT = 250 mW
POUT = 50 mW
POUT = 25 mW
6.4 Layout guidelines and design recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is
true for the VIPer0P as well. The main reasons to have a proper PCB layout are:
• Provide clean signals to the IC, ensuring good immunity against external noises and switching noises
• Reduce the electromagnetic interferences, both radiated and conducted, to pass more easily the EMC
When designing a SMPS using VIPer0P, the following basic rules should be considered:
•Separating signal from power tracks: generally, traces carrying signal currents should run far from others
carrying pulsed currents or with quickly swinging voltages. Signal ground traces should be connected to the
IC signal ground, SGND, using a single "star point", placed close to the IC. Power ground traces should be
connected to the IC power ground, PGND. SGND and PGND are then to be connected to each other with
the shortest track as possible. The compensation network should be connected to the COMP, maintaining
the trace to SGND as short as possible. In case of two layer PCB, it is a good practice to route signal traces
on one PCB side and power traces on the other side.
•Filtering sensitive pins: some crucial points of the circuit need or may need filtering. A small high-
frequency bypass capacitor to SGND might be useful to get a clean bias voltage for the signal part of the IC
and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to 0.1
μF) should be connected across VCC and SGND, placed as close as possible to the IC. With flyback
topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary
return and then to the main GND using a single track. In case of nosy environment, it is strongly
recommended to filter ON and OFF with small ceramic capacitors (tens to hundreds pF) connected to
SGND, in order to improve the system noise immunity.
•Keep power loops as confined as possible: minimize the area circumscribed by current loops where high
pulsed currents flow, in order to reduce its parasitic self-inductance and the radiated electromagnetic field:
this will greatly reduce the electromagnetic interferences produced by the power supply during the switching.
In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch,
VIPer0P
Layout guidelines and design recommendations
DS11301 - Rev 3 page 25/36
the power transformer, the one including the snubber, the one including the secondary winding, the output
rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk
capacitor, the power switch, the power inductor, the output capacitor and the free-wheeling diode.
•Reduce line lengths: any wire will act as an antenna. With the very short rise times exhibited by EFT
pulses, any antenna has the capability of receiving high voltage spikes. By reducing line lengths, the level of
radiated energy that is received will be reduced, and the resulting spikes from electrostatic discharges will be
lower. This will also keep both resistive and inductive effects to a minimum. In particular, all of traces
carrying high currents, especially if pulsed (tracks of the power loops) should be as short and fat as possible.
•Optimize track routing: as levels of pickup from static discharges are likely to be greater closer to the
extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines
will often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as
possible where applicable. Since vias are to be considered inductive elements, it is recommended to
minimize their number in the signal path and avoid them when designing the power path.
•Improve thermal dissipation: an adequate copper area has to be provided under the DRAIN pins as heat
sink, while it is not recommended to place large copper areas on the SGND and PGND.
Figure 42. Recommended routing for flyback converter
~ AC Vout
GND
Rcl
Dout
Ccl
Cs
Cout
Cin
Daux
R1
C1
OPTO
R2
OPTO
Din
T
Rin
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
GIPD030920151537MT
VIPer0P
Layout guidelines and design recommendations
DS11301 - Rev 3 page 26/36
Figure 43. Recommended routing for buck converter
~ AC
Vout
COMP FB
DRAIN
PGND
CONTROL
SGND
ON
OFF
VCC
EAGND
VIPER0P
Cs
C2
Din
C1
D
Cin
R1
Rin1
R2
Lout
Cout
Dout
Daux
GIPD030920151538MT
VIPer0P
Layout guidelines and design recommendations
DS11301 - Rev 3 page 27/36
7Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.1 SO16N package information
Figure 44. SO16N package outline
VIPer0P
Package information
DS11301 - Rev 3 page 28/36
Table 11. SO16N mechanical data
Dim.
mm
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
VIPer0P
SO16N package information
DS11301 - Rev 3 page 29/36
8Ordering information
Table 12. Order codes
Order code Package Packing FOSC ± jitter
VIPER0PLD
SO16N
Tube
60 kHz ±7%
VIPER0PHD 120 kHz ±7%
VIPER0PLDTR
Tape and reel
60 kHz ±7%
VIPER0PHDTR 120 kHz ±7%
VIPer0P
Ordering information
DS11301 - Rev 3 page 30/36
Revision history
Table 13. Document revision history
Date Revision Changes
18-Aug-2015 1 Initial release
12-Apr-2016 2 Updated Table 4: "Avalanche characteristics", Table 6: "Supply section" and Table 7: "Controller
section".Minor text changes.
01-Oct-2018 3 Updated VOFF and VON values in Table 7. Controller section
VIPer0P
DS11301 - Rev 3 page 31/36
Contents
1Description ........................................................................2
2Pin setting.........................................................................3
3Electrical and thermal ratings ......................................................4
3.1 Electrical characteristics.........................................................5
4Typical electrical characteristics ...................................................8
5General description...............................................................12
5.1 Block diagram ................................................................12
5.2 Typical power capability ........................................................12
5.3 Primary MOSFET .............................................................12
5.4 High voltage startup ...........................................................12
5.5 Soft startup...................................................................14
5.6 Oscillator ....................................................................15
5.7 Pulse skipping ...............................................................15
5.8 Direct feedback ..............................................................16
5.9 Secondary feedback ...........................................................16
5.10 Pulse frequency modulation.....................................................16
5.11 Zero-power mode .............................................................17
5.12 Overload protection (OLP) ......................................................18
5.13 Max. duty cycle counter protection ...............................................19
5.14 VCC clamp protection..........................................................19
5.15 Thermal shutdown.............................................................19
6Application information...........................................................21
6.1 Typical schematics ............................................................21
6.2 Example of ZPM management using MCU ........................................23
6.3 Energy saving performances ....................................................24
6.4 Layout guidelines and design recommendations ...................................25
7Package information..............................................................28
7.1 SO16N package information ....................................................28
8Ordering information .............................................................30
VIPer0P
Contents
DS11301 - Rev 3 page 32/36
List of tables
Table 1. Pin description......................................................................3
Table 2. Absolute maximum ratings .............................................................4
Table 3. Thermal data.......................................................................4
Table 4. Avalanche characteristics ..............................................................4
Table 5. Power section ......................................................................5
Table 6. Supply section......................................................................6
Table 7. Controller section....................................................................6
Table 8. Typical power ..................................................................... 12
Table 9. Power supply efficiency, VOUT = 12 V ..................................................... 24
Table 10. Input power consumption ............................................................. 24
Table 11. SO16N mechanical data .............................................................. 29
Table 12. Order codes ...................................................................... 30
Table 13. Document revision history ............................................................. 31
VIPer0P
List of tables
DS11301 - Rev 3 page 34/36
List of figures
Figure 1. Basic application schematic ...........................................................1
Figure 2. Connection diagram ................................................................3
Figure 3. IDLIM vs TJ .......................................................................8
Figure 4. ION vs VON ......................................................................8
Figure 5. FOSC vs TJ ......................................................................8
Figure 6. VHV_START vs TJ ..................................................................8
Figure 7. VFB_REF vs TJ ....................................................................8
Figure 8. Quiescent current Iq vs TJ ............................................................8
Figure 9. Operating current ICC vs TJ ...........................................................9
Figure 10. ICOMP vs TJ ......................................................................9
Figure 11. ICH1 vs TJ .......................................................................9
Figure 12. ICH1 vs VDRAIN ....................................................................9
Figure 13. ICH2 vs TJ .......................................................................9
Figure 14. ICH2 vs VDRAIN ....................................................................9
Figure 15. ICH3 vs TJ ...................................................................... 10
Figure 16. ICH3 vs VDRAIN ................................................................... 10
Figure 17. GM vs TJ ....................................................................... 10
Figure 18. RDS(on) vs TJ .................................................................... 10
Figure 19. Static drain source on resistance ...................................................... 10
Figure 20. Output characteristic ............................................................... 10
Figure 21. VBVDSS vs TJ .................................................................... 11
Figure 22. Max avalache energy vs TJ .......................................................... 11
Figure 23. SOA SO16N package .............................................................. 11
Figure 24. Block diagram ................................................................... 12
Figure 25. IC supply modes: self-supply and external supply ........................................... 13
Figure 26. Power-ON and power-OFF........................................................... 14
Figure 27. Soft startup ..................................................................... 14
Figure 28. Pulse skipping during start-up for FOSC = 60 kHz ........................................... 16
Figure 29. ZPM managed in mixed mode ........................................................ 18
Figure 30. ZPM fully managed by MCU.......................................................... 18
Figure 31. Overload condition ................................................................ 19
Figure 32. Thermal shutdown timing diagram...................................................... 20
Figure 33. Flyback converter (non-isolated) ....................................................... 21
Figure 34. Negative output flyback converter (non-isolated) ............................................ 21
Figure 35. Isolated flyback converter with secondary feedback.......................................... 22
Figure 36. Primary side regulation isolated flyback converter ........................................... 22
Figure 37. Buck converter (positive output) ....................................................... 23
Figure 38. Buck-boost converter (negative output) .................................................. 23
Figure 39. Example of interfacing the VIPer0P to a MCU supplied from a negative rail ......................... 24
Figure 40. PIN versus VIN in ZPM and no load ..................................................... 25
Figure 41. PIN versus VIN in light load ........................................................... 25
Figure 42. Recommended routing for flyback converter ............................................... 26
Figure 43. Recommended routing for buck converter ................................................ 27
Figure 44. SO16N package outline ............................................................. 28
VIPer0P
List of figures
DS11301 - Rev 3 page 35/36
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
VIPer0P
DS11301 - Rev 3 page 36/36
