512 x 8 Registered PROM
CY7C225A
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-04001 Rev. *C Revised August 16, 2006
Features
• CMOS for optimum speed/power
• High speed
— 25 ns address set-up
— 12 ns clock to outpu t
• Low power
— 495 mW (Commercial)
— 660 mW (Military)
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Buffered common PRESET and CLEAR inputs
• EPROM technology, 100% programmable
• Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or
28-pin PLCC
•5V± 10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C225A is a high-performance 512-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, and 28-pin PLCC. The memory cells utilize proven
EPROM floating gate technology and byte-wide intelligent
programming algorithms.
The CY7C225A replaces bipolar devices and offers the advan-
tages of lower power, superior performance, and high
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that
after customer programming the product will meet AC specifi-
cation limits.
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A8
PS
E
CLR
CP
O7
O6
O4
O5
O3
PROGRAMMABLE
ARRAY MULTIPLEXER
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O7
O6
O5
O4
O3
O2
O1
O0
PS
CLR
SRCP
CP
ES
E
ES
28
4
5
6
7
8
9
10
321 27
13
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3
E
NC
NC
NC
CLR
ES
O7
O6
A2
A1CP
O2
A8
PS
DIP
LCC/PLCC
Top View
Top View
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A7COLUMN
ADDRESS
ROW
ADDRESS
14151617
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CY7C225A
Document #: 38-04001 Rev. *C Page 2 of 10
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input V oltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide
7C225A-25 7C225A-30 7C225A-40 Unit
Minimum Address Se t-Up Time 25 30 40 ns
Maximum Clock to Output 12 15 25 ns
Maximum Operating
Current Commercial 90 90 mA
Military 120 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Military[2] −55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range[3,4]
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., I OH = −4.0 mA
VIN = VIH or VIL 2.4 V
VOL Output LOW Voltage VCC = Min., I OL = 16 mA
VIN = VIH or VIL 0.4 V
VIH Input HIGH Level Guaranteed Input Logi cal HIGH Voltage for
All Inputs 2.0 V
VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All
Inputs 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 µA
VCD Input Clamp Diode Voltage Note 4
IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled[5] −10 +10 µA
IOS Output Short Circuit Current VCC = Max., VOUT = 0.0V[6] −20 −90 mA
ICC Power Supply Cu rrent IOUT = 0 mA
VCC = Max. Commercial 90 mA
Military 120
VPP Programming Supply V oltage 12 13 V
IPP Programming Supply Current 50 mA
VIHP Input HIGH Programming
Voltage 3.0 V
VILP Input LOW Programming
Voltage 0.4 V
Notes
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on test ing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltage s to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 se conds.
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CY7C225A
Document #: 38-04001 Rev. *C Page 3 of 10
Operating Modes
The CY7C225A incorporates a D-type, master-slave regi ster
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Addi tional flexibility is
provided with synchronous (ES) and asynchronous (E) output
enables and CLEAR and PRESET inputs.
Upon power-up, the synchronous ena ble (ES) flip-flop will be
in the set condition ca using the outputs (O0−O7) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address inputs (A0−A8) and a logic
LOW to the enable (ES) input. The stored data is accessed and
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O0−O7) provided the asynchronous enable (E) is
also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the en able to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the synchronous enable (ES) input is switched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW ,
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock e dge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C225A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-trig gered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C225A has buffered asynchronous CLEAR and
PRESET inputs. Applying a LOW to the PRESET input causes
an immediate load of all ones into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). Applying a LOW to the CLEAR input,
resets the flip-flops to all zeros. The i nitialize data will appea r
at the device outputs after the outputs are enabled by bringing
the asynchronous enable (E) LOW.
When power is applied, the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impeda nce state. In order to enable the outputs, a clock
must occur and the ES input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC =5.0V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms[4]
3.0V
5V
OUTPUT
R1 250Ω
R2
167Ω
50 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10%
90%
10%
<5ns < 5 ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(b) High Z Load
OUTPUT 2.0V
Equivalent to: THÉ VENINEQUIVALENT
100Ω
R1 250Ω
(a) NormalLoad
R2
167Ω
ALL INPUT PULSES
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CY7C225A
Document #: 38-04001 Rev. *C Page 4 of 10
Switching Characteristics Over the Operating Range[3,4]
7C225A-25 7C225A-30 7C225A-40 Unit
Parameter Description Min. Max. Min. Max. Min. Max.
tSA Address Set-Up to Clock HIGH 25 30 40 ns
tHA Address Hold from Clock HIGH 0 0 0 ns
tCO Clock HIGH to Valid Output 12 15 25 ns
tPWC Clock Pulse Width 10 15 20 ns
tSES ES Set-Up to Clock HIGH 10 10 10 ns
tHES ES Hold from Clock HIGH 0 5 5 ns
tDP, tDC Delay from PRESET or CLEAR
to Valid Output 20 20 20 ns
tRP, tRC PRESET or CLEAR Recovery to
Clock HIGH 15 20 20 ns
tPWP, tPWC PRESET or CLEAR Pulse Width 15 20 20 ns
tCOS Valid Output from Clock HIGH[7] 20 20 30 ns
tHZC Inactive Output from Clock
HIGH[7] 20 20 30 ns
tDOE Valid Output from E LOW 20 20 30 ns
tHZE Inactive Output from E HIGH 20 20 30 ns
Switching Waveforms[4]
tDP
tDC
tCO tDOE
tHZE
tHZC
tSA tHA
tPWC
tHES
tPWC
tPWC tPWC
tPWC tPWC
tSES
tHA
tCO tCOS
O0−O7
A0−A10
PSor CLR
CP
ES
E
tRP
,t
RC
tPWP
tPWC
tHES
tSES tHES
tSES
Note
7. Applies only when the synchronous (ES) function is used.
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CY7C225A
Document #: 38-04001 Rev. *C Page 5 of 10
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Figure 1. Programming Pinouts
Table 1. Mode Selection
Pin Function[8]
Read or Output Disable A8–A0CP ESCLR EPS O7−O0
Mode Other A8–A0PGM VFY VPP EPS D7−D0
Read A8–A0X VIL VIH VIL VIH O7−O0
Output Disable A8–A0X VIH VIH X VIH High Z
Output Disable A8–A0X X VIH VIH VIH High Z
Clear A8–A0X VIL VIL VIL VIH Zeros
Preset A8–A0X VIL VIH VIL VIL Ones
Program A8–A0VILP VIHP VPP VIHP VIHP D7−D0
Program Verify A8–A0VIHP VILP VPP VIHP VIHP O7−O0
Program Inhibit A–A0VIHP VIHP VPP VIHP VIHP High Z
Intelligent Program A8–A0VILP VIHP VPP VIHP VIHP D7−D0
Blank Check A8–A0VIHP VILP VPP VIHP VIHP Zeros
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
D7
D6
D4
D5
D3
15
PS
E
VPP
VFY
PGM
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
V
CC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0
A4
A3
A8
NC
NC
D7
D6
A2
A1
D2
E
VPP
VFY
PGM
NC
PS
DIP LCC/PLCC
Top View Top View
Note
8. X = “don’t care” but not to exceed VCC ±5%.
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CY7C225A
Document #: 38-04001 Rev. *C Page 6 of 10
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
1.6
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK–TO–OUTPUT TIME
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C) SUPPLYVOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. VCC
0.6
1.2
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-U P TIME
AMBIENT TEMPERATURE (°C)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I
CC
NORMALIZED I
CC
VCC =5.0V
TA=25°C
TA=25°C
0.6
0.6
1.02
1.00
0.98
0.96
0.94
0.92
025 5075
CLOCK PERIOD (ns)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
100 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
25
0.88
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
4.0
1.4
1.2
1.0
0.8
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED SET-UP
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK-TO-OUTPUT TIME
0.4
SUPPLYVOLTAGE (V)
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
TA=25°C
1.0
0.8
0.6
NORMALIZED I
CC
0.90
VCC =5.5V
TA=25°C
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CY7C225A
Document #: 38-04001 Rev. *C Page 7 of 10
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
Speed
(ns) Ordering
Code Package
Type Package
Type Operating
Range
tSA tCO
25 12 CY7C225A-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
tDP 7, 8, 9, 10, 11
tRP 7, 8, 9, 10, 11
Package Diagrams
Figure 2. 28-Lead Pla stic Leaded Chip Carrier J64
51-85001-*A
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CY7C225A
Document #: 38-04001 Rev. *C Page 9 of 10
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic on duct or Cor po rati on assu me s no resp onsi b i lity f or th e u s e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significan t injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 4. 24-Lead (300-Mil) PDIP P13
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (Continued)
51-85013-*B
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CY7C225A
Document #: 38-04001 Rev. *C Page 10 of 10
Document History Page
Document Title: CY7C225A 512 x 8 Registered PROM
Document Number: 38-04001
REV. ECN NO. Issue
Date Orig. of
Change Description of Chang e
** 113858 03/06/02 DSG Changed from Spec number: 38-00228 to 38-04001
*A 118892 10/09/02 GBI Updated ordering information
*B 122242 12/27/02 RBI Added power up requi rements to Maximum Ratings Information
*C 499538 See ECN PCI Updated ordering information
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