IDT70T651S8BF8 - Integrated Device Technology

DSC-5632/6



256/128K x 36

MEMORY

ARRAY

Address

Decoder A

17R(1)

Address

Decoder

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

I/O

0L-

I/O

35L

17L(1)

I/O

0R -

I/O

35R

Di n_L

ADDR_L

Di n_R

ADDR_R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEM

INT

L(3)

BUSY

L(2,3)

M/S

R/W

BUSY

R(2,3)

SEM

INT

R(3)

4869 drw 01

CONTROL

LOGIC

L(4)

R(4)

JTAG

TC K

TRST

TMS

TDI

TD O

Functional Block Diagram

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆◆

◆Sleep Mode Inputs on both ports

◆◆

◆Supports JTAG features compliant to IEEE 1149.1

◆◆

◆Single 2.5V (±100mV) power supply for core

◆◆

◆LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

◆◆

◆Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Features

◆◆

◆True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆◆

◆High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

◆◆

◆RapidWrite Mode simplifies high-speed consecutive write

cycles

◆◆

◆Dual chip enables allow for depth expansion without

external logic

◆◆

◆IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

◆◆

◆M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

◆◆

◆Busy and Interrupt Flags

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

IDT70T651/9S

NOTES:

1. Address A17x is a NC for IDT70T659.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4 . The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

◆◆

◆Green parts available, see ordering information

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous

Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a

stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-

TER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the

IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider

memory system applications results in full-speed, error-free operation

without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE0 or CE1) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T651/9 has a RapidWrite Mode which allows the designer

to perform back-to-back write operations without pulsing the R/W input

each cycle. This is especially significant at the 8 and 10ns cycle times of

the IDT70T651/9, easing design considerations at these high perfor-

mance levels.

The 70T651/9 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controlled by the OPT pins. The power supply for

the core of the device (VDD) is at 2.5V.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3)

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

3. All VSS pins must be connected to ground supply.

4. A17X is a NC for IDT70T659.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

70T651/9BC

BC-256(5,6)

256-Pin BGA

Top View

E16

I/O14R

D16

I/O16R

C16

I/O16L

B16

A16

A15

B15

I/O17L

C15

I/O17R

D15

I/O15L

E15

I/O14L

E14

I/O13L

D14

I/O15R

D13

VDD

C12

A6L C14

OPTL

B14

A14

A0L

A12

A5L

B12

A4L

C11

BUSY

D12

VDDQR

D11

VDDQR

C10

SEML

B11

A11

INTL

VDDQR

BE1L

CE1L

VDDQL

BE0L

CE0L

D10

VDDQL

A7L

BE3L

BE2L

B13

A1L

A13

A2L

A10

OEL

VDDQR

A9L

A8L

A12L

A10L

VDDQL

A14L

A15L

A13L

VDDQL

A17L(4)

A16L

VDD

TDO

VSS

I/O20L

I/O19R

I/O19L

TDI

I/O18L

I/O18R

I/O20R

I/O21R

I/O21L

I/O22L

VDDQL

I/O23L

I/O22R

I/O23R F4

VDDQL

I/O24R G2

I/O24L G3

I/O25L

VDDQR

I/O26L

I/O25R

I/O26R

VDDQR

I/O27L J2

I/O28R J3

I/O27R J4

VDDQL

I/O29R

I/O29L K3

I/O28L

VDDQL

I/O30L

I/O31R

I/O30R

VDDQR

I/O32R M2

I/O32L M3

I/O31L M4

VDDQR

I/O33L

I/O34R

I/O33R

VDD

I/O35R P2

I/O34L P3

TMS P4

A16R

I/O35L

NC R3

TRST

R4NC

NC T2

TCK T3NC T4

A17R(4)

A13R

A15R

P12

A6R

BE1R P9

BE0R

BE3R

BE2R

P10

SEMR

T11

INTR

P11

BUSY

R12

A4R

T12

A5R

P13

A3R

A7R

R13

A1R

T13

A2R

A12R

A14R T14

A0R

R14

OPTR

P14

I/O0L P15

I/O0R

R15

T15

NC T16

R16

P16

I/O1L

N16

I/O2R

N15

I/O1R

N14

I/O2L

M16

I/O4L

M15

I/O3L

M14

I/O3R

L16

I/O5R

L15

I/O4R

L14

I/O5L

K16

I/O7L

K15

I/O6L

K14

I/O6R

J16

I/O8L

J15

I/O7R

J14

I/O8R

H16

I/O10R

H15

IO9L

H14

I/O9R

G16

I/O11R

G15

I/O11L

G14

I/O10L

F16

I/O12L

F14

I/O12R

F15

I/O13R

CE0R

R11

M/S

A11R

CE1R

A11L

B10

R/WL

C13

A3L

A10R

R10

R/WR

A9R

T10

OER

A8R

VDD

VSS

E10

VSS

E11

VDD

E12

VDD

E13

VDDQR

VDD F6

NC F8

VSS

VSS F10

VSS F12

VDD

F13

VDDQR

VSS G6

VSS G7

VSS

VSS G10

VSS G11

VSS

G12

VSS

G13

VDDQL

VSS H6

VSS

VSS H8

VSS H9

VSS H10

VSS

H11

VSS H12

VSS

H13

VDDQL

ZZRJ6

VSS

VSS J10

VSS

J11

VSS

J12

ZZL

J13

VDDQR

VSS

VSS K7

VSS

VDD

L6NC L7

VSS

VDD

VSS

VDDQR N6

VDDQR N7

VDDQL

VSS

K10

VSS K11

VSS

K12

VSS

L10

VSS

L11

VSS

L12

VDD

VSS

M10

VSS

M11

VDD

M12

VDD

VDDQR N10

VDDQR N11

VDDQL

N12

VDDQL

K13

VDDQR

L13

VDDQL

M13

VDDQL

N13

VDD

VSS F11

VSS

5632 drw 02f

03/18/03

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is

set to VSS (0V).

3. All VSS pins must be connected to ground.

4. A17X is a NC for IDT70T659.

5. Package body is approximately 28mm x 28mm x 3.5mm.

6. This package code is used to reference the package diagram.

7. 8ns Commercial and 10ns Industrial speed grades are not available in the DR-208 package.

8. This text does not indicate orientation of the actual part-marking.

100

101

102

103

104

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

70T651/9DR

DR-208

(5,6,7)

208-Pin

PQFP

Top View

(8)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

DDQL

I/O

35R

I/O

35L

TMS

TCK

TRST

17R(4)

16R

15R

14R

13R

12R

11R

10R

SEM

R/W

BUSY

INT

M/S

OPT

I/O

DDQL

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

DDQR

I/O

18R

I/O

18L

TDI

TDO

17L(4)

16L

15L

14L

13L

12L

11L

10L

SEM

R/W

BUSY

INT

OPT

I/O

17L

I/O

17R

DDQR

5632 drw 02d

03/18/03

Pin Configurations(1,2,3) (con't.)

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3)(con't.)

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is

set to VSS (0V).

3. All VSS pins must be connected to ground.

4. A17X is a NC for IDT70T659.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

1716

1412 13

9876543

21 11

I/O

19L

I/O

18L

INT

SEM

12L

16L

I/O

17L

OPT

I/O

20R

I/O

18R

BUSY

13L

17L(4)

I/O16L

DDQR

DDQL

I/O

19R

DDQR

10L

14L

NC I/O

15L

I/O

16R

I/O

22L

I/O

21L

I/O

20L

I/O

23L

I/O

22R

DDQR

I/O

21R

DDQL

I/O

23R

I/O

24L

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DDQR

I/O

25R

DDQL

I/O

29R

I/O

28L

DDQR

DDQL

I/O

29L

I/O

30R

I/O

14R

DDQL

I/O

14L

15L

11L

I/O

12L

I/O

13R

I/O

13L

I/O

12R

I/O

11L

I/O

DDQL

I/O

10L

I/O

11R

I/O

10R

DDQR

I/O

DDQL

I/O8R V

I/O

31L

I/O

31R

I/O

30L

16R

12R

SEM

INT

DDQR

I/O

33L

I/O

34R

13R

BUSY

DDQL

I/O

DDQR

I/O

33R

I/O

34L

DDQL

17R(4)

14R

10R

I/O

35L

15R

11R

DDQL

I/O

OPT

I/O

70T651/9BF

BF-208

(5,6)

208-Ball

fpBGA

Top View

(7)

5632 drw 02e

I/O

27L

I/O

28R

I/O

27R

I/O

32R

I/O

32L

DDQR

I/O

35R

I/O

17R

DDQR

I/O

15R

TDO

TDI

TCK

TMS

TRST

3/18/03

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. Address A17x is a NC for IDT70T659.

2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/OX.

3. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that

port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are

not affected during sleep mode. It is recommended that boundry scan not be

operated during sleep mode.

5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master

(M/S=VIH).

Left Port Right Port Names

Chip E nab l e s (Inp ut)

R/W

Re ad/Write Enab le (Input)

Output E nable (Input)

- A

17L

(1)

- A

17R

(1)

Ad dres s (Inp ut)

I/O

- I/O

35L

I/O

- I/ O

35R

Da ta Inpu t/ O utput

SEM

Se mapho re Enab le (Input)

INT

Inte rrup t Flag (Outp ut)

BUSY

B us y F lag (O utput)

- BE

B yte E nab l e s (9-b it b y te s ) (Inp ut)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(2)

(Input)

OPT

Op ti o n fo r s e le c ting V

DDQX

(2,3)

(Input)

Sleep Mode Pin

(4)

(Input)

M/SMaster o r S lave Se le ct (Input)

(5)

Power (2.5V)

(2)

(Input)

Gro und (0V) (Input)

TDI Tes t Da ta Inpu t

TDO Tes t Da ta Outpu t

TCK Te s t Lo g i c Cl o c k (10M Hz ) (Inp ut)

TMS Test Mode Select (Input)

TRST Res e t (Initiali z e TA P Co ntro l le r) (Input)

5632 tbl 0 1

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I—Read/Write and Enable Control(1,2)

OE SEM CE

R/WZZ Byte 3

I/O

27-35

Byte 2

I/O

18-26

Byte 1

I/O

9-17

Byte 0

I/O

0-8

MODE

X H H X X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down

X H X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down

X H L H H H H H X L Hig h-Z High-Z High-Z High-Z All Bytes Deselected

X H L H H H H L L L High-Z High-Z High-Z D

Wri te to By te 0 Only

X H L H H H L H L L High-Z High-Z D

High-Z Write to Byte 1 Only

XHLHHLHHLLHigh-Z D

High-Z High-Z Write to Byte 2 Only

XHLHLHHHLL D

Hig h-Z High-Z Hig h-Z Write to Byte 3 Only

X H L H H H L L L L High-Z High-Z D

Write to Lower 2 Bytes Only

XHLHLLHHLL D

High-Z High-Z Write to Upper 2 b ytes Only

XHLHLLLLLL D

Write to All Bytes

L H L H H H H L H L High-Z High-Z High-Z D

OUT

Re ad Byte 0 Only

LHLHHHLHHLHigh-ZHigh-ZD

OUT

High-Z Read By te 1 Only

LHLHHLHHHLHigh-ZD

OUT

Hig h-Z High-Z Re ad Byte 2 Only

LHLHLHHHHL D

OUT

Hig h-Z High-Z Hig h-Z Re ad Byte 3 Only

LHLHHHLLHLHigh-ZHigh-ZD

OUT

Read Lower 2 Bytes Only

LHLHLLHHHL D

OUT

Hig h-Z High-Z Re ad Upp er 2 By te s Only

LHLHLLLLHL D

OUT

Re ad All Bytes

H H L H L L L L X L Hig h-Z Hig h-Z High-Z High-Z Outputs Disab led

X X X X X X X X X H Hig h-Z Hig h-Z High-Z High-Z Hig h-Z Sleep Mod e

5632 tbl 02

Truth T able II – Semaphore Read/Write Control(1)

NOTES:

1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.

2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

3. Each byte is controlled by the respective BEn. To read data BEn = VIL.

Inputs

(1)

Outputs

Mode

(2)

R/WOE BE

SEM I/O

1-35

I/O

HHLLLLLLDATA

OUT

DATA

OUT

Read Data in S emap ho re Flag

(3)

H↑XXXXL L XDATA

Wri te I/O

into Semapho re Flag

LXXXXXXL

______ ______

Not All owe d

5632 tbl 03

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage(1)

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

Grade Ambient

Temperature GND V

Commercial 0

C to + 70

C0V2.5V

100m V

Industrial -40

C to +85

C0V2.5V

100m V

5632 tbl 04

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol Parameter Conditions

(2)

Max. Unit

Input Capacitance V

= 3dV 8 pF

OUT

(3)

Outp ut Cap ac itanc e V

OUT

= 3dV 10.5 pF

5632 tbl 08

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any Input or I/O pin cannot exceed VDDQ during power

supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

Recommended DC Operating

Conditions with VDDQ at 2.5V

Symbol Parameter Min. Typ. Max. Unit

Co re S up p l y Vo l tag e 2. 4 2. 5 2. 6 V

DDQ

I/O Supply Voltage

(3)

2.4 2.5 2.6 V

Ground 0 0 0 V

In p u t H igh Vol lta g e

(Address, Control &

D ata I/O Inpu ts )

(3)

1.7

____

DDQ

+ 100mV

(2)

In p u t H igh Vol tage

JTAG 1.7

____

+ 100m V

(2)

Input High Voltage -

ZZ, O PT, M/ SV

- 0.2V

____

+ 100m V

(2)

In p u t L o w Vol tage -0.3

(1)

____

0.7 V

Input Low Voltage -

ZZ, O PT, M/ S-0.3

(1)

____

0.2 V

5632 tbl 0 5

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

less.

3 . To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VSS(0V), and VDDQX for that port must be

supplied as indicated above.

Absolute Maximum Ratings(1)

Symbol Rating Commercial

& I nd ust ri al Unit

TERM

Te rm inal Vo l tag e

wi th Re s p e c t to GND -0.5 to 3.6 V

TERM

(2)

DDQ

Te rminal Vo ltage

wi th Re s p e c t to GND -0. 3 to V

DDQ

+ 0.3 V

TERM

(2)

(INP UTS and I/O ' s ) Inp ut an d I/ O Te rm in al

Voltage with Respect to GND -0. 3 to V

DDQ

+ 0.3 V

BIAS

(3)

Temperature

Under Bias -55 to + 125

STG

Storage

Temperature -65 to +150

J unc ti o n Te m p e rature + 150

OUT

(F o r V

DDQ

3.3V ) DC Output Current 50 mA

OUT

(F o r V

DDQ

2.5V ) DC Output Current 40 mA

5632 tb l 07

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

less.

3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be

supplied as indicated above.

Recommended DC Operating

Conditions with VDDQ at 3.3V

Symbol Parameter Min. Typ. Max. Unit

Co re Su p p l y Vo ltag e 2 . 4 2.5 2. 6 V

DDQ

I/O Sup ply Voltage

(3)

3.15 3.3 3.45 V

Ground 0 0 0 V

Inp ut H ig h Vo lta g e

(Ad d re s s, Co ntro l

& Data I/O Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

Inp ut H ig h Vo lta g e

JTAG 1.7

____

+ 1 00mV

(2)

Input High Voltag e -

ZZ, O P T, M / SV

- 0. 2V

____

+ 1 00mV

(2)

Inp ut Low Vo ltag e -0. 3

(1)

____

0.8 V

Inp ut L o w Vo l tag e -

ZZ, O P T, M / S-0.3

(1)

____

0.2 V

5632 tbl 06

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

T emperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

NOTES:

1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input

levels of GND to 3.3V.

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 100mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V.

"X" represents "L" for left port or "R" for right port.

6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.

7. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

70T651/9S8

(7)

Com 'l Onl y 70T651/9S10

Com'l

& Ind

(7)

70T651/9S12

Com'l

& I nd

70T651/9S15

Co m' l On l y

Symbol Parameter Test Condition Version Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Unit

Dy namic Op e rating

Current (Both

Ports Ac tiv e)

CEL and CER= V

Outp uts Disab led

f = f

MAX

(1)

COM'L S 350 475 300 405 300 355 225 305 mA

IND S

____ ____

300 445 300 395

____ ____

SB1

(6)

Stand by Curre nt

(B oth P o rts - TTL

Lev e l In p uts )

= CE

= V

f = f

MAX

(1)

COM'L S 115 140 90 120 75 105 60 85 mA

IND S

____ ____

90 145 75 130

____ ____

SB2

(6)

Stand by Curre nt

(One P o rt - TTL

Lev e l In p uts )

"A"

= V

and CE

"B"

= V

(5)

Active Po rt Outp uts Disab led ,

f = f

MAX

(1)

COM'L S 240 315 200 265 180 230 150 200 mA

IND S

____ ____

200 290 180 255

____ ____

SB3

Full Standb y Current

(B oth P o rts - CMOS

Lev e l In p uts )

Both Ports CE

and

> V

DDQ

- 0.2V,

> V

DDQ

- 0.2V o r V

< 0.2V,

f = 0

(2)

COM'LS210210210210

IND S

____ ____

220220

____ ____

SB4

(6)

Full Standb y Current

(One P o rt - CMO S

Lev e l In p uts )

"A"

< 0.2V and

"B"

> V

DDQ

- 0. 2V

(5)

> V

DDQ

- 0.2V o r V

< 0.2V,

Active Port, Outputs Disabled,

f = f

MAX

(1)

COM'L S 240 315 200 265 180 230 150 200 mA

IND S

____ ____

200 290 180 255

____ ____

Sleep Mode Current

(B oth P o rts - TTL

Lev e l In p uts )

L =

R =

f = f

MAX

(1)

COM'LS210210210210

IND S

____ ____

220220

____ ____

5632 t bl 10

Symbol Parameter Test Conditions

70T651/9S

UnitMin. Max.

| Inp ut Leak ag e Curr e nt

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

10 µA

| J TA G & ZZ Inp ut Le ak ag e Curre nt

(1,2)

DD =

Max.

= 0V to V

___

+30 µA

| Outp ut Le ak ag e Curre nt

(1,3)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

10 µA

(3. 3V ) Outp ut Lo w Vo ltag e

(1)

= +4mA, V

DDQ

= Min.

___

0.4 V

(3. 3V) Outp ut Hig h Vo ltag e

(1)

= -4mA, V

DDQ

= Mi n. 2. 4

___

(2. 5V ) Outp ut Lo w Vo ltag e

(1)

= +2mA, V

DDQ

= Min.

___

0.4 V

(2. 5V) Outp ut Hig h Vo ltag e

(1)

= -2mA, V

DDQ

= Mi n. 2. 0

___

5632 t b l 09

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC T est Conditions (VDDQ - 3.3V/2.5V)

Inp ut Puls e Lev els

Inp ut Ris e /Fal l Time s

Inp ut Ti mi ng Re fe re nce Le ve ls

Outp ut Refere nc e Le ve ls

Outp ut Lo ad

GND to 3. 0V / GND to 2.4V

2ns Max.

1.5V/1.25V

Figure 1

5632 tbl 11

Figure 1. AC Output Test load.

1.5V/1.25

50Ω

5632 drw 03

10pF

(Tester)

ATA

OUT

5632 drw 05

40 60 80 100 120 140

0160

0.5

1.5

2.5

3.5

∆

Capacitance (pF) from AC Test Load

∆

ACE

(

Typical, ns)

Figure 3. Typical Output Derating (Lumped Capacitive Load).

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when

CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(4)

Symbol Parameter

70T651/9S8

(5)

Com'l Only 70T651/9S10

Com'l

& I nd

(5)

70T651/9S12

Com'l

& I nd

70T651/9S15

Com'l Only

UnitMin. Max. Min. Max. Min. Max. Min. Max.

READ CYCLE

Re ad Cy c l e Tim e 8

____

Add re ss Access Time

____

15 ns

ACE

Chip Enable A cce ss Time

(3)

____

15 ns

ABE

Byte Enable A cce ss Time

(3)

____

7ns

AOE

Ou tput En abl e Ac ces s Tim e

____

7ns

Output Hold from Address Change 3

____

Outp ut Lo w-Z Time Chi p Enab le and Semapho re

(1,2)

____

LZOB

Outp ut Lo w-Z Time Outp ut Enabl e and B yte Enabl e

(1,2)

____

Outp ut Hig h-Z Time

(1,2)

03.5040608ns

Chi p E nab l e t o Powe r Up Ti me

(2)

____

Chi p Dis a bl e to Po we r Do wn Tim e

(2)

____

12 ns

SOP

Semaphore Flag Update Pulse (OE or SEM)

____

8ns

SAA

Semaphore Address Access Time 2 8 2 10 2 12 2 15 ns

SOE

Semaphore Output Enable Access Time

____

7ns

5632tbl 12

Symbol Parameter

70T651/9S8

(5)

Com ' l O nl y 70T651/9S10

Com'l

& I nd

(5)

70T651/9S12

Com'l

& I nd

70T651/9S15

Com'l Only

UnitMin. Max. Min. Max. Min. Max. Min. Max.

WR I T E C YC L E

Write Cycle Time 8

____

Chip Enab le to End -o f-Write

(3)

____

Address Valid to End-of-Write 6

____

Ad dre ss Se t-up Ti me

(3)

____

Write Puls e Wid th 6

____

Write Recovery Time 0

____

Data Valid to End-of-Write 4

____

Data Ho ld Time 0

____

Write Enabl e to Output i n Hig h-Z

(1,2)

____

3.5

____

8ns

Outp ut A c ti v e fro m E nd -of- Write

(1,2)

____

SWRD

SEM Flag Write to Read Time 4

____

SPS

SEM Flag Co nte ntio n Wind ow 4

____

5632 tb l 13

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing of Power-Up Power-Down

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE, CE or BEn.

2. Timing depends on which signal is de-asserted first CE, OE or BEn.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, tABE or tBDD.

5. SEM = VIH.

6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

R/W

ADDR

BEn

5632 drw 06

(4)

ACE

(4)

AOE

(4)

ABE

(4)

(1)

LZOB

(2)

(3,4)

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

(6)

5632 drw 07

50% 50%

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wa v eform of Write Cyc le No. 1, R/W Controlled Timing(1,5,8)

Timing Wa veform of Write Cycle No. 2, CE Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or BEn = VIH during all address transitions for Write Cycles 1 and 2.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

R/W

DATA

OUT

(2)

ADDRESS

DATA

(6)

(4) (4)

(7)

BEn

5632 drw 10

(9)

CE or SEM

(9)

(7)

(3)

(7)

5632 drw 11

ADDRESS

DATA

R/W

BEn

(3)

(2)

(6)

CE or SEM

(9)

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

RapidWrite Mode Write Cycle

Unlike other vendors' Asynchronous Random Access Memories,

the IDT70T651/9 is capable of performing multiple back-to-back write

operations without having to pulse the R/W, CE, or BEn signals high

during address transitions. This RapidWrite Mode functionality allows the

system designer to achieve optimum back-to-back write cycle performance

without the difficult task of generating narrow reset pulses every cycle,

simplifying system design and reducing time to market.

During this new RapidWrite Mode, the end of the write cycle is now

defined by the ending address transition, instead of the R/W or CE or BEn

transition to the inactive state. R/W, CE, and BEn can be held active

throughout the address transition between write cycles. Care must be

taken to still meet the Write Cycle time (tWC), the time in which the Address

inputs must be stable. Input data setup and hold times (tDW and tDH) will

now be referenced to the ending address transition. In this RapidWrite

Mode the I/O will remain in the Input mode for the duration of the operations

due to R/W being held low. All standard Write Cycle specifications must

be adhered to. However, tAS and tWR are only applicable when switching

between read and write operations. Also, there are two additional

conditions on the Address Inputs that must also be met to ensure correct

address controlled writes. These specifications, the Allowable Address

Skew (tAAS) and the Address Rise/Fall time (tARF), must be met to use the

RapidWrite Mode. If these conditions are not met there is the potential for

inadvertent write operations at random intermediate locations as the

device transitions between the desired write addresses.

5632 drw 08

ADDRESS

CE or SEM

(6)

BEn

R/W

DATA

OUT

(2)

(5) (5)

(4)

Timing Wa v eform of Write Cy cle No . 3, RapidWrite Mode Write Cy cle(1,3)

NOTES:

1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and

R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.

3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.

5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics over the Operating Temperature Range

and Supply Voltage Range for RapidWrite Mode Write Cycle(1)

Symbol Parameter Min Max Unit

AAS

Allowable Ad dress Skew for RapidWrite Mod e

____

1ns

ARF

Address Rise/Fall Time for RapidWrite Mode 1.5

____

V/ns

5632 tb l 14

NOTE:

1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.

Timing Wav eform of Address Inputs for RapidWrite Mode Write Cyc le

5632 drw 09

AAS

ARF

(1)

NOTE:

1. A16 for IDT70T659.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wa veform of Semaphore Read after Write Timing, Either Side(1)

NOTES:

1. DOR = D OL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

Timing Waveform of Semaphore Write Contention(1,3,4)

NOTES:

1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for

appropriate BEn controls.

2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value.

SEM

(1)

5632 drw 12

I/O

VALID ADDRESS

SAA

R/W

ACE

VALID ADDRESS

DATA VALID

DATA

OUT

SWRD

SOE

Read Cycle

Write Cycle

-A

VALID

(2)

SOP

SEM

"A"

5632 drw 13

SPS

MATCH

R/W

"A"

MATCH

0"A"

-A

2"A"

IDE "A"

(2)

SEM

"B"

R/W

"B"

0"B"

-A

2"B"

IDE "B"

(2)

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

Symbol Parameter

70T651/9S8

(6)

Com'l Only 70T651/9S10

Com'l

& Ind

(6)

70T651/9S12

Com'l

& I n d

70T651/9S15

Com'l Only

Unit

Min. Max. Min. Max. Min. Max. Min. Max.

BUSY TI M ING (M/ S=V

)

BAA

BUSY Acce ss Time from Add ress Match

____

15 ns

BDA

BUSY Disable Time from Address Not Matched

____

15 ns

BAC

BUSY Ac cess Time fro m Chip Enable Lo w

____

15 ns

BDC

BUSY Disable Time from Chip Enable High

____

15 ns

APS

Arb itration Priority Se t-up Time

(2)

2.5

____

2.5

____

2.5

____

2.5

____

BDD

BUSY Disable to Valid Data

(3)

____

15 ns

Write Ho ld Afte r BUSY

(5)

____

BUSY TI M ING (M/ S=V

)

BUSY Input to Wr ite

(4)

____

Write Ho ld Afte r BUSY

(5)

____

P ORT-TO-PORT DEL AY TIM ING

WDD

Write Pulse to Data Delay

(1)

____

20 ns

DDD

W ri te Da ta Va li d to Re a d Da ta De l ay

(1)

____

20 ns

56 32 tbl 1 5

Symbol Parameter

70T651/9S8

(4)

Com'l Only 70T651/9S10

Com'l

& I nd

(4)

70T651/9S12

Com'l

& Ind

70T651/9S15

Com'l Only

Min. Max. Min. Max. Min. Max. Min. Max.

SLEEP MODE TIMING (ZZx=V

)

ZZS

Sleep Mode Set Time 8

____

ZZR

Sleep Mode Reset Time 8

____

ZZPD

Sleep Mode Power Down Time

(5)

____

ZZPU

Sleep Mode Power Up Time

(5)

____

5632 tbl 15a

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1,2,3)

NOTES:

1. Timing is the same for both ports.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected

during sleep mode. It is recommended that boundary scan not be operated during sleep mode.

3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

5. This parameter is guaranteed by device characterization, but is not production tested.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)

Timing Wa v ef orm of Write with BUSY (M/S = VIL)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB only applies to the slave mode.

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

5632 drw 14

APS

ADDR

"A"

DATA

OUT "B"

MATCH

R/W

"A"

DATA

IN "A"

ADDR

"B"

VALID

(1)

MATCH

BUSY

"B"

BDA

VALID

BDD

DDD

(3)

WDD

BAA

5632 drw 15

R/W

"A"

BUSY

"B"

(3)

R/W

"B"

(1)

(2)

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1,2)

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing (M/S = VIH)(1,3,4)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.

4. CE0X = OEX = BEnX = VIL. CE1X = VIH.

5632 drw 16

ADDR

"A"

and

"B"

ADDRESSES MATCH

"A"

"B"

BUSY

"B"

APS

BAC

BDC

(2)

5632 drw 17

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

70T651/9S8

(3)

Com 'l On ly 70T651/9S10

Co m 'l

& I nd

(3)

70T651/9S12

Com'l

& I nd

70T651/9S15

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

I NTERRU P T T IMI NG

Address Set-up Time 0

____

Write Re co very Time 0

____

INS

Interru p t Set Ti m e

____

15 ns

INR

Interru p t Re s e t Tim e

____

15 ns

56 32 tb l 16

NOTES:

1. Timing is the same for both ports.

2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth T able III — Interrupt Flag(1,4)

Wa v eform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.

4. Timing depends on which enable signal (CE or R/W) is asserted last.

5. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

1. Assumes BUSYL = BUSYR =VIH. CE0X = VIL and CE1X = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5. A17x is a NC for IDT70T659. Therefore, Interrupt Addresses are 1FFFF and 1FFFE.

5632 drw 18

ADDR

"A"

INTERRUPT SET ADDRESS

"A"(3)

R/W

"A"

(4) (5)

INS

(4)

INT

"B"

(2)

5632 drw 19

ADDR

"B"

INTERRUPT CLEAR ADDRESS

"B"(3)

"B"

(4)

INR

(4)

INT

"B"

(2)

Left Port Ri ght Port

FunctionR/W

17L

-A

(5)

INT

R/W

17R

-A

(5)

INTR

L L X 3FFFF XXXX X L

(2)

S e t Rig ht INTR Flag

XXXXXXLL3FFFFH

(3)

Re se t Rig ht INTR Flag

XXX XL

(3)

L L X 3FFFE X Se t Left INTL Flag

X L L 3FFFE H

(2)

X X X X X Re s e t Le ft INTL Flag

5632 tbl 17

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70T651/9 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70T651/9 has an automatic power down

feature controlled by CE. The CE0 and CE1 control the on-chip power

down circuitry that permits the respective port to go into a standby mode

when not selected (CE = HIGH). When a port is enabled, access to the

entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is asserted when the right port writes to memory location

3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the

Truth Table. The left port clears the interrupt through access of

address location 3FFFE when CEL = OEL = VIL, R/W is a "don't care".

Likewise, the right port interrupt flag (INTR) is asserted when the left port

writes to memory location 3FFFF (HEX) and to clear the interrupt

flag (INTR), the right port must read the memory location 3FFFF. The

message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70T659)

is user-defined since it is an addressable SRAM location. If the interrupt

function is not used, address locations 3FFFE and 3FFFF are not used

T ruth Table IV —

Address BUSY Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the

IDT70T651/9 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

4. A17 is a NC for IDT70T659. Address comparison will be for A0 - A16.

5. CEX = L means CE0X = VIL and CE 1X = VIH. CEX = H means CE0X = VIH and/or CE1X = V IL.

Inputs Outputs

Function

(5)

-A

17L

(4)

-A

17R

BUSY

(1)

BUSY

(1)

X X NO MATCH H H No rmal

HX MATCH H H Normal

XH MATCH H H Normal

LL MATCH (2) (2)Write Inhibit

(3)

5632 tb l 18

Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T651/9.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35). These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Functions D

- D

Left D

- D

Ri g h t S ta tu s

No Action 1 1 Semaphore fre e

Le ft Port Writes "0" to Semapho re 0 1 Left p ort has semaphore to ken

Rig h t P o rt Wri tes " 0" to Se m ap ho re 0 1 No change . Right s ide has no wri te ac c e s s to s e m ap ho re

Le ft Port Writes "1" to Semapho re 1 0 Right port obtains semapho re token

Le ft Port Write s "0" to S e map ho re 1 0 No c hang e . Le ft p o rt has no wri te ac c e s s to s e m ap ho re

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Le ft Port Writes "1" to Semapho re 1 1 Semaphore fre e

Right Port Write s "0" to Semap hore 1 0 Right port has semaphore token

Right Port Write s "1" to Semap hore 1 1 Semaphore fre e

Le ft Port Writes "0" to Semapho re 0 1 Left p ort has semaphore to ken

Le ft Port Writes "1" to Semapho re 1 1 Semaphore fre e

5632 tb l 19

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70T651/9 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

The BUSY arbitration on a master is based on the chip enable and

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with the R/W signal. Failure to

observe this timing can result in a glitched internal write inhibit signal

and corrupted data in the slave.

Semaphores

The IDT70T651/9 is an extremely fast Dual-Port 256/128K x 36

CMOS Static RAM with an additional 8 address locations dedicated to

binary semaphore flags. These flags allow either processor on the left or

right side of the Dual-Port RAM to claim a privilege over the other processor

for functions defined by the system designer’s software. As an ex-

ample, the semaphore can be used by one processor to inhibit the

other from accessing a portion of the Dual-Port RAM or any other

shared resource.

The Dual-Port RAM features a fast access time, with both ports

being completely independent of each other. This means that the

activity on the left port in no way slows the access time of the right port.

Both ports are identical in function to standard CMOS Static RAM and

can be read from or written to at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic power-down

feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and

SEM, the semaphore enable. The CE0, CE1, and SEM pins control on-

chip power down circuitry that permits the respective port to go into standby

mode when not selected.

Systems which can best use the IDT70T651/9 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70T651/9s

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70T651/9 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port RAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that a

shared resource is in use. If the left processor wants to use this

resource, it requests the token by setting the latch. This processor then

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70T651/9 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAMs

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70T651/9 RAM the BUSY pin is an output if the part is used as a

master (M/S pin = VIH), and the BUSY pin is an input if the part used

as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70T651/9 Dual-Port RAMs.

5632 drw 20

MASTER

Dual Port RAM

BUSYR

MASTER

Dual Port RAM

BUSYR

SLAVE

Dual Port RAM

BUSYR

SLAVE

Dual Port RAM

BUSYR

BUSYLBUSYL

as mail boxes, but as part of the random access memory. Refer to Truth

Table III for the interrupt operation.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

verifies its success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side processor

has set the latch first, has the token and is using the shared resource.

The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70T651/9 in a

separate memory space from the Dual-Port RAM. This address space

is accessed by placing a low input on the SEM pin (which acts as a chip

select for the semaphore flags) and using the other control pins (Address,

CE0, CE1,R/W and BEn) as they would be used in accessing a

standard Static RAM. Each of the flags has a unique address which can

be accessed by either side through address pins A0 – A2. When accessing

the semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level

is written into an unused semaphore location, that flag will be set to

a zero on that side and a one on the other side (see Truth Table V).

That semaphore can now only be modified by the side showing the zero.

When a one is written into the same location from the same side, the flag

will be set to a one for both sides (unless a semaphore request

from the other side is pending) and then can be written to by both sides.

The fact that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what makes

semaphore flags useful in interprocessor communications. (A thorough

discussion on the use of this feature follows shortly.) A zero written into the

same location from the other side will be stored in the semaphore request

latch for that side until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE

signals need to be active. (Please refer to Truth Table II). Furthermore,

the read value is latched into one side’s output register when that side's

semaphore select (SEM, BEn) and output enable (OE) signals go active.

This serves to disallow the semaphore from changing state in the middle

of a read cycle due to a write cycle from the other side.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Table V). As an example, assume a processor

writes a zero to the left port at a free semaphore location. On a

subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side

during subsequent read. Had a sequence of READ/WRITE been

used instead, system contention problems could have occurred during

the gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The

reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two semaphore

request latches feed into a semaphore flag. Whichever latch is first to

present a zero to the semaphore flag will force its side of the semaphore

flag LOW and the other side HIGH. This condition will continue until a one

is written to the same semaphore request latch. If the opposite side

semaphore request latch has been written to zero in the meantime, the

semaphore flag will flip over to the other side as soon as a one is written

into the first request latch. The opposite side flag will now stay LOW until

its semaphore request latch is written to a one. From this it is easy to

understand that, if a semaphore is requested and the processor which

requested it no longer needs the resource, the entire system can hang up

until a one is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one,

all semaphores on both sides should have a one written into them

at initialization from both sides to assure that they will be free

when needed.

Figure 4. IDT70T651/9 Semaphore Logic

5632 drw 21

0DQ

WRITE D

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT

RPORT

SEMAPHORE

READ SEMAPHORE

READ

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wav eform of Sleep Mode(1,2)

NOTES:

1. CE1 = VIH.

2. All timing is same for Left and Right ports.

5632drw22

ZZPD

DATA

VALIDADDRESS

ZZR

NonewreadsorwritesallowedNormalOperation

NormalOperationSleepModeNoreadsorwritesallowed

VALIDDATA

ADDRESS

ZZS

ZZPU

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

JT AG AC Electrical

Characteristics(1,2,3,4,5)

70T651/9

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

JTAG Clo ck HIGH 40

____

JCL

JTAG Clock Low 40

____

JTAG Clock Rise Time

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Reset 50

____

JRSR

JTAG Re se t Re cov ery 50

____

JCD

JTAG Data Outp ut

____

25 ns

JDC

JTA G Data Output Ho ld 0

____

JTAG Setup 15

____

JTAG Hold 15

____

5632 tb l 20

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

5. JTAG cannot be tested in sleep mode.

JTAG Timing Specifications

TCK

Device Inputs(1)/

TDI/TMS

evice Outputs(2)/

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

5632 drw 23

NOTES:

1. Device inputs = All device inputs except TDI, TMS, TCK and TRST.

2. Device outputs = All device outputs except TDO.

Sleep Mode

The IDT70T651/9 is equipped with an optional sleep or low power

mode on both ports. The sleep mode pin on both ports is active high. During

normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the

port will enter sleep mode where it will meet lowest possible power

conditions. The sleep mode timing diagram shows the modes of operation:

Normal Operation, No Read/Write Allowed and Sleep Mode.

For a period of time prior to sleep mode and after recovering from sleep

mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read

operation occurs during these periods, the memory array may be

corrupted. Validity of data out from the RAM cannot be guaranteed

immediately after ZZ is asserted (prior to being in sleep).

During sleep mode the RAM automatically deselects itself. The RAM

disconnects its internal buffer. All outputs will remain in high-Z state while

in sleep mode. All inputs are allowed to toggle. The RAM will not be selected

and will not perform any reads or writes.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

I n struc ti on F i el d Val u e Desc ri pti o n

Rev i s io n Num b e r (31: 28) 0x 0 Res e r ved for ve r si on num b e r

IDT Device ID (27:12) 0x338

(1)

Defines IDT p art n umbe r 70T651

IDT JEDEC ID (11: 1) 0x 33 Al lo ws uniq ue id e ntificatio n o f d e v ic e ve nd o r as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

5632 tb l 21

Scan Register Sizes

Regi ster Na me Bi t S ize

Instruction (IR) 4

Bypass (BYR) 1

Iden tif ica ti on (I D R) 3 2

Boundary Scan (BSR) Note (3)

5632 tb l 2 2

NOTE:

1. Device ID for IDT70T659 is 0x339.

System Interface Parameters

Instruction Code Description

EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs

(1)

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCO DE 0010 L o ad s the ID reg i s te r ( IDR) wi th the v e n d o r ID c o de and p l ac e s the

HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

SAMPLE/PRELOAD 0001 Plac es the bound ary scan reg ister (BSR) b etwee n TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the b ound ary sc an ce ll s and shifte d s erially thro ug h TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

RESERVED All Othe r Code s Se v e ral co mb inatio ns are re se rve d . Do no t us e co d e s o the r than tho se

identified above.

5632 tbl 23

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, TCK and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Power

999

Speed

Package

Process/

Temperature

Range

Blank

ICommercial (0°Cto+70

°C)

Industrial (-40°Cto+85

°C)

SStandard Power

XXXXX

Device

Type

Speed in nanoseconds

70T651

70T659 9Mbit (256K x 36) Asynchronous Dual-Port RAM

4Mbit (128K x 36) Asynchronous Dual-Port RAM

256-ball BGA (BC-256)

208-pin PQFP (DR-208)

208-ball fpBGA (BF-208)

5632 drw 24

Commercial Only(1)

Commercial & Industrial(1)

Commercial & Industrial

Commercial Only

GGreen

(2)

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DADA

DATT

TASHEET DOCUMENT HISTASHEET DOCUMENT HIST

ASHEET DOCUMENT HISTASHEET DOCUMENT HIST

ASHEET DOCUMENT HISTOROR

OROR

ORYY

Y::

04/25/03: Initial Datasheet

10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table

Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table

Page 9, 11, 15, Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only

17 & 26

Page 10 Added Capacitance Derating Drawing

Page 11, 15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables

Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table

Page 12 Added tLZOB to the Waveform of Read Cycles Drawing

Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing

Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information

Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms

10/20/03: Page 15 Corrected tARF to 1.5V/ns Min.

04/21/04: Removed Preliminary status from entire datasheet

01/05/06: Page 1 Added green availability to features

Page 27 Added green indicator to ordering information

07/25/08: Page 9 Corrected a typo in the DC Chars table

01/19/09: Page 27 Removed "IDT" from orderable part number

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

NOTES:

1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

