GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
Data Sheet
DO-009643-DS, Issue 2
Overview
The GlobespanVirata® XDSL2™ Digital Subsc ribe r Line
(DSL) chip set s provid e low po wer, hi gh de nsi ty solu tio ns for
2-wire DSL equipment. These chip sets ar e ful l y
programmable and field upgradeable eliminating the risk of
product obsolescence and accelerating the time-to-market for
new netwo rk serv ices. The Globes panVira ta® XDSL2™ DSL
chip sets are fully interoperable with multi-vendor DSL chip
set solutions. This interoperability enables dynamic
interworking of multiple vendor DSL solutions with the
capability to interoperate with products that conform to ANSI
and ETSI DSL standards.
GlobespanVirata’s unique hardware platform supports
multiple dual-channel applications including SDSL, HDSL2,
and SHDSL, using population options for optimization.
The XDSL2 DSL chip sets incorporate two DSL bit pumps
plus framing into a three-chip solution comprised of a dual-
channel digital signal processor (DSP) with built-in framer and
two Analog Front Ends each with an Integrated Line Driver
(ILD2).
The XDSL2 chip sets interface directly with off-the-shelf T1/
E1 transceivers and Nx64 multiplexing, eliminating the need
for a separate DSL framer to combine and format the two DSL
channe ls into a standard inte rfac e. Gl obe sp anVi rata’s DSL
XDSL2 chip sets deliver two channels of full duplex
transmission up to 2320 kb/s, depending on the application.
The high density XDSL2 du al-channel DSL chip se ts are ideal
for CO applications, while single-channel versions with
integrated framer are also available for CPE applications.
Features
•Dual-channel DSP with framer that fully integrates
2 separate DSL chips into a single device
•Two AFEs, each with an integrated differential line driver
•2B1Q, CAP, or PAM line codes
•Supports dual-channel symmetric data rates of 144 kb/s
to 2320 kb/s (depending on the application)
•Supports IDSL with optional data interface rates of
64 kb/s, 128 kb/s, and 144 kb/s
•Offe rs p hys ic al lay er i nte rope rability wi th c om pet itiv e s ol u-
tions
•Glueles s int erfa ce to popu lar micro proc es so rs
•Transmission compliant with ETSI TS 101 135, ITU-T
G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP,
ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL
•Referenc e desig n comp ati ble wit h Bellco re GR-1 089, IEC
60950, UL 1950, ITU-T K.20 and K.21
•Built-in fram er provides eas y access to EOC and indicator
bits (framing can be bypassed completely for 2-channel
independent operation)
•Interfaces directly with off-the-shelf single-channel T1/E1
transceivers
•ATM UTOPIA Level 1 and 2 interface
•A single os ci ll ator and hyb rid to pol ogy su pp orts all spe ed s
•+3.3V and +5V power supp lies
June 25, 2002, Issue 2
Part Numbers
G2216-208-041PF B2 (SDSL 2B1Q)
G2214-208-041DF B2 (SDSL CAP)
G2237-208-041PT B2 (SHDSL/HDSL2)
G2237-208-041PT C1 (SHDSL/HDSL2)
XDSL2TM SDSL, HDSL2, or SHDSL - ILD2
Dual-Channel, Low Power, Programmable
Tran sceiver with Integrated Framer an d Line Drivers
µProcessor Interface
Dual
Channel
DSP
w/Framer
ILD2
ILD2
TDATA (A/B)
TClock (A/B)
Frame Pul se (A/B)
RDATA (A/B)
Rclock (A/B)
Frame Pul se (A/B)
Customer Interf ace
Figure 1. Block Diagra m of XDSL2™ DSP with Two Single-Channel ILD2s
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions2DO-009643-DS, Issue 2
Introduction
The GlobespanVirata DSL chip sets support
applications ranging from remote network access,
digital pair gain, video conferencing, and cellular base
station land-line connectivity, for T1/E1 services. Up to
36 voice circuits may be provisioned over a single
copper pair.
Example Applications
•Compatibility with voice/data pair gain systems
•Cellular and microcellular systems
•T1/E1 and fractional T1/E1 DSL transceiver
•Wireless base station c onnec tivity
Related Material s
To accelerate time-to-market, GlobespanVirata offers
our customers a comprehensive Design Guide which
includes details on planning, layout, testing, debugging,
and expert tips and recommendations for building a
successful DSL product. The Design Guide is
distributed as part of a Design Package which includes
firmware, transceiver schemati cs, sample code,
transceiver layout Gerber files, and Bill of Materials.
For rapid prototyping, Quick Kits are available. These
Quick Kits contain all transceiver design BOM
components in kit form so there’s no component lead
time delay.
The Super GlobespanVirata Development System
(SGDSTM), an easy-to-use evaluation and development
platform designed to support all GlobespanVirata xDSL
transceiver solutions, is also available for early product
development.
The SGDS also provides an interface to the
GlobespanVirata Microsoft® Windo ws® - based Host
Interface Program (WHIP). When the SGDS is teamed
with WHIP, product evaluation, testing and debugging is
achieved with the click of a mouse.
GlobespanVirata Transceiver System
Overview
•The GlobespanVira ta XDSL2™ DSL ch ip se ts con-
sist of a dual-channel DSP with an on-chip framer,
and two single-channel AFEs (with ILD2).
•The single-channel ILD2s filter and digitize the sig-
nal received on the telephone line and for the trans-
mit side, generate analog signals from the digital
data and filter the analog signals to create the
2B1Q, CAP or PAM transmit signal (depending on
the line code).
•The GlobespanVirata Windows-based Host Inter-
face Program (WHIP) is offered as part of the
GlobespanVirata transceiver system development
package for SDSL 2B1Q, HDSL2, and SHDSL
applications. WHIP allows you to test and debug
your product design with the click of a mouse. This
graphical interface allows you to send commands,
perform trace and debug procedures, and initiate a
startup on both the CO and CP units. WHIP offers
complete flexibility and modularity - you can rear-
range windows and toolbars to suit your prefer-
ences and design requirements.
•SDSL CAP applications are offered the Globespan-
Virata Host Interface Program (HIP) software as
part of the Gl obespanVirata transceiver system
development package. The PC-based HIP software
provides a PC interface to the host. HIP allows the
host to run scripts to obtain and manipulate data,
test performance, and debug the software. No addi-
tional software or special PC hardware or tools are
required. Customers who use HIP with their host
processor receive the benefits of faster diagnosis
and specialized assistance from the GlobespanVi-
rata staff.
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 3
DO-009643-DS, Issue 2
Architecture
The interface between the Host and the transceiver
consists of the following:
•Transmission Interface (data, clock and synchronization
signals)
•Control Interface (microprocessor compatible)
•Diagnostic Interface
•Power Interface
•Loop Interface
System timing is derived from a free running oscillator
in the transceiver of the central office (CO). At the
customer premises end (CPE), the CPE derives a clock
from the received line signal and provides this clock to
the CPE transmitter.
The dual-channel chip set also supports Network
Timing Recovery (NTR) at the CO end. With this feature
enabled, the CO unit will accept a clock at 8 kHz (± 100
ppm) as an input and the STU-R will output a clock that
is phase locked to the CO clock. The NTR clock should
have a duty cycle of 45-55%. Note that this feature is
only available with an UTOPIA interface.
The DSL transceiver supports both T1 and E1 rates,
and fractional rates.
Transceiver States
The following is a list of the possible states that the DSL
transceiver can be in:
•IDLE mode, where the transceiver is not attempting
to start up, pass data, or perform tests
•TEST mode, where the transceiver is either in local
analog loopback or local digital loopback and is not
passing user data
•STARTUP mode (SDSL only), where the trans-
ceiver is attempting a startup of the DSL connec-
tion, prior to entering DATA mode
•HANDSHAKE mode (HDSL2 and SHDSL), where a
link is established between the CO unit and the
CPE unit
•TRAINING mode (HDSL2 and SHDSL), where the
transceiver is attempting a startup, prior to entering
DATA mode
•DATA mode, where the transceiver has started up
and trained and is capable of passing user data
Software Inte rface
A microprocessor interface that uses simple read/write
drivers provides direct access to the GlobespanVirata
chip set—eliminating the need for complicated register
maps and advanced programming. These drivers allow
the Host to select rates, adjust transmit power, read
signal quality, and perform a variety of other tasks
which include reporting the current operational status of
the transceiver.
To configure and control the transceiver,
GlobespanVirata provides hardware-dependent driver
examples and GlobespanVirata supplied transceiver
software modules (TSMs). The TSMs have the ability to
allow a single CPU in the Host to control multiple
transceivers. This could be a potential cost savings for
arrangements where it might be advantageous to put
multiple transceivers on one card, such as at the CO.
NOTE:You will not need a regis ter ma p of t he DSP, as this
information is not required to successfully design
and implement an STU. As discussed previously,
access to the DSP is provided through hardware-
dependent I/O routines and GlobespanVirata
provided TSMs.
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions4DO-009643-DS, Issue 2
Figure 2. Typical Transceiver Power Up/Start Up
Sequence
Power Up
InitXCVR()
ExecuteXCVR()
Reset DSP
InitXCVR_CS()
SetParamXCVR()
TRAININGHANDSHAKE
BOOT
LOAD
(not tim e d)
FRAMER
SYNC*
IDLE
MODE
Optional
SetParamFramer()
Optional
SStatusXCVR()
Host Processes
Abort
Data Mode
STARTUP MODE * Only if PLL is enabled
FRAMER INTERRUPTSDSP INTERRUPTS
FAILED STARTUP
Ma y o ccu r anyt ime
before Data Mode.
DETAIL A:
DETAIL A
GTI_COMPLETE_PASS
Data Mode
GTI_ACTIVE
DSP/Framer Interrupt Received
Set all
framer
options Idle Mode
Start Up
Activities
Idle Mode
Idle Mode
Power Up/
Reset DSP
Power Up
Activities
Retrain
DATA MODE
Transceiver Power Up Sequence
Figure 2 describes a typical sequence from power up to
DATA mode for a transceiver. After power is applied to
both the Host and the transceiver, the Host calls the
InitXCVR_CS() and InitXCVR() routines to
initialize trans ce iv er varia bles and to initial ize the DSP /
Framer.
Next, the Host calls the SetParamXCVR() routine to
set up the parameters that are appropriate for start up of
the transceiver.
The SetParamFramer() routine is called by the Host
to initialize framer options.
After setting up the transceiver parameters, the Host
calls the ExecuteXCVR() routine to execute the
command that was set up using the SetParamXCVR()
routine. With a successful completion of the
ExecuteXCVR() rou tine, th e transc eiver wi ll now b e in
DATA mode.
The SStatusXCVR() routine is used to track
performance and to obtain information from the
transceiver about what state the transceiver is in (i.e.,
monitor start-up, check signal quality, etc.).
Setting Up the Command Parameters
[SetParamXCVR()]
The routine SetParamXCVR() proces ses the
parameter array structure that will be executed when
the ExecuteXCVR() routine is called.
The parameter structure will be similar to the following
start-up example:
struct PARAM_XCVR_ARRAY Items;
Items.length = GTI_NUM_OF_CMD_PARAMETERS
Items.item[GTI_ACTION_ITEM]=GTI_STARTUP_REQ;
Items.item[GTI_MODE_ITEM]=GTI_CO;
Items.item[GTI_POWER_SCALE_ITEM]=GTI_DEFAULT_SCALE;
Items.item[GTI_FRAMER_TYPE_ITEM]= GTI_UTOPIA_L2;
.
.
.
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 5
DO-009643-DS, Issue 2
Table 1 describes the example arguments to the
SetParamXCVR() routine when performing start-up.
This is only a sample subset of possible parameters,
provided to illustrate how easy it is to work with the
GlobespanVirata chip sets.
Table 1. Example SetParamXCVR() Structure
Parameter Function
GTI_ACTION_ITEM
The action GTI_STARTUP_REQ begins
start-up, which, upon successfu l
completion, res ults in the transceive r
changing into DATA mode.
GTI_MODE_ITEM Mode describes which transceiver the
Host is talking to, the CO or CP.
GTI_POWER_SCALE_ITEM Allows the transmit power to be set in
small increments.
GTI_FRAMER_TYPE_ITEM
The framing modes are interface specific.
Possible arguments for framing modes,
depending on the customer interface,
include: No Framing, UTOPIA Level 1,
UTOPIA Level 2, T1, E1, and nxDS0
(with the abil ity to choose continuou s
DS0 blocks).
Checking the Transceiver Status
[SStatusXCVR()]
The SStatusXCVR() routine can be executed when in
DATA mode, utilizing minimal processing power. To
further illustrate the ease of programming
GlobespanVirata chip sets, Table 2 supplies a few
exampl es of SStatusXCVR().
Table 2. Example SStatusXCVR() Parameters
Parameter Function
GTI_XMIT_POWER This action returns the transmitted power.
GTI_START_PROGRESS The current detailed start-up state of the
transceiver is returned.
GTI_BERT_ERROR The number of bit errors detected during
the 511 BERT test is returned.
GTI_RECEIVER_GAIN Total receiver gain setting can be calcu-
lated using the return values from this
action.
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions6DO-009643-DS, Issue 2
System Pow er Require ments
The 144-pin Dual-channel DSP/Framer chip requires +3.3V (see Table 14 on page 16 for tolerance), and the two
ILD2 chips require +3.3V (±5%) as well as +5V (±5%). Power requirements, including transceiver power
consumption, have a tolerance of ±5%. The maximum peak-to-peak ripple and noise voltage is 50 mV for all
supplies.
The transceiver obtains its power from the power feed in the Host through the power interface. Table 3, Table 4,
Table 5, and Table 7 provide power requirements for the 144-pin Dual-channel DSP.
NOTE:1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-02 using 1:2 transformer
Add 30 mA at 5VA for unified designs based on
SHDSL population option G-02-2302-1006C-03
using 1:4 transformer or HDSL2 population option
G-02-2302-1006C-03 using 1:5.4 transformer
3. Transmit power: 13.5 dbm (nominal at all rates)
4. Measured during activation and data mode
Table 3. Typical SDSL 2B1Q System Power Consumptio n
Per Channel (DSP/Framer in a 144 LPQ2)
Line Rate
(Kb/s)
Drain Current (mA) Power/Port
(mW)
3.3VD
DSP & ILD2 5VA
ILD2
144 75 85 673
272 105 85 772
400 110 90 813
528 115 90 830
784 160 90 978
1040 170 90 1011
1168 210 90 1143
1552 235 95 1251
2064 250 95 1300
2320 280 95 1400
NOTE:1. Power per channe l based on dual -ch an nel
operation
2. Based on customer schematic:
G-02-2302-1006C-03 using 1:4 transformer
3. Transmit power: 13.5 dbm (nominal at 2320kb/s)
4. Measured during activation and data mode
Table 4. Typical SDSL CAP System Power Consumption
Per Channel (DSP/Framer in a 144 TQFP)
Line Rate
(Kb/s)
Drain Current (mA) Power/Port
(mW)
3.3VD
DSP & ILD2 5VA
ILD2
144 75 90 698
272 80 90 714
400 115 105 905
528 145 115 1055
784 145 115 1055
1040 145 115 1055
1552 155 115 1087
2064 165 120 1145
2320 185 120 1210
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 7
DO-009643-DS, Issue 2
NOTE:1. Power per channel based on dual-channel
operation
2. Based on custo mer schemat ic :
G-02-2302-1006C-01 using 1:5.4 transformer
3. Transmit power: 16.8 dbm (nominal)
Table 6. Maximum Junction Tempe rature
Table 5. Typical HDSL2 System Power Consumption Per
Port (DSP/Framer in a 144 LPQ2)
Line Rate
(Kb/s)
Drain Current (mA) Power/Port
(mW)
3.3VD
DSP & ILD2 5VA ILD2
T1
(1.552) 270 150 1681
TJ Maximum
125 oC
NOTE:1. Power per channe l based on dual -ch an nel
operation
2. Based on customer schematic:
G-02-2302-1006C-03 using 1:4 transformer
3. Transmit power: 13.5 dbm (nominal at all rates)
4. Measured during activation and data mode
5. All Nx64 payl oad rates are sup ported (where N =
3 through 3 6). The line rates list ed i n Ta ble 7 are a
few typical data points
Electr ical Inte rface Spe cif ica tion
All processor interfaces, customer clock and data, and
diagnostic interface inputs and outputs associated with
the 144-pin DSP Core are compatible with 5V CMOS
and TTL logic, as well as 3.3V CMOS logic. While the
DSP is a 3.3V device, all the above inputs are designed
to be 5V tolerant. The Control Interface supports
multiplexed, non-multiplexed, and Motorola processor
interface modes.
Table 7. Typical SHDSL System Power Consumption Per
Channel (DSP/Framer in a 144 LPQ2)
Line Rate
(Kb/s)
Drain Current (mA) Power/Port
(mW)
3.3VD
DSP & ILD2 5VA
ILD2
144 100.0 125.0 955.0
200 105.0 125.0 971.5
208 105.0 125.0 971.5
272 120.0 125.0 1021.0
392 130.0 125.0 1054.0
400 130.0 125.0 1054.0
528 135.0 125.0 1070.5
776 160.0 125.0 1153.0
784 160.0 125.0 1153.0
1040 180.0 125.0 1219.0
1168 185.0 125.0 1235.5
1552 225.0 130.0 1392.5
2056 245.0 130.0 1458.5
2064 245.0 130.0 1458.5
2312 270.0 130.0 1541.0
2320 270.0 130.0 1541.0
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions8DO-009643-DS, Issue 2
Performance
GlobespanVirata has rigorously tested the performance of the DSL chip sets, with the results detailed in Table 8,
Table 9, Table 10 and Table 11.
Table 8. SDSL 2B1Q Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
24 AWG 26 AWG
kft km kft km
144 25.4 7.7 21.0 6.4
272 23.6 7.2 19.5 5.9
400 22.4 6.8 17.3 5.2
528 21.3 6.5 16.1 4.9
784 19.1 5.8 15.2 4.6
1040 17.6 5.4 14.4 4.4
1168 15.9 4.8 13.8 4.2
1552 13.3 4.1 12.7 3.9
2064 11.8 3.6 11.1 3.4
2320 11. 3 3.4 10.9 3.3
Table 9. SDSL CAP Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
24 AWG 26 AWG
kft km kft km
144 30.4 9.2 21.4 6.5
272 30.3 9.2 20.3 6.1
400 28.7 8.7 18.8 5.7
528 26.2 7.9 17.0 5.3
784 23.1 7.0 15.8 4.8
1040 22.4 6.8 15.5 4.7
1552 19.4 5.9 13.9 4.2
2064 17.2 5.2 12.2 3.7
2320 15.8 4.8 11.7 3.5
NOTE:All Nx64 payload rates are supported (where N= 3
through 36). The line rates listed in Table 11 are a
few typical data points.
Table 10. HDSL2 Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
24 AWG 26 AWG
kft km kft km
T1
(1.552 kb/s) 18.0 5.5 13.5 4.1
Table 11. SHDSL Performance Specific ation s
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
26 AWG
kft km
144 26.0 7.9
200 21.4 6.5
392 19.9 6.0
520 18.7 5.7
776 17.5 5.3
1032 16.6 5.1
1168 15.8 4.8
1544 14.0 4.2
2056 13.0 3.9
2312 12.5 3.8
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 9
DO-009643-DS, Issue 2
Figure 3. XDSL2™ Dual-Channel DSP with Integrated Line Driver Functional Diagram
Host
Processor
RDN, WRN
INTN
AD[7:0]
Host
Processor
Interface
Framer
DACB
Q0A
Q1A
MCLK
CSD
ILD2
DACB
Q0A
Q1A
MCLK
CSD
ILD2
APDO5
APDO4
APDI0
APDO2
APDO0
APDO1
DACA
DACA
BPDO5
BPDO4
APDI1
BPDO2
BPDO1
BPDO0
Level Display
Monitor
Diagnostic
Interface
Loop
Loop
Dual-
Channel
DSP
Q0B
Q1B
Q0B
Q1B
APDI5
APDI3
BPDI1
BPDI5
To Data
Interface A
To Data
Interface B Transformer
Transformer
Address/
Data Bus
Control
Signals
RXDA
RXCKA
TXDA
TXCKA
TXSOFA
RXSOFA
RXDB
RXCKB
TXDB
TXCKB
TXSOFB
RXSOFB
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions10 DO-009643-DS, Issue 2
Dual-Channel DSP/Framer Specifications
Figure 4. 144-Pin Dual-Channel DSP/Framer Pin Di agram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
D2ACKA
BPDO5/APDO11
APDO0
APDO1
APDO2
APDO3
APDO4
APDO5
VSS
VSS
VSS
BPDO4/APDO10
BPDO3/APDO9
BPDO2/APDO8
BPDO0/APDO6
BPDO1/APDO7
CSCKA
CSDOA
CSDOB
CSCKB
A2DCKB
BPDI0/APDI6
BPDI1/APDI7
BPDI2/APDI8
BPDI3/APDI9
BPDI5/APDI11
BPDI4/APDI10
VDD
APDI0
APDI1
APDI2
APDI3
APDI4
APDI5
CSRD
A2DCKA
VDD
AD5
D2ACKB
XSB0B/TXA2
XSB1B/TXA3
TXA4
VSS
RXA4
RXA2
REFCK
AD4
AD6
AD7
CSN
VDD
PWRSTN
RXA3
INTA
AD2
AD3
AD1
A0
A1
A2
A3
AD0
A4
DCO
MOD2
MOD1
MOD0
AVDD
AVSS
VDD
VSS
INTB
DP10
TA18
DP9
DP8
RXCLK
DP2
TXCLK
VDD
VSS
TA10
TA17
TA19
WRN
RDN
VSS
ALE
TA0/RXA1
TA1/TXA1
TA15
TA16
TA14
VDD
SYTCK
VSS
P5IO
TA13
TA12
TA11
TA3
TA4
TA5
TA6
TA7
TA8
TA9
TA2
VDD
DP7
XSB0A
XSB1A
POP2A
SOCK
ISO
QSO
PIP/POP/RXA0
RXSOFA/RXSOC
DP3
DP1
RXSOFB/RXCLAV
DP0
VDD
VSS
PIP/POP/RXEN
TXSOFB/TXEN
DP5
DP4
DP6
DP13
DP14
DP11
DP12
TBAUD/TXCLAV
DP15
TXSOFA/TXSOC
VSS
AVSS
XTLO
XTLI
AVSS
AVDD
VSS
PIP/POP/TXA0
144 LPQ2
(Top View)
DSP/Framer
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 11
DO-009643-DS, Issue 2
Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions
Pin Name(s) Mode(s) Functional Descri ption
1D2ACKA I/O Not used for this application. Per applicatio n schem atic, do not connect.
2APDO0 O Data Out, Channel A. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACA for
channel A.
3APDO1 O Control Output, Channel A. Control signal transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin
CSD for channel A.
4APDO2 O Master Clock to ILD2, Channel A. Input to AFE PLL which generates oversampling clocks. Connected
to ILD2 pin MCLK for channel A.
5APDO3 O Not used for this application. Per application schem ati c, do not connect .
6APDO4 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0A for channel
A.
7APDO5 O Data Out, Channel A. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACB for
channel A.
8VSS — Ground.
9CSCKA ONot used for Revision “B2” DSP/Framer applicatio ns. Per applicatio n schem atic, do not connect.
ITMS. Boundary-scan mode select. Applicable to Revision “C1” DSP/Framer applications only, for JTAG
support.
10 CSDOA O Not used for this application. Per application schem ati c, do not connect .
11 A2DCKA I/O Not used for this application. Per applicatio n schem atic, do not connect.
12 APDI0 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1A for channel
A.
13 APDI1 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1A for channel
B.
14 APDI2 I Not used for this application. Per application schematic, pulled low through a 1kΩ resistor to ground.
15 APDI3 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1B for channel
A.
16 APDI4 I Not used for this application. Per application schematic, pulled low through a 1kΩ resistor to ground.
17 APDI5 I Data In, Channel A. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0B for channel
A.
18 CSRD I
Not used fo r Revision “B2” DSP/Fram er applications. Per application schematic, pulled low through
a 1kΩ resistor to ground.
TDI. B ounda ry-sc an dat a in. Appli cable to Re visi on “C1” D SP/F ramer appli catio ns onl y , f or JTAG s uppor t.
19 VSS — Ground.
20 VDD P +3.3V suppl y.
21 BPDI0/APDI6 I Not used for this application. Per application schematic, pulled low through a 1kΩ resistor to ground.
22 BPDI1/APDI7 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0B for channel
B.
23
24
25
BPDI2/APDI8
BPDI3/APDI9
BPDI4/APDI10 INot used for this application. Per application schematic, pulled low through a 1kΩ resistor to ground.
26 BPDI5/APDI11 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q1B for channel
B.
27 A2DCKB I/O Not used for this application. Per applicati o n schem atic, do not connect.
28 CSDOB O Not used for this application. Per applicati o n schem atic, do not connect.
29 CSCKB O
Not used fo r Revision “B2” DSP/Framer ap plications. Per applicati o n schem atic, do not connect.
TDO. Boundary-scan data out. Applicable to Revision “C1” DSP/Framer applications only, for JTAG
support.
30 VSS — Ground.
31 BPDO5/APDO11 O Data Out, Channel B. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACB for
channel B.
32 BPDO4/APDO10 I Data In, Channel B. Data transmitted to DSP/Framer from ILD2. Connected to ILD2 pin Q0A for channel
B.
33 BPDO3/APDO9 O Not used for this application. Per appli catio n schem atic , do not connect .
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions12 DO-009643-DS, Issue 2
34 BPDO2/APDO8 O Master Clock to ILD2, Channel B. Input to AFE PLL which generates oversampling clocks. Connected
to ILD2 pin MCLK for channel B.
35 BPDO1/APDO7 O Control Output, Channel B. Control signal transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin
CSD for chan ne l B.
36 BPDO0/APDO6 O Data Out, Channel B. Data transmitted to ILD2 from DSP/Framer. Connected to ILD2 pin DACA for
channel B.
37 VDD P +3.3V supply.
38 D2ACKB O Not used for this application. Per application schematic, do not connect.
39 XSB0B/TXA2
SERIAL I/O No Connect. For serial interface applications, this pin is used for debug purposes only.
UTOPIA I/O TXA2- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
40 XSB1B/TXA3
SERIAL I/O No Connect. For serial interface applications, this pin is used for debug purposes only.
UTOPIA I/O TXA3- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
41 TXA4
SERIAL I/O Not used for this ap plication. Per application schematic, do not connect.
UTOPIA I/O TXA4- ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
42 VSS — Ground.
43
44
45
RXA4
RXA2
RXA3
SERIAL I/O Not used for this ap plication. Per application schematic, do not connect.
UTOPIA I/O ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the appropriate
PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
46 INTA O
Interrupt of DSP A. Carries interrupts from internal DSP core A. The polarity of the interrupt level is
programmable with default to inactive open-drain. Internally generated status can be enabled to activate
the interrupt pin. Used during start-up for code downloads. INTA and INTB are both required. Both can
be declared open-drain and tied together, if desired.
47 INTB O
Interrupt of DSP B. Carries interrupts from internal DSP core B and framer. The polarity of the interrupt
level is programmable with default to inactive open-drain. Internally generated status can be enabled to
activate the interrupt pin. Used during start-up for code downloads and EOC interrupts in data mode. INTA
and INTB are both required. Both can be declared open-drain and tied together, if desired.
48
49
50
MOD2
MOD1
MOD0 I
Host Bus Mode. Bits 2 through 0. These input pins define the host bus control modes:
000 = Non-mu l tipl e xed pro cessor mode
001 = Motorola mode where RDN is R/W and WRN is DSN
01X = reserved for testing
100 = Multiplexed processor mode
101 = reserv ed for test in g.
51 AVDD P AVDD. Digital +3.3V supply for VCO.
52 AVSS — AVSS. Ground pin for VCO. Connect to digital ground as per schematic.
53 VDD P +3.3V supply.
54 VSS — Ground.
55 REFCK I/O Reference Clock. Used to pass network timing reference.
56 DCO I/O DCO. Pul l up as per application schematic.
57
58
59
60
61
A0
A1
A2
A3
A4
IAddress Bus. Bits 4 through 0. Host Address bus in the non-multiplexed mode.
A[4:3] are used to select between the two internal 8 byte address spaces.
62
63
64
65
66
67
68
69
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O Multiplexed Address and Data Bus.
AD[4:0] = Address inputs in multiplexed mode. See A[4:0] for usage.
Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions
Pin Name(s) Mode(s) Functional Description
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 13
DO-009643-DS, Issue 2
70 CSN I Chip Select. Active low in µP mode.
71 PWRSTN I Power Reset Not. Low active. DSP hardware reset that after deactivation still leaves the internal circuits
in the software reset mode. In addition, all outputs are forced into high impedance mode when active.
Also functions as RSTN for JTAG control for Revision “C1” DSP/Framer applications.
72 VDD P +3.3V suppl y.
73 VSS — Ground.
74 ALE I Address Latch Enable. In the processor mode, this pin is an input that indicates an active address cycle
on the multiplexed bus.
75 RDN I Read Not. Active low read pulse. This signal enables data bus output buffers during read operations.
76 WRN I Write Not. Active low write pulse. This signal is used as a standard processor data write control signal.
77
78
79
80
81
82
83
84
TA19
TA18
TA17
TA16
TA15
TA14
TA13
TA12
I/O External TDM. Not used for this application. Per application schematic, do not connect.
85 P5IO I Programmabl e Input Pin fo r Revision “B2” DSP/Framer applications.
TCK. Boundary-scan clock. A ppli cab le t o Rev isi on “C1 ” DS P/Fr amer app lic atio ns o nly, for JTAG s upp ort.
86 VSS — Ground.
87 SYTCK O Not used for this application. Per app lic atio n schem atic , do not connect .
88 VDD P 3.3V supply.
89
90
91
92
93
94
95
96
97
98
TA11
TA10
TA9
TA8
TA7
TA6
TA5
TA4
TA3
TA2
I/O External TDM. Not used for this application. Per application schematic, do not connect.
99 TA1/TXA1
SERIAL I/O Not used for this application. Internally configured as output.
UTOPIA I/O TXA1 - ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
100 TA0/RXA1
SERIAL I/O Not used for this application. Internally configured as output.
UTOPIA I/O RXA1 - ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
101 VSS — Ground.
102 VDD P +3.3V supply.
103 TXCLK SERIAL I/O TXCKA - Transmit clock for channel A. Framed = I; unframed = O.
UTOPIA I TXCLK - ATM UTOPIA Level 1 and 2 Transmit Clock. Synchronizes all signal transfers from the ATM
to the PHY device.
104 DP2 SERIAL I/O TXCKB - Transmit clock for channel B. Framed = I; unframed = O.
UTOPIA I TXDT2 - ATM UTOPIA Level 1 and 2 Transmit Data. Byte-Wide True Data from the ATM to the PHY
device.
105 RXCLK SERIAL O RXCKA - Receive clock for channel A.
UTOPIA I RXCLK - ATM UTOPIA Level 1 and 2 Receive Clock. Synchronizes all signal tr ansfers from the ATM
to the PHY device.
106 DP8 SERIAL O RXDA - Receive serial data for channel A.
UTOPIA O RXDT0 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions
Pin Name(s) Mode(s) Functional Descri ption
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions14 DO-009643-DS, Issue 2
107 DP9 SERIAL O RXDB - Receive serial data for channel B.
UTOPIA O RXDT1 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
108 DP10 SERIAL O RXCKB - Receive clock for channel B. This pin is the same as BRXCK for applications bypassing the
on-chip framer.
UTOPIA O RXDT2 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
109 VDD P +3.3V supply.
110 VSS — Ground.
111 DP0 SERIAL I TXDA - S erial transmit data for channel A.
UTOPIA I TXDT0 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
112 RXSOFB/RXCLAV SERIAL O RXSOFB - Receive start of frame for channel B.
UTOPIA O RXCLAV - ATM UTOPIA Level 1 and 2 Receive Cell Available Signal. Used by the PHY layer device
to indicate that the receive buffer has a new cell.
113 DP1 SERIAL I TXDB - S erial transmit data for channel B.
UTOPIA I TXDT1 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
114 DP7 SERIAL I/O Not used for this application. Internally configured as output.
UTOPIA I TXDT7 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
115 DP3 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA I TXDT3 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
116 DP4 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA I TXDT4 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
117 DP5 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA I TXDT5 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
118 DP6 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA I TXDT6 - ATM UTOPIA Level 1 and 2 Transmit Dat a. Byte-Wide True D ata from the ATM to the PHY
device.
119 TBAUD/TXCLAV SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA O TXCLAV - ATM UTOPIA Level 1 and 2 Transmit Cell Available Signal. Used by the PHY layer device
to indicate that there is space available for a new cell.
120 DP15 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA O RXDT7 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
121 DP12 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA O RXDT4 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
122 DP11 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA O RXDT3 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
123 DP14 SERIAL I/O Not used for this application. Per application schematic, do not connect.
UTOPIA O RXDT6 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
124 DP13 SERIAL O Not used for this application. Per application schematic, do not connect.
UTOPIA O RXDT5 - ATM UTOPIA Level 1 and 2 Receive Data. Byte-Wide True Data from the PHY to the ATM
device.
125 TXSOFA/TXSOC SERIAL I TXSOFA - Transmit Start of frame for channel A.
UTOPIA I TXSOC - ATM UTOPIA Level 1 and 2 Transmit Start of Cell (active high). This bit is true on the first
byte of the transmitted cell from the ATM to the PHY.
Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions
Pin Name(s) Mode(s) Functional Description
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 15
DO-009643-DS, Issue 2
126 RXSOFA/RXSOC SERIAL O RXSOFA - Receive Start of frame for channel A.
UTOPIA O RXSOC - ATM UTOPIA Level 1 and 2 Receive Start of Cell (active high). This bit is true on the first byte
of the transmitted cell from the PHY to the ATM.
127 VSS — Ground.
128 AVDD P AVDD. Digital +3.3V supply for VCO.
129 AVSS — AVSS. Ground pin for VCO. Connect to digital ground as per schematic.
130 XTLI I Crystal Oscillator Input. Oscillator input. It accepts a free running external clock at subrate of the internal
VCO/PLL (see board recommendations).
131 XTLO O Crystal Oscilla to r Outpu t. Connects to one crystal terminal and capacitor.
132 AVSS — AVSS. Ground pin for VCO. Connect to digital ground as per schematic.
133 VSS — Ground.
134 PIP/POP/TXA0
SERIAL I/O Not used for this application. Per applicati o n schem atic, do not connect.
UTOPIA I/O TXA0 - ATM UTOPIA Level 2 Transmit Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
135 TXSOFB/TXEN SERIAL I TXSOFB - Transmit Start of Frame for cha n nel B.
UTOPIA I TXEN - ATM UTOPIA Level 1 and 2 Transmit Enable (active low). The ATM layer device uses this pin
to throttle the rate at the octet boundary.
136 PIP/POP/RXEN SERIAL I Not used for this application. Terminate with a pull-up resistor.
UTOPIA I RXEN - Receive Enable (active low). The ATM layer device uses this pin to throttle the rate at the octet
boundary.
137 PIP/POP/RXA0
SERIAL I/O Not used for this application. Internally configured as output.
UTOPIA I/O RXA0 - ATM UTOPIA Level 2 Receive Address. (I) Driven by the ATM to PHY layer to select the
appropriate PHY device and port.
Not used for ATM UTOPIA Level 1 applications, internally configured as output.
138 QSO O
2B1Q and PAM: QSOA, QSOB - Level Display 2 Serial Data Output. Serial data for level display 2.
Data format the same as ISO.
CAP: QSOA, QSOB - Quadrature Serial Output. Quadrature constellation display serial output. Data
format the same as ISO.
139 ISO O
2B1Q and PAM: ISOA, ISOB - Level Display 1 Serial Data Output. Serial data for level display 1. Data
format is asynchronous with 12 bits of data and start and stop bits.
CAP: ISOA, ISOB - In-phase Serial Output. In-phase constellation display serial output. Data format is
asynchronous with 12 bits of data and start and stop bits.
140 SOCK O 2B1Q and PA M: Serial Data Clock. For ISO and QSO data outputs.
CAP: Serial Data Clock. For ISO and QSO constellation data outputs.
141 POP2A O POP2A - Configured as a programmable output after power-up for Channel A.
142 XSB1A O External Strobe1 of DSP A. One of two strobes from the DSP that are synchronized with the internal
signal processing clock.
143 XSB0A O External Strobe0 of DSP A. One of two strobes from the DSP that are synchronized with the internal
signal processing clock.
144 VDD P +3.3V supply.
Table 12. 144-Pin Dual-Channel DSP/Framer Signal Descriptions
Pin Name(s) Mode(s) Functional Descri ption
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions16 DO-009643-DS, Issue 2
Boundary-Scan Testing
Four pins are provided for compliance to IEEE Standard 1149.1 (JTAG) for boundary scan testing. These DSP pins
are used to control and communicate with the boundary-scan logic. JTAG support is available only in Revision “C1”
of the DSP/Framer. Table 13 provides a list of the four JTAG pins:
Note: All of the following pins are 5V tolerant:
All Input (I) signal pins except XTLI
All Input/Output (I/O) signal pins
No Output (O) signal pins except INTA, INTB, and POP2A
Table 13. Boundary-Scan Pins
144-Pin
DSP/Frame r Re vision “C1 ”
Pin # JTAG Description
9 TMS - Test Mode Selec t
18 TDI - Test Data Input
29 TDO - Test Data Output
85 TCK - Test Clock
Table 14. Dual-Channel DSP/Framer E lectrical Character istics
Parameters Min Nom Max Unit Test Conditions/Comments
Absolute Maxim u m Ratings
Power Supply Voltag e, VDD — — 3.6 V
Power Supply Voltage, AVDD — — 3.6 V
Input Voltage GND – 0.3 —5.5 V
Storage Temperature –40 —125 °C
Junction Temperature — — 125 °C
Recommended Operating Conditions
Power Supply Voltag e, VDD 3.13 3.3 3.47 V
Power Supply Voltage, AVDD 2.75 3.3 3.47 V
Input Voltage GND – 0.3 3.3 5.5 V
Operating Tem perature –40 25 85 °C
Digital Specifications
I/O Levels TTL and/or CMOS compatible
Digital Inputs
Input Low Voltage, VIL –0.3 00.8 VFor all inputs except XTLI. For XTLI, the maximum VIL
is VDD/2.
Input High Vol tag e, VIH 2.0 3.3 5.25 V
Digital Outputs
Output Low Voltage, VOL — 0 0.4 VCurrent sink, IOL, ≤ 3.5 mA
Output High Voltage, VOH
for Rev. B2 of the DSP 2.4 3.3 — V Current load, IOH, ≤ 6 mA for all pins
Output High Voltage, VOH
for Rev. C1 of the DSP 2.4 3.3 — V Current load, IOH, ≤ 6 mA for all non-UTOPIA pins
Current load, IOH, ≤ 10 mA for all UTOPIA pins
DC Specifications
Input Leakage Current, ILI 10 — — µAInput voltage, VI, between 0 volts and VDD
High-Z Leakage Current, ILO 10 — — µAOutput voltage, VO, between 0 volts and VDD
Input Capacitan ce, C IN (fc = 1 MHz) — 6 — pF
I/O Capacitance, CIO (fc = 1 MHz) —10 —pF
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 17
DO-009643-DS, Issue 2
Note the following layout guidelines:
1. We recommend not more than 4 DSPs per clock source.
2. The clock source distribution network should be routed in a star pattern ensuring equal distances to all DSPs.
3. Place a series termination resistor as close to the clock source as possible.
4. Refer to the “Critical Clock and Signal Layout Guidelines” section in Chapter 3 of the Design Guide for further information.
Table 15. Clock Specifications for XTLI Pin
Timing Parameters Voltage
Duty Cycle Rise Time
Maximu m (n sec ) Fall Time
Maximum (nsec) Overshoot
Maximum Undershoot
Maximum
40 - 60% 443.3V + 5% 100 mV below ground
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions18 DO-009643-DS, Issue 2
Customer Data Interface
The customer data interface includes data signals, control signals, and address signals. The GlobespanVirata 144-
pin DSP has an on-chip programmable framer for handling multiple TC layer framing formats. The supported,
software selectable, framing formats include Serial Mode and Asynchronous Transfer Mode (ATM) UTOPIA Level
1 and Level 2. Please note only one UTOPIA Level 1 interface is supported per dual channel DSP/Framer . Table 16
lists corresponding pins for both Serial and UTOPIA Modes.
* Not used for UTOPIA Level 1 applications.
Table 16. 144-Pin DSP Data Interface Pin Usage
Pin Name Pin
Number UTOPIA Mode Serial Mode
DP0 111 I TXDT0 I TXDA
DP1 113 I TXDT1 I TXDB
DP2 104 I TXDT2 I/O TXCKB
DP3 115 I TXDT3 I/O Not used
DP4 116 I TXDT4 I/O Not used
DP5 117 I TXDT5 I/O Not used
DP6 118 I TXDT6 I/O Not used
DP7 114 I TXDT7 I/O Not used
DP8 106 O RXDT0 O RXDA
DP9 107 O RXDT1 O RXDB
DP10 108 O RXDT2 O RXCKB
DP11 122 O RXDT3 I/O Not used
DP12 121 O RXDT4 I/O Not used
DP13 124 O RXDT5 O Not used
DP14 123 O RXDT6 I/O Not used
DP15 120 O RXDT7 I/O Not used
TXCLK 103 I TXCLK I/O TXCKA
TXSOFA/TXSOC 125 I TXSOC I TXSOFA
TBAUD/TXCLAV 119 O TXCLAV I/O Not used
RXCLK 105 I RXCLK O RXCKA
RXSOFA/RXSOC 126 O RXSOC O RXSOFA
RXSOFB/RXCLAV 112 O RXCLAV O RXSOFB
PIP/POP/TXA0 134 I TXA0* I/O Not used
TA1/TXA1 99 I TXA1* I/O Not used
XSB0B/TXA2 39 I TXA2* I/O Not used
XSB1B/TXA3 40 I TXA3* I/O Not used
TXA4 41 I TXA4* I/O Not us ed
PIP/POP/RXA0 137 I RXA0* I/O Not used
TA0/RXA1 100 I RXA1* I/O No t us ed
RXA2 44 I RXA2* I/O Not used
RXA3 45 I RXA3* I/O Not used
RXA4 43 I RXA4* I/O Not used
TXSOFB/TXEN 135 I TXEN I TXSOFB
PIP/POP/RXEN 136 I RXEN I Not used
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 19
DO-009643-DS, Issue 2
ATM UTOPIA Level 1 and Level 2
Figure 5 and Figure 6 detail the interface for standard ATM UTOPIA Level 1 and Level 2. Dual-channel ATM over
UTOPIA Level 2 or single-channel ATM over UTOPIA Level 1 is supported for SHDSL, SDSL 2B1Q, and HDSL2.
Figure 5. UTOPIA Level 1 Signals
Figure 6. UTOPIA Level 2 Signals
TXDT[7:0]
TXCLK
TXSOC
TXEN
RXDT[7:0]
RXCLK
RXSOC
RXEN
RXCLAV
TXCLAV
ATM layer
device
Globespan
Virata
DSP/Framer
NTR
(CO)
TXDT[7:0]
TXCLK
TXSOC
TXEN
RXDT[7:0]
RXCLK
RXSOC
RXEN
RXCLAV
TXCLAV
TXA[4:0]
RXA[4:0]
ATM layer
device
NOTE: RXSOC, RXCLAV, and TXCLAV are tri-state active high
signals and need appropriate pull-down terminations.
Globespan
Virata
DSP/Framer
NTR
(CO)
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions20 DO-009643-DS, Issue 2
Transmit, receive, and tri-state timing is shown in Figure 7, Figure 8, and Figure 9. Timing parameters are shown in
Table 17.
Figure 7. Transmit ATM Timing
Figure 8. Receive ATM Timing
Figure 9. Tri-State ATM Timing
TXCKA
TXDT[7:0]
TXA[4:0]
TXSOC
TXEN
Tcyc
TAhld
TXCLAV
TAdel
TAsu
RXCKA
RXEN
RXA[4:0]
Tcyc
TAhld
RXDT[7:0]
RXSOC
RXCLAV TAdel
TAsu
TXCK
RXCK
TAdel TAdel
TXDT[7:0]
RXSOC
RXCLAV
TXCLAV
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 21
DO-009643-DS, Issue 2
Table 17. ATM Timing Parameters
Specifi-
cation Description Min Max
Tcyc Clock Period 40 ns
TAsu Input Setup to Clock Rising Edge 4 ns
TAhld Input Hold from Clock Rising Edge 1 ns
TAdel Output Delay from Clock Rising Edge 15 ns
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions22 DO-009643-DS, Issue 2
Supported Serial Int erfaces
The following serial inte rfaces are supported per application:
SHDSL: Dual or single-channel Slotted E1, Slotted T1, and Nx64 Interfaces (refer to the SHDSL Design
Guide, GSDG-0014, for a detailed description).
HDSL2: Single-channel Fixed T1 Interface (refer to the HDSL2 Design Guide, GSDG-0013, for a detailed
description).
SDSL CAP: Single-channel Slotted E1, Slotted T1, and Nx64 Interfaces (refer to the SDSL CAP Design
Guide, GSDG-0012 for a detailed description). Dual-channel supported in unframed mode only (no physical
layer f raming).
NOTE:Each Type field shows the directiona l flow for the CO /CP with Framer, or CO/CP with out the inte grated Framer
(Bypass mode) from the view of the DSP/Framer.
Figure 10 and Figure 11 depict the directions of the framed and unframed serial data/clock interfaces.
Table 18. Summary of Transceiver Serial Interface Leads
Name Type
CO/Framer Type
CO/Framer
Bypass Type
CP/Framer Type
CP/Framer
Bypass Description
Transmission Interface
TXD[A,B] I I I I Transmit Data for channels A and B
TXCK[A,B]IOIO
Transmit Bit Clock for channels A and B (see
NOTE)
RXD[A,B] O O O O Receive Dat a for channels A and B
RXCK[A,B] O O O O Receive Bit Clock for channels A and B
(see NOTE)
TXSOF[A,B] I N/C I N/C Transmit start of Frame for channels A and B
RXSOF[A,B] O N/C O N/C Receive start of Frame for channels A and B
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 23
DO-009643-DS, Issue 2
Figure 10. *Framed Serial Data/Clock Interface
Figure 11. *Unframed (Framer Bypass Mode) Serial Data/Clock Interface.
* Note that TX and RX clocks must have the same frequency at both the CO and CPE.
DSL
Termination
Unit
Central Office
DSL
Termination
Unit
Remote
TXD[A/B]
TXCK[A/B]
TXSOF[A/B]
RXD[A/B]
RXCK[A/B]
RXSOF[A/B]
RXD[A/B]
RXCK[A/B]
RXSOF[A/B]
TXD[A/B]
TXCK[A/B]
TXSOF[A/B]
DSL
Termination
Unit
Central Office
DSL
Termination
Unit
Remote
TXD[A/B]
TXCK[A/B]
RXD[A/B]
RXCK[A/B]
RXD[A/B]
RXCK[A/B]
TXD[A/B]
TXCK[A/B]
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions24 DO-009643-DS, Issue 2
The relationship between the data and the Start Of Frame signal (SOF) to the clock pulse is illustrated below. Figure
12 and Figure 13 depict E1, which has sync byte in time slot 0. Figure 14 and Figure 15 depict T1, which has an F-
bit signifying the start of time slot 0. For unframed mode, the SOF is not applicable. Figure 16 and Figure 17 depict
Nx64 operation.
Figure 12. Transmit Slotted E1 Interface Tim ing
Figure 13. Receive Slotte d E1 Interface Timing
102378255254 9
TS0 TS1TS31
NOTE: The transmit start of frame pulse
must be low for at least 8 clock cycles.
TXCKA/B
TXSOFA/B
TXDA/B
(32 TS )
(TXSOFA/B)
102378255254 9
TS0 TS1TS31
RXCKA/B
RXSOFA/B
RXDA/B
(32 TS)
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 25
DO-009643-DS, Issue 2
Figure 14. T1 Interface Transmit Tim ing for HDSL2
Figure 15. T1 Interfa ce Rece ive Timing for HDSL2
102378192191 9
TS0 TS1TS23
HTXCKA,
HTXCKB
HTXSOFA,
HTXSOFB
HTXDA,
HTXDB
(24 TS)
10
F
bit
NOTE: The transmit start of frame pulse (TXSOFA)
must be low for at least 8 clock cycles.
102378192191 9
TS0 TS1TS23
HRXCKA,
HRXCKB
HRXSOFA,
HRXSOFB
HRXDA,
HRXDB
(24 TS)
10
F
bit
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions26 DO-009643-DS, Issue 2
Figure 16. Transmit Nx64 Interface Timing
Figure 17. Receive Nx64 Interface Timing
1023789
TXCKA/B
TXDA/B
1023789
RXCKA/B
RXDA/B
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 27
DO-009643-DS, Issue 2
Figure 18 and Figure 19 show serial transmit and receive timing. This timing applies to all products (SDSL, HDSL2,
and SHDSL - ILD2).
Figure 18. Serial Transmit Timing
Figure 19. Serial Receive Timing
Table 19. Serial Timing Parameters
Specification Description Min Max
Tcyc Clock Period 50 ns
TFsu Input Setup to Clock Falling Edge 10 ns
TFhld Input Hold from Clock Falling Edge 5 ns
TRdelLH Output Delay From Low to High 20 ns
TRdelHL Output Delay From High to Low 20 ns
TFsu TFhld
Tcyc
TXCKA/B
TXDA/B
TXSOFA/B
TRdelLH TRdelHL
Tcyc
RXCKA/B
RXDA/B
RXSOFA/B
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions28 DO-009643-DS, Issue 2
Input Timing Parameters
Specifications are defined in terms of setup and hold times of the data inputs relative to a reference clock.
Table 20. Input Timing Par a meters
Figure 20. Input Timing Diagram
Input
Signal Pin Edge Setup
(nsec) Hold
(nsec)
TxDA
TxDB TXCKA (103)
TXCKB (104) +/- 10 5
setup
hold
+
-
Reference clock
Data input, relative
to the rising edge
setup
hold
D ata inp u t , re la t ive
t o the falling edg e
This timing applies to ALL data inp uts and their respective clocks
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 29
DO-009643-DS, Issue 2
Output Timing Parameters
Specifications are defined in terms of propagation delay from a reference clock edge to the data output stable
condition.
NOTE:All loads are 35 pF, unless noted otherwise.
Add 1.5 nsec per 10 pF of additional loading.
Rise and fall times are 5 nsec.
Table 21. Output Timing Parameters
Figure 21. Output T im ing Diagram
Output Pin Edge Min
(nsec) Max
(nsec)
All outputs to high-Z PWRSTN (71) +50
RxDA
RxDB RXCKA (105)
RXCKB (108) +/- 20
ISO/QSO SOCK (140) +10
+
-
Reference clock
Data output, r ela tive
to the rising edge
Data output, relative
to t he fall ing edge
delay
delay
This timing applies to ALL data outputs and their respective clocks
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions30 DO-009643-DS, Issue 2
Host Processor Interfaces
GlobespanVirata chip sets easily interface with multiplexed (Intel style), generic non-multiplexed, and non-
multiplexed Motorola style host processors. The MOD pins on the DSP must be set according to Table 22 for the
type of processor interface required. These pins should be set (pulled high or low) using the resistor values shown
in the Customer Schematics.
Table 22. MOD Settings
NOTE:A value of 1 refers to pulled high and 0 refers to pulled low.
NOTE:Each Type field show s the direc tiona l flow for the CO/C P with Fram er, or CO/CP with out the inte grated Fram er
(Bypass mode) from the view of the DSP/Framer.
Figure 10 and Figure 11 depict the directions of the framed and unframed serial data/clock interfaces.
Processor MOD2 MOD1 MOD0 RDN Function WRN Function ALE Use
Multiplexed 100 RDN WRN ALE
Motorola 001 RD/WRN DSN n/a (pulled low)
Other non-multiplexed 000 RDN WRN n/a (pulled low)
Table 23. Summary of Transceiver Host Interface Leads
Name Type
CO/Framer Description
AD[0-7] I/O 8 Bit Multiplexed Ad d ress/Data Bus
CSN I DSP Chip Select
ALE I Multiplexed Processor Address Latch Enable
WRN I Write S trobe
RDN I Read Strobe
PWRSTN I Power Reset Not
INTNA, INTNB O DSP/Framer Interrupts
MOD[2,1,0] I Host Bus Control Modes
A[0-4] I Non-multiplexed Address Bus
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 31
DO-009643-DS, Issue 2
Multiplexed Bus Mode Timing Requirements and Characteristics
Table 24. Read Cycle Tim ing C harac ter is tics
Table 25. Read Cycle Timing Requi reme nts
Table 26. Write Cycle Timing Requirements
Parameter Symbol Max ( ns) Test Conditions/Comments
Address valid to data valid tHAVDV 35
Capacitive load on HAD[7:0] is 100 pF
Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Read strobe active to data valid tHRDNLDV 25
Capacitive load on HAD[7:0] is 100 pF
Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Bus active after read tHRDNHDX 10
Parameter Symbol Min (ns) Test Conditions/Comments
Chip select setup time before read strobe tHCSNLHRDNL 0Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Chip select hold time after read strobe tHRDNHHCSNH 0Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Address setup time before latch strobe low tHAVHALEL 10
Address hold time after latch strobe low tHALELHAX 5
Address latch strobe width tHALEHHALEL 10
Address setup time before read strobe tHAVHRDNL 10
Read strobe inactive before next cycle tHRDNLHHALEH 10
Inter-a ccess cycle time (not shown ) tHALEHHALEH 200 The minimum time between successive reads
Parameter Symbol Min (ns) Test Conditions/Comments
Inter-a ccess cycle time (not shown ) tHALELHALEL 200 The minimum time between successive writes
Chip select setup time before write strobe low tHCSNLHWRNL 10 Active HCSNA overlap with active HWRN defines the
effective HWRN pulse
Write strobe width tHWRNLHWRNH 20
Chip select hold time after write strobe high tHWRNHHCSNH 0Active HCSNA overlap with active HWRN defines the
effective HWRN pulse
Address setup time before latch strobe low tHAVHALEL 10
Address hold time after latch strobe low tHALELHAX 5
Data setup time before write strobe tHDVHWRNH 10
Data hold time after write strobe tHWRNHHDX 2
Address latch strobe width tHALEHHALEL 10
Address setup time before write strobe tHAVHWRNL 0
Write strobe inactive before next cycle tHWRNHHALEH 10
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions32 DO-009643-DS, Issue 2
Figure 22. Multiplexed Bus Mode Timing Diagram
Data DataHAD
HRDN
HWRN
HCSNA
READ WRITE
tHALEHHALEL
HALE
tHAVHALEL tHALELHAX
tHAVDV
tHAVHRDNL tHRDNLDV
tHCSNLHRDNL tHRDNHHCSNH
tHRDNHHALEH
tHRDNHHDX
Addr. Addr.
tHALEHHALEL
tHAVHALEL tHALELHAX
tHAVHWRNL
tHDVHWRNH
tHWRNHHDX
tHWRNHHCSNH
tHCSNLHWRNL
tHWRNHHALEH
tHWRNLHWRNH
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 33
DO-009643-DS, Issue 2
Non-multiplexed Bus Mode Timing Requirements and Characteristics
Table 27. Read Cycle Tim ing C harac ter is tics
Table 28. Read Cycle Timing Requi reme nts
Table 29. Write Cycle Timing Requirements
Parameter Symbol Max ( ns) Test Conditions/Comments
Address valid to data valid tHAVHDV 35
Capacitive load on HD[7:0] is 100 pF
Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Read strobe active to data valid tHRDNLHDV 25
Capacitive load on HD[7:0] is 100 pF
Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Bus active after read tHRDNHHDZ 10
Parameter Symbol Min (ns) Test Conditions/Comments
Chip select active before read tHCSNLHRDNL 0Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Chip select hold time after read tHRDNHHCSNH 0Active HCSNA overlap with active HRDN defines the
effective HRDN pulse
Address setup time before read tHAVHRDNL 5
Address hold time after read tHRDNHHAX 5
Inter-a ccess cycle time (not shown ) tHRDNLHRDNL 200 The minimum time between successive reads
Parameter Symbol Min (ns) Test Conditions/Comments
Inter-a ccess cycle time (not shown ) tHWRNLHWRNL 200 The minimum time between successive writes
Chip select setup time before write strobe low tHCSNLHWRNL 10 Active HCSNA overlap with active HWRN defines the
effective HWRN pulse
Write strobe width tHWRNLHWRNH 20
Chip select hold time after write tHWRNHHCSNH 0Active HCSNA overlap with active HWRN defines the
effective HWRN pulse
Address setup time before write tHAVHWRNL 10
Address hold time after write tHWRNHHAX 5
Data setup time before write tHDVHWRNH 10
Data hold time after write tHWRNHHDX 2
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions34 DO-009643-DS, Issue 2
Figure 23. Non-multiplexed Bus Mode Timing Diagram
Address
tHCSNLHRDNL
tHAVDV
tHAVHRDNL
tHRDNHDZtHRDNLDV
tRDNHHAXH
Data
tHRDNHHCSNH
Address
Data
HA
HD
HRDN
HWRN
HCSNA
tHCSNLHWRNL tHWRNHHCSNH
tHAVHWRNL
tHWRNLDV tHWRNHHDX
tHWRNLHWRNH
tHWRNHHAX
READ WRITE
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 35
DO-009643-DS, Issue 2
Motorola Bus Mode Timing Requirements and Characteristics
Table 30. Read Cycle Tim ing C harac ter is tics
Table 31. Read Cycle Timing Requi reme nts
Table 32. Write Cycle Timing Requirements
Parameter Symbol Min (ns) Max (ns) Test Conditions/Comments
Address valid to data valid tHAVDV 20
Data set (DSN) strobe active to data valid tDSNLDV 10
Bus active after data set strobe inactive tDSNHHDX 6
Parameter Symbol Min (ns) Max (ns) Test Conditions/Comments
Inter-a ccess cycle time (not shown ) -200 The minimum time between successive reads
Address setup time before chip select low tHAVHCSNL 5
R/Wn setup before chip select low tHRWNHHCSNL 5
R/Wn hold time after chip select inactive tHCSNHHRWNL 0
Address hold time after chip select inactive tDSNHHAX 5
Chip select setup time before data set strobe tHCSNLDSNL 5
Chip select hold time after data set strobe tDSNHHCSNH 0
Parameter Symbol Min (ns) Max (ns) Test Conditions/Comments
Inter-a ccess cycle time (not shown ) -200 The minimum time between successive writes
Address setup time before chip select low tHAVHCSNL 5
R/Wn setup before chip select low tHRWNHHCSNL 5
R/Wn hold time after chip select inactive tHCSNHHRWNH 0
Data setup time before data set strobe active tDVDSNL 5
Data set strobe width for write operation tDSNLDSNH 5
Address hold time after chip select inactive tDSNHHAX 5
Chip select setup time before data set strobe tHCSNLDSNL 5
Chip select hold time after data set strobe tDSNHHCSNH 0
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions36 DO-009643-DS, Issue 2
Figure 24. Motorola Bus Mode Timing Diagram
Address
tHRWNHHCSNL
tHAVDV
tHAVHCSNL
tDSNHHDX
tHCSNLDSNL
tDSNHHAX
Data
tDSNHHCSNH
Address
Data
HA
HD
HDSN
(HWRN)
HCSNA
tHCSNLDSNL tDSNHHCSNH
tHAVHCSNL
tDSNLDSNH
tHCSNHHRWNHtHRWNLDSNL
READ WRITE
tDSNLDV
tHCSNHHRWNL
tDVDSNL tDSNHHDX
tDSNHHAX
R/W
(HRDN)
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 37
DO-009643-DS, Issue 2
GS3137 ILD2 Specificati ons
Figure 25. GS3137 28-pin ILD2 Pin Diagram
NOTE:The EPTSSOP is required to support a transmit power of higher than 15 dbm (HDSL2 and asymmetric PSD
options for SHDSL).
Table 33. GS3137 ILD2 Signal Descriptions
Pin Symbol Type Name / Function
1Q1B OData Output to DSP.
2Q0B O
3VDDD PDigital Supply. +3.3V.
4GNDD PDigital Ground.
5MCLK IMaster Clock from DSP. Input to PLL which generates oversampling clocks.
6CSD IControl Input from DSP. Configures the devic e.
7DACA IData Input from DSP.
8DACB I
9Q0A OData Output to DSP.
10 Q1A O
11 RBIAS IEx ternal Bias Resistor Connection.
12 GNDA PAnalog Ground.
13 VDDA PAnalog Supply. +5V.
14 HYBN INega tive Input from H ybrid Ne twork. See NOTE.
15 HYBP IPositive Input from Hybrid Network. See NOTE.
16 RCVN INega tive Input from Line Transformer. See NOTE.
17 RCVP IPositive Input from Line Transformer. See NOTE.
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
GS3137
VDDD
GNDA
LDOUTP
VDDA
LDOUTN
GNDA
VDDA
VREFN
VCM
GNDA
RCVP
RCVN
HYBP
VREFP
Q1B
Q0B
VDDD
GNDD
MCLK
CSD
DACA
DACB
Q0A
Q1A
RBIAS
GNDA
HYBN
VDDA
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions38 DO-009643-DS, Issue 2
NOTE:Refer to your application schematics for all application-specific pin assignments.
Pin Symbol Type Name / Function
18 GNDA PAnalog Ground.
19 VREFP IPositive Reference Voltage.
20 VCM ICommon-mode Reference Voltage.
21 VREFN INegative Reference Voltage.
22 VDDA PAnalog Supply. +5V.
23 GNDA PAnalog Ground.
24 LDOUTN ONegative Line Driver Output. See NOTE.
25 VDDA PAnalog Supply. +5V.
26 LDOUTP OPositive Line Driver Output. See NOTE.
27 GNDA PAnalog Ground.
28 VDDD PPLL Suppl y 3.3V. See NOTE.
Table 34. GS3137 ILD2 Electrical Characteristics
Parameter Conditions Min Nom Max Unit
Absolute Maximum Ratings
Power Supply Voltages 5V supply 7.0 V
3.3V supply 3.6 V
Recom m ended Operatin g Conditions
Power Supply Voltages 5V supply 4.75 5 5.25 V
3.3V supply 3.135 3.3 3.465 V
Operating Temperature –-40–85°C
Digital Inputs
Input Logic High VIH IIH<10µADV
DD-1 – – V
Input Logic Low VIL IIH<10µA - 0.3 – 0.8 V
Digi tal Ou tputs
Output Logic High, VOH IOH=-20µADV
DD-0.5 – – V
Output Logic Low, VOL IOL=20µA––0.4V
Table 33. GS3137 ILD2 Signal Descriptions
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 39
DO-009643-DS, Issue 2
Manufacturing Information
Thermal Performance
NOTE:oC/W = oC/Watts
LPM = Linear Feet Per Minute (LPM/196.8 = Meter/Second)
ΘJA= Thermal Re sistance - Junction to Ambient
Thermal data is obtained by mounting the chip set to a JEDEC standard board. The thermal performance in a custom
board may vary. The following describes JEDEC standards:
In August (1996), the Electronics Industries Association released Standard EIA/JESD51-3 titled, “Low Effective
Thermal Conductivity Test Board for Leaded Surface Mount Packages.” This Standard provides guidelines for
design of the test board used in taking thermal resistance measurements of integrated circuit packages. Prior to
release of this Standard, thermal resistance data for similar packages varied greatly across the industry because of
the use of different test board designs. In particular, the characteristics of the test board were found to have a
dramatic impact on the measured Theta JA (ΘJA). As the industry converts to using this standard test board design,
the variation in thermal resistance data caused by the board should be minimized.
Key features of the standard test board design are:
• Board thickness: 0.062”
• Board dimension: 3.0" x 4.5" for packages < 27.0 mm
• Board dimension: 4.0" x 4.5" for packages > 27.0 mm
The JEDEC method for specifying the thermal performance of ICs does not reflect thermal performance at the line
card or system level. Equipment OEMs must take thermal management into account in the design of systems
featuring high-density line cards.
Table 35. Device Manuf acturing Characteristics
Parameter Chip(s) Conditions
Maximum Temperature
Gradient DS P and AFE
JEDEC Moisture Sensitivity Class 3
•Unsealed parts may be exposed to
30°C 60% relative humidity for up to
one week
•If exposed more than one week, parts
must be baked at 125°C for 7 hours
Solder Profile DSP and AFE
•6°C/second maximum temperature
ramp rate
•10-40 seconds at 220°C-225°C (do
not exceed 225°C)
•120-180 seconds above solder liqui-
dus (approxim atel y 183°C)
Table 36. Thermal Resistance
Product ΘjA at 0 LPM
Air Velocity (oC/W)
ΘjA at 200 LPM
Air Velocity (oC/W)
144 LPQ2 DSP 16.0 13.6
28 SSOP AFE 49.8 43.9
28 EPTSSOP AFE 37.9 32.5
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
40 DO-009643-DS, Issue 2
DSL Chip Set Outline Diagrams
Figure 26. 144 LPQ2 and TQFP Dual-Channel DSP/Framer Outline Diagram
NOTE:144 TQFP DSP/Fram er is for dual-channel SDSL CAP unframed applications only.
22.0 B SC
20.0 B SC
20. 0 BSC
0.50 BSC 0.19/0.27 1.60 MAX
1.35/1.45
0.05/0.15
SEE DETAIL A
0.25
1.0 REF
0-7o
0.45/0.75
DETAIL A
Note: All dimensions are in millimeters.
June 25, 2002 XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions 41
DO-009643-DS, Issue 2
Figure 27. Bottom View of an LPQ2 Package
NOTE:Refer to Applicati on Note AN-026, “Differences Between TQFP and LPQ2 Packages for GlobeSpan
G22xx-series DSP/Framers,” for details on the use of the LPQ2 package.
22.0 BSC
20.0 BSC
20.0 BSC
15.0 REF
15.0 REF
2.90 x 45
4 PLACES
o
Note: All Dimensions are in millimeters (mm).
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
42 DO-009643-DS, Issue 2
Figure 28. GS3137-08F ILD2 in 28 SSOP package
0.22 - 0.38
2.00
MAX.
0.55 - 0.95
DETAIL A
0 - 8
1.85
MAX.
0.65 TYP.
5.60 MAX.
7.40 - 8.20
DETAIL A
1
10.50 MAX.
o
o
28
14
15
NOTE: All dimensions a re in millimeters.
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
43 DO-009643-DS, Issue 2
Figure 29. GS3137-08T ILD2 in 28 EPTSSOP package (Required to support HDSL2 and asymmetric PSD options for
SHDSL).
NOTE:Please make sure your PCB design takes into consideration the exposed PAD at the bottom of this package,
which will need to be connected to the analog ground plane. The dimensions for this expos ed pad are 7.1 mm
x 4.4 mm located at the center of the device, as shown in the Bottom View above. Refer to Application Note
AN-022, “Mounti ng Guidelines for GlobeSpan GS3137-08T in a 28-pin EPTSSOP Package,” for detailed
mounting guidelines for this package.
DETAIL A
DETAIL A
1
28
14
15
NOTE:
All dimensions are in millimeters.
1.10
MAX.
0
O
– 8
O
9.7
±
0.1
6.1
±
0.1
0.50 - 0.75
0.245
±
0.055
1.0 TYP.
0.90
±
0.05
8.10 BSC
0.65 BSC 0.10
±
0.05
Seating Plane
7.1
4.4
EXPOSED PAD (BOTTOM) VIEW
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet June 25, 2002
44 DO-009643-DS, Issue 2
XDSL2TM SDSL, HDSL2 and SHDSL - ILD2 Chip Set Order Information
Table 37. DSL Chip Set Part Number
* The exposed PAD TSSOP (EPTSSOP) is required for designs that are upgradeable to SHDSL or
HDSL2.
Table 38. Device Packaging
For additional information, contact GlobespanVirata, Inc. at 1-888-855-4562 (toll-free within the U.S. and Canada)
or 1-732-345-7500.
Visit the GlobeSpan Internet site at www.globespan.net.
This GlobespanVirata, Inc. proprietary document is intended for use as specified in the Non-Disclosure Agreement
(NDA). Reproduction is not permitted.
Specification subject to change without notice.
Printed in USA © GlobespanVirata, Inc. 2002.
GlobespanVirata is a trademark of GlobespanVirata, Inc. All other products or services mentioned are the
trademarks, service marks, or registered service marks of their representative owners.
Product Supports Chip Set DSP/Framer ILD2
SDSL 2B1Q Only Up to 2320 kb/s G2216-208-041PF B2 144 LPQ2
GS2216-208-001P B2 28 SSOP
GS3137-08F* (QTY 2)
SDSL CAP Only Up to 2320 kb/s G2214-208-041DF B2 144 TQF P
GS2214-208-001D B2 28 SSOP
GS3137-08F* (QTY 2)
SHDSL/HDSL2 Up to 2320 kb/s G2237-208-041PT B2 144 LP Q2
GS2237-208-001P B2 28 EPT SSOP
GS3137-08T (QTY 2)
G2237-208-04 1PT C 1 144 LPQ2
GS2237-208-001P C1
Device Part Number Package Preproduction Orders Production Orders
Minimum Order
Quantity Quantity
Multiples Minimum Order
Quantity Quantity
Multiples
DSP GS2216-208-001P B2 144 LPQ2 60 60 240 240
DSP GS2214-208-001D B2 144 TQFP 60 60 240 240
DSP GS2237-208-001P B2 144 LPQ2 60 60 240 240
DSP GS2237-208-001P C1 144 LPQ2 60 60 240 240
AFE GS3137-08F 28 SSOP 50 50 500 500
AFE GS3137-08T 28 EPTSSOP 50 50 500 500
