AS2702-16T - austriamicrosystems AG

AS2702 (SAP4.1)

AS-Interface Slave IC

Data Sheet

Rev. C, January 2001

Key Features

• Interface Device to connect Actuators and Sensor s t o an AS- Interface Bus

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 2 of 18

• Confor m s to AS-Interface Spec. V2.11

• DC Power Extraction f r om the AS-Inter face Bus

• Serial bidir. Dat a Communication with the Bus

• Data Communicat ion Watchdog

• 4-Bit bidir. Data Port plus Strobe t o poll the Sensors and control the Act uators con-

nected

• 4-Bit Param et er Port plus Strobe t o pr ovide Sett ings to the Sensors and Actuat ors

• 24V Power Supply for the Sensors and Act uators

• Periphery Fault Input to signal Hardware Failure of the Sensors and Actuators

• Integ r ated 16 x 8 Bit EEPROM to store (5 + 1)-Bit Slave Address and Set t ings

• 2 LED Output s t o optically flag Slave Unit Oper ation Status

• Operating Temperature T a: - 25 °C … + 85 °C

• Operating Supply Voltage / Bus DC Volt age: typ. 30 V

• Operating Current (O sc. on, Outputs idle): ≤ 6 mA

• Supply for Sensors / Actuators: typ. 24 V, ≤ 50 mA

• Packag e: SOIC 20 for full Functionality;

SOIC 16 for Applications not r equiring the Parameter Port

General Description

AS2702 (SAP4.1) is a new gener at ion AS- int erface slave device conform ing to AS-interface-

specificat ion V2. 11, which supports AS-interf ace bus system s with up to 62 slave modules.

Each slave module is equipped with an AS2702 device, which interfaces the module to the

unshielded 2-wire AS-interface bus for ser ial bidirectional data communication and power ex-

traction.

Data communicat ion over the AS- interface bus t akes place in master slave fashion, which

for esees t hat all slave devices AS2702 connected t o t he bus are sequentially and cyclicly ad-

dressed by a single, centr al master unit. Dat a on t he AS-interface bus ar e Manchester en-

coded and can be found as sin2- pulses with a Vpp of bet ween 3V and 8V on top of the bus’

dc voltage of nominally 30V.

AS2702 regulat es the nominal dc bus voltage of 30V internally down to 5V to supply it’s inter-

nal circuitr y including a 16 x 8 bits EEPRO M, as well as down to a nominal supply level 24V

with a max. loading of 50 m A for the actuat ors and sensors connected to it at t he field side.

Each slave device AS2702 may interface to up to 4 sensor s or 3 actuators. An AS- interface

bus system based on AS2702 may hence link as many as 248 sensors or 186 act uat or s t o a

single mast er unit.

Slave device AS2702 (SAP4.1) is system compatible with predecessor device AS2701A

(ISA3+) : slave modules equipped with AS2702 (SAP4.1) will run in existing AS- int erface bus

systems based on AS2701A (ISA3+).

The AS-inter face concept is well established as a standardized digit al bus system for indus-

trial automation.

Block Diagram

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 3 of 18

Pin Assignment and Description

SOIC 20 SOIC 16 Name Type Note Description

Pin Nr.: Pin Nr.:

1 -- P1 I/O, digital,

pull-up 1, 2 Bidir. param et er port bit 1

2 -- P0 I/O, digital,

pull-up 1, 2 Bidir. param et er port bit 0

3 1 D1 I/O, digital Bidir. data port bit 1

4 2 D0 I/O, digital Bidir. data port bit 0

5 3 DSTBn I/O, digital,

pull-up 1 Data port strobe output; reset - input

6 4 LED1 I/O, digital,

pull-up 1 LED output 1 (IC test input)

7 5 OSC2 O, analog Output to quarz crystal

8 6 OSC1 I, analog Input from quar t z crystal

9 7 U5R O, power Nom. 5V power supply output

10 8 LT G N I, power Neg. supply pin, connecte d

to neg. AS-interf ace bus line;

ground reference.

LTGP

LTGN

UOUT

CDC

U5R

OSC2

OSC1

OSCIL-

LATOR RECEIVE TRANSMIT JABBER

INHIBIT

U5R U5R U5R

U5R

LTGP

-6V

THERMO-

DETECTOR

BANDGAPPORN

TRIMMING

U5R

16 x 8 BIT

SERIAL E

PROM

IMP_POS

IMP_NEG

RESET

threshold

DSTBn

P0...P3

D0...D3

PSTBn

SCL

SDA

PFAULT

LED1

LED2

LOGIC BLOCK

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 4 of 18

11 9 LTGP I, power Pos. supply pin, connected

to pos. AS-interface bus line

12 10 CDC I/O, analog Pin for ext. buffer capacitor

13 11 UOUT O, power Nom. 24V power supply output

14 12 PFAULT I, digital, pull-

up 1 Low-active input to flag failure

of t he sensor s / act uators circuitry con-

nected

15 13 LED2 I/O, digital,

pull-up 1 LED output 2 (IC test input)

16 14 PSTBn I/O, digital,

pull-up 1 Parameter por t strobe output

(IC test input)

17 15 D3 I/O, digital Bidir. data port bit 3

18 16 D2 I/O, digital Bidir. data port bit 2

19 -- P3 I/O, digital,

pull-up 1, 2 Bidir. param et er port bit 3

20 -- P2 I/O, digital,

pull-up 1, 2 Bidir. param et er port bit 2

Notes:

1 T he pull- up structure is a passive high-side cur r ent source with a nom. 10 µA current

2 T he passive pull-up cur r ent sour ce as per note 1 on these paramet er por t pins is off,

if the slave device is programmed with I/O-configuration code 7 and a master data

call is present

Functional, electrical and timing characteris-

tics

All voltages are r eferenced to g round pin LTGN. T im ing is valid for a quar tz crystal frequency

of 5. 333 MHz.

a) Absolute maximum ratings

Symbol Parameter Min. Max. Unit Note

VLTGP Voltage at the positive supply pin - 0.3 40 V 1

VCDC Volage at pin for ext. buf fer capacitor - 0.3 VLTGP +

0.3V V

VU5R Voltage at pins U5R, OSC1, OSC2 - 0.3 7 V

IIN Input cur r ent at any pin, except for LTGP,

CDC - 50 50 mA 2

ESD1 Electrostatic discharge voltage 1500 V 3

ESD2 Electrostatic discharge voltage 200 V 4

ΘSTG Stor age temperatur e - 55 125 V

ΘLEAD Solder temperat ure 260 °C 5

PTOT Max. power dissipation 1 W 6

RTHJA Therm al r esistance SOIC 16 61.2 74.8 °K / W 7

RTHJA Therm al r esistance SOIC 20 58.5 71.5 °K / W 7

Notes:

1 50 V during t > 50 µs; repetition rate < 0.5 Hz

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 5 of 18

2 Lat ch- up im m unity test. Pls. observe max. power dissipation allowed.

3 Human body model: R = 1.5 kOhm; C = 100 pF

4 Machine model; applies only f or LTGP-LTG N

5 260 °C during 10 s (ref low and wave soldering); 360 °C during 3 s for manual solder-

ing. Twofold reflow soldering is acceptable.

6 Free convection, see fig. 1

7 No forced cooling. PCB-surface: 21 cm 2; still air volume around the device: 10 cm3

Fig. 1: Max. acceptable power dissipation relative to am bient temperature

b) Recommended Operating Conditions

Symbol Parameter min. nom. max. Unit Note

VLTGP Positive supply voltage / dc

portion 17.5 34 V 1

ILTG Supply current consumpt ion 6 m A 2

OA Ambient tem per at ure - 25 25 85 °C 3

FC Quartz f requency 5.3333

33 MHz 4

Sensitivity against m o ist ure 5

Notes:

1 False-poling protection diode t o be inser ted between pos. AS-interf ace bus line and

LTGP-pin. LTGP-pin to be pr ot ected furt her m or e with a voltage clam p bet ween

LTGP and LT G N.

2 Oscillator on; data transmission stage off; no loads connect ed

3 Power dissipation rest rictions as per fig . 1 to be observed

4 ASI Quarz

5 Level 5 acc. t o JEDEC- standard JESD22-A112, T able 1

0,5

50 100 t/ °C

Pv/ W 1

0,5

50 100 t/ °C

Pv/ W

SOIC20SOIC16

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 6 of 18

c) Supply pin LTGP

Positive supply pin connected to positive AS-interface bus line and clamped relat ive to neg .

supply pin / ground LT G N as descr ibed under Recom mended Operating Condit ions.

VLTGP and I LTG specified under Recommended Operating Conditions as well.

Symbol Parameter min. max. Unit Note

VSIG VPP of sin2-data-pulses

on top of dc supply voltage 38V

Z Input impedance

between 50 kHz and 300 kHz 40 pF CCDC = 100 nF

18 kOhm 1

50 mH 1

Note:

1 I nput equivalent circuit is parallel ar rangement of C, R and L

d) Buffer pin CDC

An external buffer capacitor with a recom m ended value of 100 nF should be connected to this

pin to ensure a sufficiently high input impedance Z at power supply pin LTGP.

Voltage at this pin can be as high as VLTG P.

e) Nom. 24V power supply output UOUT

The supply output voltage at UOUT is dir ectly derived from VLT G P and regulated to a level

with an offset of about - 6V relative to VLTG P.

UOUT pr ovides bias to t he sensor s and act uators circuitry connected to the slave device as

well as to the LEDs connected to outputs LED1 and LED2.

UOUT is equipped with a thermal overload protection, which f oresees that VUOUT is switched

off as soon as the slave device’s substrate temper at ur e TJ passes a threshold value in the

range of (155 -+ 20)°C.

Aft er TJ has come down and has passed a temperature t hr eshold about (15 -+ 5)°C lower

than (155 -+ 20) °C and after a consecutive minimum delay of 1 s has elapsed, VUOUT is

switched on again.

Symbol Parameter min. max. Unit Note

VUOUT Power supply output voltag e VLTGP -

6.3V VLTG P -

5.3V V

IUOUT Load current 50 mA 1

VCOMOFF UOUT voltage level 9.5 10.5 V

below which data tr ansmission

is inhibited

CUOUT Buffer capacitor 10 µF 2

Notes:

1 In case IUOUT > 40 mA and presence of sin2-data pulses on LTG P

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 7 of 18

with VSIG > 3V, VUOUT may drop as much as 1V below it's level

in unloaded condition

2 Electrolythic and rf filter capacitor in parallel

f) Nom. 5V power supply output U5R

The voltag e at U5R is der ived from the voltage present at UOUT, as long as UO UT is not

switched off due to overload. In the latter case U5R is derived from an alternative voltage out

of t he UOUT voltage regulator, which is more or less similar to VUOUT in non switched off

condition of UO UT. As a result VU5R is not affected by overload condit ion at UOUT and will

remain.

Symbol Parameter min. max. Unit

VU5R Power supply output voltage 4.85 5.15 V

IU5R Load current 1 mA

CU5R Buffer capacitor 100 nF

g) Oscillatorpins OSC1 and OSC2

The only component to be connect ed to these pins is a quartz crystal with a resonance fre-

quency of 5. 333333 MHz (AS-Inter face quart z crystal) .

Symbol Parameter min. max. Unit

CX2 Stray capacitance 10 pF

h) Data port pins D3, …, D0 and data strobe pin DSTBn

Basically data port D3, …, D0 is designed for bidir ectional data transfer out of and into the

slave device. Each data port pin is equipped with both a low-side open-drain output stage as

well as an input stage to t his pur pose.

Depending on the so called I O -configuration code, written into and st or ed in the slave device,

each data port pin is individually set to behave as

• output, or

• output / input, or

• input.

The timing of the data transfer is presented in fig . 2.

Strobe sig nal DSTBn flags and governs the data transfer as f ollows:

ha) data port pin is set ‘output’:

output data becom e valid upon the HL- edge of t he st r obe and will remain so until the next

HL-edge, hence dur ing the entire str obe cycle;

hb) data port pin is set ‘output / input’:

output data become valid upon the HL-edge of the strobe and will remain so until it’s LH-

edge; input data to be valid within a specific time window relative to the HL-edge, after

completion of t he strobe’s L-phase;

hc) data port pin is set ‘input’:

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 8 of 18

input data to be valid within a specific time window relative to the HL- edge of the st r obe,

aft er com plet ion of the strobe’s L- phase.

If necessar y, out put data as per ha) and hb) can be easily latched with the LH-edge of strobe

DSTBn as they will remain valid for about 0.4 µs beyond as a minimum.

Care must be t aken however, that signal delay added by external circuitr y is lower fo r t he

strobe than for the data.

Fig. 2: Timing of dat a transfer at data port D3, …, D0 r elative to strobe DSTBn

The following table specifies the t im ing parameters relat ing to fig. 2:

Symbol Parameter min. max. Unit Note

tSTB Delay DST Bn HL- edge to Dx

output data valid 1.5 µs

tDSTBn DSTBn strobe width 6 6.8 µs 1

tOUT OFF Delay DSTBn LH-edge to Dx

output off 0.2 1 µs 2

tINP Input data valid time window 10.5 12.5 µs 3

Notes:

1 Pulse width depends substant ially on value of exter nal pull- up r esistor

2 Applies only to dat a por t pins set to 'output / input' operation

3 Timing reference is DST Bn HL- edge.

Applies only to data port pins set t o eit her 'output / input' or 'input' operat ion

Data inData out

Data in

Data out

STB

DSTBn

+ 0.4 µs

DSTBn

+ t

OUTOFF

DSTBn

INPmin

INPmax

DSTBn

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 9 of 18

The dc-parameters of the data port pins D3, …, D0 ar e specified as follows:

Symbol Parameter min. max. Unit Note

IOUTL O Sink current @ out put L 10 mA VOUT =

IOUTHI Leakage current @ output off - 1 1 µA 1

VSCHLT Input th r eshold voltage 2.5 3.5 V 2

VIN Acceptable input voltag e @

output off - 0.3 40 V

Notes:

1 Output stag e is low-side open-dr ain; ext. pull-up resistor required as no pull-up

structur e on chip

2 No hysteresis im plem ented

To govern t he data transf er at data port D3, …,D0 st r obe pin DSTBn is equipped with a low-

side open-drain output switch plus a passive high-s ide cur r ent source with a nom. 10 µA pull-

up current capabilit y.

However a second function is assigned t o the DSTBn pin which requires it to be input as well:

if a low-pulse is imposed on DST Bn by external m eans with a pulse width of at least 50 to 100

ms, the slave device will be put in RESET condition, as descr ibed in section “Reset”.

The dc-and t iming parameters of strobe pin DST Bn ar e specified as follows:

Symbol Parameter min. max. Unit Note

IOUTLO Sink current @ output L 10 mA VOUT = 1V

IOUTHI Leakge current @ output off - 10 10 µA VOUT = 5V

IINLO I nput cur r ent @ VIN = 1V - 5 - 20 µA 1

VSCHLT Input th r eshold voltage 1.5 3.5 V 2

VIN Acceptable input voltag e @

output off - 0.3 40 V

tNORESET DSTBn L-phase width, not

triggering RESET 50 ms

tRESET DSTBn L- phase width, t rig-

gering RESET 100 ms

CPINEXT Stray capacitance 20 pF

Notes:

1 DSTBn is equipped with an on-chip pull-up current sour ce, which ensures

a sufficiently fast LH- edge upon output switch-of f in open-pin condition,

to prevent err oneous RESET triggering.

If DSTBn has an external load connected to it,

an additional external pull-up resistor may be needed

to prevent err oneous RESET triggering upon output switch-off

2 No hysteresis im plem ented

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 10 of 18

i) Parameter port pins P3, …, P0 and parameter strobe pin PSTBn

(Note that par am eter port pins P3, …, P0 ar e only available on AS2702 package option SOIC

20, not on the SO IC 16 option.)

The transfer of data at P3, …, P0 and the suppor t ing strobe action at pin PST Bn t akes place

similarly as at D3, …, D0 resp. DSTBn.

Each parameter por t pin P3, …, P0 is equipped with both a low-side open-drain out put switch

plus a passive, but switchable high-side cur r ent source with a nom . 10 µA pull- up current ca-

pability, and with an input stag e.

Though equipped for bidir ectional data transfer as D3, …, D0, the parameter por t is less flexi-

ble than the data por t.

Basically the parameter por t is set to behave portwise as

• output, or

• input

depending on the I O -configur ation code, written into and stor ed in the slave device.

The timing of the data transfer is presented in fig . 3.

Strobe sig nal PSTBn flags and governs the data transfer as f ollows:

ia) paramet er port is set ‘output’:

output data becom e valid upon the HL- edge of t he st r obe and will remain so until the

next HL-edge, hence dur ing the entire st r obe cycle;

ib) paramet er port is set ‘input’:

input data to be valid within a specif ic t im e window relative to the HL-edg e of the

strobe, after complet ion of the strobe’s L-phase.

Output data as per ia) could be easily latched with the LH-edg e of strobe PST Bn, if at all nec-

essary.

Fig. 3: Timing of dat a transfer at parameter por t P3, …, P0 relative to strobe PSTBn

Parameter out Parameter out

Data in

STB

PSTBn

INPmin

INPmax

PSTBn

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 11 of 18

The following table specifies the t im ing parameters relat ing to fig. 3:

Symbol Parameter min. max. Unit Note

tSTB Delay PST Bn HL- edge to Px

output data valid 1.5 µs

tPSTBn PSTBn strobe width 6 6.8 µs 1

tINP Input data valid time window 10.5 12.5 µs 2

Notes:

1 Pulse width depends substant ially on value of exter nal pull- up r esistor

2 Timing reference is PST Bn HL- edge.

Applies only to parameter por t set to 'input' operation

The dc-parameters of the parameter por t pins P3, …, P0 are specified as follows:

Symbol Parameter min. max. Unit Note

IOUTLO Sink current @ output L 10 mA VOUT = 1V

IOUTHI Leakage current @ output off - 10 10 µA VOUT = 5V

IOUTHI 7 Leakage current @ output off;

pull-up current sour ce off - 1 1 µA VOUT = 5V;

IO-conf. = 7

IINLO I nput cur r ent @ VIN = 1V - 5 - 20 µA 1

VSCHLT Input th r eshold voltage 2.5 3. 5 V 2

VIN Acceptable input voltag e @

output off - 0.3 40 V

Notes:

1 The passive high-side current-source provides an about constant input current @

0V <= VIN <= 4V

2 No hysteresis im plem ented

Though equipped for bidir ectional data transfer as D3, …, D0, the parameter por t is never-

theless less f lexible than the dat a port.

Note the following differences:

ik) The parameter por t is set portwise, the data port bit wise by the IO- configurat ion code;

il) The par am eter port can only be set to eit her ‘output’ or ‘input’. A bidirectional behaviour

within a strobe cycle is not possible;

im) The parameter port is set to ‘output’ as a rule; t he only exception occurs in case of IO-

configuration 7 and a master data request, which set it to ‘input’.

To govern t he dat a transfer at t he parameter port P3, …, P0 strobe pin PSTBn is equipped

with a low-side open- dr ain out put switch plus a passive high - side cur rent source with a nom.

10 µA pull-up current capability. Typically the PSTBn-strobe width is about 6 µs, see fig. 3.

( However to simplify and short en the component test t im e of the slave device, the PSTBn pin

is also used as an input. Input low pulses of m or e than 50 µs each will step and cycle the de-

vice through 3 different testmodes beyond the regular oper ation as described in this da-

tasheet.)

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 12 of 18

The dc- and t iming parameters of strobe pin PST Bn ar e specified as follows:

Symbol Parameter min. max. Unit Note

IOUTLO Sink current @ output L 10 mA VOUT = 1V

IOUTHI Leakage current @ output off - 10 10 µA VOUT = 5V

IINLO Input curr ent @ VIN = 1V - 5 - 20 µA 1

VSCHLT Input th r eshold voltage 1.5 3.5 V 2

VIN Acceptable input voltage @ out-

put of f - 0.3 40 V

tNOT M PSTBn L- phase width, not t rig-

gering testmode 35 µs

tTM PSTBn L-phase width, triggering

testmode 50 µs

CPINEXT Stray capacitance 20 pF

Notes:

1 PST Bn is equipped with an on-chip pull-up current sour ce, which ensures

a sufficiently fast LH- edge upon output switch-of f in open-pin condition, t o prevent

erroneous test m ode t riggering .

If PSTBn has an external load connected to it, an additional external pull-up resist or

may be needed to prevent erroneous t est m ode trigger ing upon output switch-of f

2 No hysteresis im plem ent ed

Operation status pins LED1 and LED2

Pins LED1 and LED2 are both eq uipped with a low-side open-drain output switch plus a pas-

sive high-side curr ent source with a nom . 10 µA pull-up current capabilit y. They will each have

an LED load connected to UOUT, which will flag the operat ion st at us of the slave device, ac-

cording t o the following table:

Output LED1 Output LED2 Flagging Priority Slave Device

Operation St at us Reason

(green LED

connected) (red LED con-

nected) (1 = highest , …,

4 = lowest)

off off Supply voltage off No supply voltage

on off Regular operation

off on 4 No Data

Communication Regular, non-zero

slave address coded;

data comm. watchdog

triggered

blinks on 3 No regular slave

address coded Slave address = de-

fault zero

blinks blinks

(alternating with

LED1)

2 Hardware f ailur e in

sensor / acuator

circuitry

Input PFAULT = L

off blinks 1 External RESET or

Overload at UOUT

DSTBn = L to RESET,

or UOUT switched-off

due to overload

(LED1 and LED2 both also feature an input stage, to simplify component test and short en test

time of the slave device.)

The dc- and t iming parameters of pins LED1 and LED2 are specif ied as follows:

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 13 of 18

Symbol Parameter min. max. Unit Note

ILED Sink current @ output L 10 mA VOUT = 1V

IOUTHI Leackag e cur r ent @ output off - 10 10 µA VOUT = 5V

VIN Accept able input voltage @ out-

put of f - 0.3 40 V

fBLI NK Blinking frequency 2 3 Hz

Data Communication Watchdog

AS2702 is equipped with a watchdog timer t o super vise data comm unication by monitoring

the strobe signals at pins DSTBn and PSTBn.

If a par am eter or data str obe is not followed by a consecutive str obe within a time per iod of

50 … 100 ms, the watchdog is trigger ed and initiates a ‘soft ’ reset, see section ‘Reset’

RESET

There are 2 categories of r eset-events, leading to 2 slightly different reset- conditions of the

slave device:

1) a ‘hard’ reset t aking place at power-up and power-down of supply-voltages U5R and

UOUT.

At power-up the slave device leaves reset-condition as soon as U5R has passed 3.75V

and UOUT has passed VCO MOFF = nom. 10V.

At power-down the slave device is forced into reset - condition as soon as U5R drops below

3.75V.

(Tolerance of the threshold voltages referr ed to is -/+ 5%.)

2) a ‘soft ’ re set , resulting from one of the following events:

2.1) Data st robe pin DSTBn is kept L for more than 100 ms;

2.2) Master comm and ‘RESET SLAVE’ is received;

2.3) Master command ‘RESET BROADCAST’ is received;

2.4) T he com m unicat ion watchdog is t riggered.

A ‘hard’ reset event condit ions t he slave device as follows:

• Internal states (counters, flags, …) are r eset

• The slave device’s receiver is desynchronized from the AS-interf ace bus

• The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are

switched off

• Any test-mode will be cancelled.

A ‘soft ’ reset has the following consequences:

• A regular , nom inal 6µs L-phase strobe is gener at ed on bot h the DSTBn and PSTBn pin

• The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are

switched off

• Internal st at es ( c ount er s, flags, …) ar e r eset , however the following states and operations

are not affected:

• the timer function which controls blinking of LED1 and LED2

• the data communication watchdog

• any testmode

• any EEPROM write operat ion.

Remark:

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 14 of 18

If UO UT drops below VCOMOFF = nom. 10V data communication with t he AS- int erface bus is

aborted by the receiver or t ransmitter of the slave device. As long as U5R does not drop be-

low 3.75V in this situation, no ‘har d’ reset takes place; however the data com m unicat ion

watchdog will be triggered (unless disabled) and a ‘soft’ reset will result.

EEPROM

AS2702 has a 16 x 8 Bits serial interface EEPROM on board to store t he slave unit’s address

and set-up data in a non- volatile fashion.

The EEPROM stores the following data:

EEPROM-

Address Data Relevant Nr.

of bits Programmed by Note

0, 1 Slave Address 5 + 1 Master ( I nitialization) 1

2 Settings (EID1) 4 Master (Initialization)

3 Set tings (IO- Conf.) 5 Slave unit manufacturer

4 Settings ( ID) 5 Slave unit manufacturer

5 Settings ( EI D2) 5 Slave unit manufacturer

6 Setting s (Control-

Code) 5 Slave unit manufact u r er

Note

1 6 Bits (A4, …, A0 + Sel- bit ) in extended addr ess m ode: 62 slaves addressable;

5 Bits (A4, …, A0) in non- extended addr ess m ode: 31 slaves addressable

Obviously the capacity of the EEPROM is only partially used.

Reading and writing of the EEPROM is perf ormed bytewise and trough temporary, volatile

registers.

Writ ing of data from t he volatile r egister into the EEPRO M takes about 10 ms per byte,

whereas reading tak es less than 1 ms per byte.

Upon RESET the EEPRO M inf o is r ead int o t em porary registers, including the slave’s address

which has been written redundantly into EEPROM locations 0 and 1 befor e.

The tem por ar y reg ist er s receiving the address are compar ed for similarity; in case of non-

similarity – which e.g. m ay have been caused by a supply voltage dip during address writing –

the slave will flag non-regular operation st at us / slave address zero.

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 15 of 18

AS-Interface Bus Communication

All slaves connected to an AS-interface bus are sequentially and cyclicly called by the master

in a string of individual transactions between the master and each slave unit.

A transaction consist s of a 14 bits mast er r equest, typically containing the slave’s address as

well as data or parameter info, and an immediate acknowledging slave response of 7 bits.

The 14 bits m aster request - apart from Start Bit ST = 0 and End Bit EB = 1 – has the f ollow-

ing content s:

• 1 Control Bit CB: CB = 0 stands for data transf er ( typ. data or parameter s)

CB = 1 identif ies com m and- type requests

• 5 Address Bits: A4, …, A0

• 5 Inf or m at ion Bit s: I4, …, I0 (t yp. data or parameters)

• 1 Parity Bit PB.

AS2702 allows for up to 62 slaves on the sam e AS- int er face bus; this r equires a slave ad-

dress extended to 6 bits, hence an extr a bit beyond A4, …, A0.

Inf or m ation bit I3 is used as the 6th address bit in t his so-called extended address mode. It is

called Sel-bit, as it is perceived as to select between A-slave (Sel = 0) and B-slave (Sel = 1) at

address location A4, …, A0.

In non-extended address mode AS2702 is addressed with A4, …, A0 only - for a max. tot al of

31 slaves per AS-interface bus system, and is system compatible with existing slave device

AS2701A.

The 7 bits slave response – apart from St ar t Bit ST = 0 and End Bit EB = 1 – has t he following

contents:

• 4 Inf or m at ion Bit s: I4, …, I0 (t yp. data or parameters)

• 1 Parity Bit PB.

Detailed descriptions of all types of mast er r equests and corresponding slave responses can

be found in AS- I nterface Specification V2.11, obt ainable from the AS-International Association

(D) or its local representative, see section “ Applicat ion Suppor t ”.

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 16 of 18

Application Example

Sensor/actuat or circuit supplied by the ASI Slave IC (UOUT ) for supply current needs

≤ 50 mA.

C1 = 100 nF / 35 V

C2 = 100 nF / 6 V

C3 = 10...470 µF / 30 V

C4 = 22...100 nF / 30 V

V1 = 1N4002 or equivalent

V2 = TGL 41- 39A or equivalent

G1 = AS-Interface Cr ystal 5. 333 MHz

AS-Interface Quartz 5.333 MHz

AS2702 works f ine with the following crystal types:

CitizenCM 309

Philips SQ 4849

AS-Inter face quartz crystals are available from:

Endrich GmbH Geyer electronic

Contact: Axel Gensler Contact: Jür gen Blank

Hauptstr. 56 Camer loher st r . 71

D-72202 Nagold D-80689 München

Tel.: +49- 7452- 6007- 31 Tel.: +49- 89- 546868- 13

Fax: +49-7452-6007-70 Fax: +49-89-546868-90

Email: a.gensler@endrich.com

ASI Line

ASI-P

LTGN

U5R

OSC1

OSC2

LED1

DSTBn

LTGP

CDC

UOUT

PFAULT

LED2

PSTBn

AS 2702

Sensor / Actuator Circuit

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 17 of 18

Kinseki Europe G mbH Rutronik Elektronische Bauelement e GmbH

Contact: Dir k Holstein Contact: Jür gen Tischhauser

Schirmer St r . 76 Industriest r asse 2

D-40211 Düsseldorf D-75228 Ispring en / Pforzheim

Tel.: +49- 211- 36815- 33 Tel.: +49- 7231- 801- 543

Fax: +49-211-36815-10 Fax: +49-7231-801-633

Email: dholstein@kinseki.de Email: juergen_tischhauser@r ut ronik.com

Application Support

For general information and docum ent ation on the AS-Inter face concept you may contact one

of t he following AS-Inter face Associations:

AS-International Association

Contact: Rolf Becker

Zum Taubeng arten 52

D-63571 Gelnhausen

Tel.: +49- 6051- 473212

Fax: +49-6051-473282

Email: as-int er face@t-online. de

AS-Interface Switzerland AS-Interface France

Contact: Rainer Schnaidt Contact: Gilles Mazet

Bittert enstraße 15 5 rue Nadar

CH-4702 Oensing en F-92566 Rueil Malmaison cedex

Tel.: +41- 62- 388- 2567 Tel.: +33-1-41-298294

Fax: +41-62-388-2525 Fax: +33-1-41-298482

Email: rainer.schnaidt@f ho.ch Em ail: gilles_mazet@mail. schneider.fr

AS-Interface It aly AS-I nterface The Nederlands

Contact: Maurizio Ghizzoni Contact: Andre Braakman

Via G.B. Bar inet t i, 1 Boerhaavelaan 40

I-20145 Milano NL-2700 AD Zoetermeer

Tel.: +39- 02- 66761 Tel.: +31- 79- 353- 1269

Fax: +39-02-6676-3491 Fax: +31-79-353- 1365

Email: maurizio.ghizzoni@siemens.it Email: ABA@FME.NL

AS-Int er face Great Britain AS-Int er face USA

Contact: Geoff Hodgkinson Contact: Michael Bryant

1 West St r eet 16101 N. 82nd Street, Suite 3B

GB-PO 14 4DH Titchfield, Hampshire USA-85260 Scott s dale, Arizona

Tel.: +44- 1329- 511882 Tel.: +1- 480- 368- 9091

Fax: +44-1329-512063 Fax: +1-480-483-7202

Email: asi_uk @gghcomms.demon.co.uk Email: mbryant@g oodnet.com

AS-Inte r face Belgium AS-Inte r face Sweden

Contact: Maurice de Smedt Contact: Lar s Mattsson

Avenue Paul Hymanslaan 47 Karl Nordströms väg 31

B-1200 Bruxelles-Brussel SE-43253 Varberg

Tel.: +32- 2- 771- 3912 Tel.: +46- 3406- 29270

Fax: +32-2-771-1264 Fax: +46-3406-77190

Email: m. desmedt@udias.be Email: lar s - m attsson@mark nadspartnermol.se

AS-Interface Slave IC

AS2702 (SAP4.1)

Rev. C, January 2001 Page 18 of 18

Bibliography

ASI: T he Act uator-Sensor-Int erface f or Automation

Edts.: Werner Kriesel, Otto W. Madelung

Carl Hanser Verlag , Munich and Vienna, 1995

ISBN: 3-446- 18265-9

Ordering Information

AS2702-20T Packag e: SOIC 20; delivery: tape & reel

AS2702-16T Packag e: SOIC 16 W; delivery: tape & r eel; no parameter por t available

AS2702-20 Package: SOIC 20; delivery: tubes

AS2702-16 Package: SOIC 16 W; delivery: tubes; no par ameter port available

Tel. +43-(0)3136-500-0, Fax +43-(0)3136-52501, E-Mail info@amsint .com

any means , without the prior perm i ssion in writing by the copyright holder. To t he best of its knowledge, Austri a Mikro Systeme

Internati onal asserts t hat the information contained i n this public at i on i s accurate and c o rrect.