te n ta rib ut io fS on TLE6368-G2 Di c_ oc Do _C st Multi-Voltage Processor Power Supply D Data Sheet Rev. 2.3, May 2009 Automotive Power Multi-Voltage Processor Power Supply 1 Overview 1.1 * * * * * * * * * * * * * * * * * TLE6368-G2 Features High efficiency regulator system Wide input voltage range from 5.5V to 60V Stand-by mode with low current consumption Suitable for standard 12V/24V and 42V PowerNets Step down converter as pre-regulator: 5.5V / 1.5A Step down slope control for lowest EME Switching loss minimization Three high current linear post-regulators with selectable output voltages: 5V / 800mA 3.3V or 2.6V / 500mA 3.3V or 2.6V / 350mA Six independent voltage trackers (followers): 5V / 17mA each Stand-by regulator with 1mA current capability Three independent undervoltage detection circuits (e.g. reset, early warning) for each linear post-regulator Power on reset functionality Tracker control and diagnosis by SPI All outputs protected against short-circuit Power PG-DSO-36-26 package Green (RoHS compliant) version of TLE6368-G2 AEC qualified PG-DSO-36-26 Type Package TLE6368-G2 / SONIC PG-DSO-36-26 (RoHS compliant) SMD = Surface Mounted Device Data Sheet 2 Rev. 2.3, 2009-05-04 TLE6368-G2 1.2 Short functional description The TLE6368-G2 is a multi voltage power supply system especially designed for automotive applications using a standard 12V / 24V battery as well as the new 42V powernet. The device is intended to supply 32 bit micro-controller systems which require different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external sensors are also provided. The TLE6368-G2 cascades a Buck converter block with a linear regulator and tracker block on a single chip to achieve lowest power dissipation thus being able to power the application even at very high ambient temperatures. The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum current capability of 1.5A. Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V, or 2.6V of output voltages depending on the configuration of the device with current capabilities of 800mA, 500mA and 350mA. In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to drive a current of 17mA each. The trackers can be turned on and off individually by a 16 bit serial peripheral interface (SPI). Through this interface also the status information of each tracker (i.e. short circuit) can be read out. To monitor the output voltage levels of each of the linear regulators three independent undervoltage detection circuits are available which can be used to implement the reset or an early warning function. The supervision of the C can be managed by the SPItriggered window watchdog. For energy saving reasons while the motor is turned off, the TLE6368-G2 offers a standby mode, where the quiescent current does not exceed 30A. In this stand-by mode just the stand-by regulator remains active. The TLE6368-G2 is based on Infineon Power technology SPT which allows bipolar, CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry. Data Sheet 3 Rev. 2.3, 2009-05-04 TLE6368-G2 1.3 Pin configuration PG-DSO-36- GND 1 36 GND C LK 2 35 SLEW CS 3 34 W AKE DI 4 33 BOOST DO 5 32 IN ERR 6 31 SW Q_STB 7 30 IN Q _T1 8 29 SW Q _T2 9 28 B o o tstra p Q _T3 10 27 Q _LD O 1 Q _T4 11 26 F B /L _ IN Q _T5 12 25 F B /L _ IN Q _T6 13 24 Q _LD O 2 Q _LDO 3 14 23 SEL R3 15 22 CCP R2 16 21 C+ R1 17 20 C- GND 18 19 GND TLE 6368 Figure 1 Pin Configuration (Top View), bottom heat slug and GND corner pins are connected Data Sheet 4 Rev. 2.3, 2009-05-04 TLE6368-G2 1.4 Pin definitions and functions Pin No. Symbol Function 1,18,19, 36 GND Ground; to reduce thermal resistance place cooling areas on PCB close to these pins. The GND pins are connected internally to the heat slug at the bottom. 2 CLK SPI Interface Clock input; clocks the shift register; CLK has an internal active pull down and requires CMOS logic level inputs; see also chapter SPI 3 CS SPI Interface chip select input; CS is an active low input; serial communication is enabled by pulling the CS terminal low; CS input should only be switched when CLK is low; CS has an internal active pull up and requires CMOS logic level inputs; see also chapter SPI. 4 DI SPI Interface Data input; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first; the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see also chapter SPI 5 DO SPI Interface Data output; this tristate output transfers diagnosis data to the controlling device; the output will remain 3stated unless the device is selected by a low on Chip-Select CS; see also the chapter SPI 6 ERR Error output; push-pull output. Monitors failures in parallel to the SPI diagnosis word, reset via SPI. ERR is an active low, latched output. 7 Q_STB Standby Regulator Output; the output is active even when the buck regulator and all other circuitry is in off mode 8 Q_T1 Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. 9 Q_T2 Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. 10 Q_T3 Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Data Sheet 5 Rev. 2.3, 2009-05-04 TLE6368-G2 1.4 Pin definitions and functions (cont'd) Pin No. Symbol Function 11 Q_T4 Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. 12 Q_T5 Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. 13 Q_T6 Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. 14 Q_LDO3 Voltage Regulator Output 3; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 2.2.2); For stability a ceramic capacitor of 470nF to GND is sufficient. 15 R3 Reset output 3, undervoltage detection for output Q_LDO3; open drain output; an external pull-up resistor of 10k is required 16 R2 Reset output 2, undervoltage detection for output Q_LDO2; open drain output; an external pull-up resistor of 10k is required 17 R1 Reset output 1, undervoltage detection for output Q_LDO1 and watchdog failure reset; open drain output; an external pull-up resistor of 10k is required 20 C- Charge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and C- 21 C+ Charge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and C- 22 CCP Charge Pump Storage Capacitor Output; Add the storage capacitor of 220nF between pin CCP and GND. 23 SEL Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3 (see also 2.2.2) 24 Q_LDO2 Voltage Regulator Output 2; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 2.2.2); For stability a ceramic capacitor of 470nF to GND is sufficient. 25, 26 FB/L_IN Feedback and Linear Regulator Input; input connection for the Buck converter output Data Sheet 6 Rev. 2.3, 2009-05-04 TLE6368-G2 1.4 Pin definitions and functions (cont'd) Pin No. Symbol Function 27 Q_LDO1 Voltage Regulator Output 1; 5V output; acts as the reference for the voltage trackers.The SPI and window watchdog logic is supplied from this voltage. For stability a ceramic capacitor of 470nF to GND is sufficient. 28 Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW and pin Bootstrap, the capacitance value should be 2% of the Buck converter output capacitance 29, 31 SW Switch Output; connect both pins externally through short lines directly to the cathode of the catch diode and the Buck circuit inductance. 30, 32 IN Supply Voltage Input; connect both pins externally through short lines to the input filter/the input capacitors. 33 BOOST Boost Input; for switching loss minimization connect a diode (cathode directly to boost pin) in series with a 100nF ceramic capacitor to the IN pin and from the anode of the diode to the buck converter output a 22 resistor. Recommended for 42V applications. In 12/24V applications connect boost directly to IN. 34 WAKE Wake Up Input; a positive voltage applied to this pin turns on the device 35 SLEW Slew control Input; a resistor to GND defines the current slope in the buck switch for reduced EME Data Sheet 7 Rev. 2.3, 2009-05-04 TLE6368-G2 1.5 Basic block diagram TLE 6368 Q_STB Standby Regulator Boost SW 2* IN 2* BUCK REGULATOR Slew Bootstrap Driver OSZ ErrorAmplifier PWM Internal Reference feedback FB/L_IN 2* C+ Charge Pump CCP Protection Wake C- Power Down Logic SEL R1 R2 Reset Logic R3 ref Window Watchdog ref CLK ref CS ref SPI 16 bit DI ref DO ref ERR Linear Reg. 1 Q_LDO1 Linear Reg. 2 Q_LDO2 Linear Reg. 3 Q_LDO3 Tracker 5V Q_T1 Tracker 5V Q_T2 Tracker 5V Q_T3 Tracker 5V Q_T4 Tracker 5V Q_T5 Tracker 5V Q_T6 -controller / memory supply Sensor supplies (off board supplies) GND 4* Figure 2 Block Diagram Data Sheet 8 Rev. 2.3, 2009-05-04 TLE6368-G2 2 Detailed circuit description In the following major buck regulator blocks, the linear voltage regulators and trackers, the undervoltage reset function, the watchdog and the SPI are described in more detail. For applications information e.g. choice of external components, please refer to section 5. 2.1 Buck Regulator The diagram below shows the internal implemented circuit of the Buck converter, i. e. the internal DMOS devices, the regulation loop and the other major blocks. IN 5V Int. voltage regulator Int. charge pump 14V 150A to current sense amplifier 8 to 10V FB/L_IN C+ CCP Gate driver Main switch ON/OFF Main DMOS IN undervoltage lockout CSW BOOTSTRAP Slope switch charge signal switching frequency 330kHz Divider BOOST Slope DMOS Oscillator 1.4MHz Slope switch discharge signal Slope compensation Gate off signal from overtemp or sleep command Lowpass Voltage feedback amplifier Current comparator Vref=6V SW Trigger for gate on PWM logic Slope logic Zero cross detection Trigger for gate off Lowpass from current sensing Current sense amplifier Delay unit + Slope control SLEW external components pins Figure 3 Detailed Buck regulator diagram The 1.5A Buck regulator consists of two internal DMOS power stages including a current mode regulation scheme to avoid external compensation components plus additional blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how Data Sheet 9 Rev. 2.3, 2009-05-04 TLE6368-G2 the gate driver supply is managed by the combination of internal charge pump, external charge pump and bootstrap capacitor. 2.1.1 Current mode control scheme The regulation loop is located at the left lower corner in the schematic, there you find the voltage feedback amplifier which gives the actual information of the actual output voltage level and the current sense amplifier for the load current information to form finally the regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the slope compensation block is necessary. The control signal formed out of those three blocks is finally the input of the PWM regulator for the DMOS gate turn off command, which means this signal determines the duty cycle. The gate turn on signal is set by the oscillator periodically every 3s which leads to a Buck converter switching frequency around 330kHz. With decreasing input voltage the device changes to the so called pulse skipping mode which means basically that some of the oscillator gate turn off signals are ignored. When the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin the device is turned off.During normal switching operation the gate driver is supplied by the bootstrap capacitor. 2.1.2 Start-up procedure To guarantee a device startup even under full load condition at the linear regulator outputs a special start up procedure is implemented. At first the bootstrap capacitor is charged by the internal charge pump. Afterwards the output capacitor is charged where the driver supply in that case is maintained only by the bootstrap capacitor. Once the output capacitor of the buck converter is charged the external charge pump is activated being able to supply the linear regulators and finally the linear regulators are released to supply the loads. 2.1.3 Reduction of electromagnetic emission In figure 3 it is recognized that two internal DMOS switches are used, a main switch and an auxiliary switch. The second implemented switch is used to adjust the current slope of the switching current. The slope adjustment is done by a controlled charge and discharge of the gate of this DMOS. By choosing the external resistor on the SLEW pin appropriate the current transition time can be adjusted between 20ns and 100ns. 2.1.4 Reducing the switching losses The second purpose of the slope DMOS is to minimise the switching losses. Once being in freewheeling mode of the buck regulator the output voltage level is sufficient to force the load current to flow, the input voltage level is not needed in the first moment. By a feedback network consisting of a resistor and a diode to the boost pin (connection see Data Sheet 10 Rev. 2.3, 2009-05-04 TLE6368-G2 section 5) the output voltage level is present at the drain of the switch. As soon as the voltage at the SW pin passes zero volts the handover to the main switch occurs and the traditional switching behaviour of the Buck switch can be observed. 2.2 Linear Voltage Regulators The Linear regulators offer, depending on the version, voltage rails of 5V, 3.3V and 2.6V which can be determined by a hardware connection (see table at 2.2.2) for proper power up procedure. Being supplied by the output of the Buck pre-regulator the power loss within the three linear regulators is minimized. All voltage regulators are short circuit protected which means that each regulator provides a maximum current according to its current limit when shorted. Together with the external charge pump the NPN pass elements of the regulators allow low dropout voltage operation. By using this structure the linear regulators work stable even with a minimum of 470nF ceramic capacitors at their output. Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable output voltage of 3.3V or 2.6V and Q_LDO3 is also programmable to 3.3V or 2.6V (see section 2.2.2). All three regulators are on all the time, if one regulator is not needed a base load resistor in parallel to the output capacitance for controlled power down is recommended. 2.2.1 Startup Sequence Linear Regulators When acting as a 32 bit C supply the so-called power sequencing (the dependency of the different voltage rails to each other) is important. Within the TLE6368-G2, the following Startup-Sequence is defined (see also figure 4): VQ_LDO2 VQ_LDO1; VQ_LDO3 VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V or 3.3V and VQ_LDO3 = 2.6V or 3.3V The power sequencing refers to the regulator itself, externally voltages applied at Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower than those outputs. That means for the power down sequencing if different output capacitors and different loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this behaviour three Schottky diodes have to be connected between the three outputs of the linear regulators in that way that the cathodes of the diodes are always connected to the higher nominal rail. Data Sheet 11 Rev. 2.3, 2009-05-04 TLE6368-G2 Power Sequencing VFB/L_IN VLDO_EN t VQ_LDO1 5V VRth5 3.3V 2.6V t VQ_LDO2 (2.6V Mode) 0.7V 2.6V VRth2.6 5V LDO 5V LDO 0.7V t VQ_LDO3 (3.3V Mode) 5V LDO 3.3V VRth3.3 5V LDO +/- 50mV +/- 50mV t Figure 4 Power-up and -down sequencing of the regulators 2.2.2 Q_LDO2 and Q_LDO3 output voltage selection* To determine the output voltage levels of the three linear regulators, the selection pin (SEL, pin 23) has to be connected according to the matrix given in the table below. Definition of Output voltage Q_LDO2 and Q_LDO3 Select Pin SEL connected to Q_LDO2 Q_LDO3 output voltage output voltage GND 3.3 V 3.3 V Q_LDO1 2.6 V 2.6 V Q_LDO2 2.6 V 3.3 V * for different output voltages please refer to the multi voltage supply TLE6361 Data Sheet 12 Rev. 2.3, 2009-05-04 TLE6368-G2 2.3 Voltage Trackers For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output current capability each are available. The output voltages match Q_LDO1 within +5 / -15mV. They can be individually turned on and off by the appropriate SPI command word sent by the microcontroller. A ceramic capacitor with the value of 1F at the output of each tracker is sufficient for stable operation without oscillation. The tracker outputs can be connected in parallel to obtain a higher output current capability, no matter if only two or up to all six trackers are tied together. For uniformly distributed current density in each tracker internal balance resistors at each output are foreseen internally. By connecting two sets of three trackers in parallel two sensors with more than 50mA each can be supplied, all six in parallel give more than 100mA. The tracker outputs can withstand short circuits to GND or battery in a range from -4 to +40V. A short circuit to GND is detected and indicated individually for each tracker in the SPI status word. Also an open load condition might be recognized and indicated as a failure condition in the SPI status word. A minimum load current of 2mA is required to avoid open load failure indication. In case of connecting several trackers to a common branch balancing currents can prevent proper operation of the failure indication. 2.4 Standby Regulator The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output current which is on all the time. It is intended to supply the microcontroller in stop mode and requires then only a minimum of quiescent current (<30A) to extend the battery lifetime. 2.5 Charge Pump The 1.6 MHz charge pump with the two external capacitors will serve to supply the base of the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the Buck DMOS transistor in 100% duty cycle operation at low battery condition. The charge pump voltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended to be used as a supply for additional circuitry. 2.6 Power On Reset A power on reset is available for each linear voltage regulator output. The reset output lines R1, R2 and R3 are active (low) during start up and turn inactive with a reset delay time after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. The reset outputs are open drain, three pull up resistors of 10k each have to be connected to the I/O rail (e.g. Q_LDO1) of the C. All three reset outputs can be linked in parallel to obtain a wired-OR. The reset delay time is 8 ms by default and can be set to higher values as 16 ms, 32 ms or 64 ms by SPI command. At each power up of the device in case the output voltage at Data Sheet 13 Rev. 2.3, 2009-05-04 TLE6368-G2 Q_LDO1 had decreased below 3.3V (max.), the SPI will reset to the default settings including the 8ms delay time. If the voltage on Q_LDO1 during sleep or power off mode was kept above 3.3V the delay time set by the last SPI command is valid. VFB/L_IN VRx t < trr VQ_LDOx VRTH,Q_LDOx t trr tRES tRES tRES tRES t thermal shutdown under voltage over load Figure 5 Undervoltage reset timing 2.7 RAM good flag A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM good flags can be read after power up to determine if a cold or warm start needs to be processed. Both RAM good flags will be reset after each SPI cycle. 2.8 ERR Pin A hardware error pin indicates any fault conditions on the chip. It should be connected to an interrupt input of the microcontroller. A low signal indicates an error condition. The microcontroller can read the root cause of the error by reading the SPI register. 2.9 Window Watchdog The on board window watchdog for supervision of the C works in combination with the SPI. The window watchdog logic is turned off per default and can be activated by one special bit combination in the SPI command word. When operating, the window watchdog is triggered when CS is low and Bit WD-Trig in the SPI command word is set to "1". The watchdog trigger is recognized with the low to high transition of the CS signal. To allow reading the SPI at any time without getting a reset due to misinterpretation the WD-Trig bit has to be set to "0" to avoid false trigger conditions. Data Sheet 14 Rev. 2.3, 2009-05-04 TLE6368-G2 definition tSR = tOW /2 tWDR = tRES tCW =tCW tOW =tCW (not the same scale) (not the same scale) closed window open window reset delay time without trigger reset start delay time after window watchdog timeout definition t EOW = end of open window t ECW Example with: tCW =128ms =25% (oscillator deviation) fOSC =f OSCmax t EOW, w.c.= ( t CW+tOW )(1-) worst cases f OSC=f OSCmin reset duration time after window watchdog time-out tECW, w.c. = 128(1.25) = 160ms t ECW, w.c.= tCW (1+) tEOW, w.c = (128+128)(0.75) = 192ms towmin t OWmin = 32ms Minimum open window time: t OWmin= t OW - * ( t OW + 2* t CW ) Figure 6 Window watchdog timing definition Figure 6 shows some guidelines for designing the watchdog trigger timing taking the oscillator deviation of different devices into account. Of importance (w.c.) is the maximum of the closed window and the minimum of the open window in which the trigger has to occur. The length of the OW and CW can be modified by SPI command. If a change of the window length is desired during the Watchdog function is operating please send the SPI command with the new timing with a "Watchdog trigger Bit" D15=1. In this case the next CW will directly start with the new length. A minimum time gap of > 1/48 of the actual OW/CW time between a "Watchdog disable" and 'Watchdog enable' SPI-command should be maintained. This allows the internal Watchdog counters to be resetted. Thus after the enable command the Watchdog will start properly with a full CW of the adjusted length. Data Sheet 15 Rev. 2.3, 2009-05-04 TLE6368-G2 P e rfe c t trig g e rin g a fte r P o w e r o n R e s e t V Q _LD O 1 V R th 1 1V t tR ES R1 t tC W W a tc h d o g w in d o w CW tSR OW CW OW CW CW OW t CS 1) 2) 2) 2) t ERR t In c o rre c t trig g e rin g W a tc h d o g w in d o w CW OW 3) 4) t CS w ith W D trig = 1 1) 2) 3) 4) t W a tc h d o g e n a b le c o m m a n d w ith n o trig g e r: D 0 D 9 D 1 4 D 1 5 = 0 1 0 0 W a tc h d o g trig g e r: D 1 5 = 1 P re trig g e r M is s in g trig g e r Legend: O W = O p e n w in d o w C W = C lo s e d w in d o w Figure 7 Window watchdog timing Figure 7 gives some timing information about the window watchdog. Looking at the upper signals the perfect triggering of the watchdog is shown. When the 5V linear regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before Data Sheet 16 Rev. 2.3, 2009-05-04 TLE6368-G2 the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect on the reset line and/or error pin is observed. With the missing watchdog trigger signal the error signal turns low immediately where the reset is asserted after another delay of half the closed window time. Also shown in the figure are two typical failure modes, one pretrigger and one missing signal. In both cases the error signal will go low immediately the failure is detected with the reset following after the half closed window time. 2.10 Overtemperature Protection At a chip temperature of more than 150 an error and temperature flag is set and can be read through the SPI. The device is switched off if the device reaches the overtemperature threshold of 170C. The overtemperature shutdown has a hysteresis to avoid thermal pumping. 2.11 Power Down Mode The TLE6368-G2 is started by a static high signal at the wake input or a high pulse with a minimum of 50s duration at the Wake input (pin 34). Voltages in the range between the turn on and turn off thresholds for a few 100s must be avoided! By SPI command ("Sleep"-bit, D8, equals zero) all voltage regulators including the switching regulator except the standby regulator can be turned off completely only if the wake input is low. In the case the Wake input is permanently connected to battery the device cannot be turned off by SPI command, it will always turn on again. For stable "on" operation of the device the "Sleep"-bit, D8 has to be set to high at each SPI cycle! When powering the device again after power down the status of the SPI controlled devices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Did the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section) is set otherwise the last SPI command defines the status. 2.12 Serial Peripheral Interface A standard 16 bit SPI is available for control and diagnostics. It is capable to operate in a daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI interface. The 16-bit control word (write bit assignment, see Figure 8) is read in via the data input DI, synchronous to the clock input CLK supplied by the C beginning with the LSB D0. The diagnosis word appears in the same way synchronously at the data output DO (read bit assignment, see figure 9), so with the first bit shifted on the DI line the first bit appears on the DO line. The transmission cycle begins when the TLE6368-G2 is selected by the "not chip select" input CS (H to L). After the CS input returns from L to H, the word that has been read in Data Sheet 17 Rev. 2.3, 2009-05-04 TLE6368-G2 at the DI line becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to Figures 10 to 13. The SPI will be reset to default values given in the following table "write bit meaning" if the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V). The reset will be active as long as the power on reset is present so during the reset delay time at power up no SPI commands are accepted. The register content of the SPI - including watchdog timings and reset delay timings - is maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not decrease below 3.3V). 2.12.1 Write mode The following tables show the bit assignment to the different control functions, how to change settings with the right bit combination and also the default status at power up. 2.12.2 Write mode bit assignment BIT Name Default DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D 15 WD_ OFF1 NOT assigned T1control T2control T6control T4control T5control T6control sleep WD_ OFF2 reset 1 reset 2 WD1 WD2 WD_ OFF3 WD_ TRIG 1 X 1 1 1 1 1 1 1 0 1 1 0 0 1 0 Figure 8 Write Bit assignment Write Bit meaning Function Bit Combination Default Not assigned D1 X X Tracker 1 to 6 - control: turn on/off the individual trackers D2 D3 D4 D5 D6 D7 0: OFF 1: ON 1 Power down: send device to sleep D8 0: SLEEP 1: NORMAL 1 Data Sheet 18 Rev. 2.3, 2009-05-04 TLE6368-G2 Write Bit meaning Function Bit Combination Default Reset timing: Reset delay time tRES valid at warm start D10D11 00: 64ms 10: 32ms 01: 16ms 11: 8ms 11 Window watchdog timing: Open window time tOW and closed window time tCW valid at warm start D12D13 00: 128ms 10: 64ms 01: 32ms 11: 16ms 00 Window watchdog function: Enable /disable window watchdog D0D9D14 010: ON 1xx: OFF x0x: OFF xx1: OFF 101 Window watchdog trigger: Enable / disable window watchdog trigger D15 0: not triggered 0 1: triggered 2.12.3 Read mode Below the status information word and the bit assignments for diagnosis are shown. 2.12.3.1 Read mode bit assignment BIT Name Default DO D1 D2 D3 D4 D5 D6 D7 D8 D9 ERROR temp_ warn T1status T2status T3status T4status T5status T6status RAM Good 1 RAM Good 2 0 0 1 1 1 1 1 1 0 0 D10 D11 D12 D13 WD R-Error1 R-Error2 R-Error3 Window 0 0 0 0 D14 D 15 WD Error DC/DC status 0 1 Figure 9 Read Bit assignment Error bit D0: The error output ERR is low and the error bit indicates fail function if the temperature prewarning or the watchdog error is active, further if one RAM good indicates a cold start or if a voltage tracker does not settle within 1ms when it is turned on. Data Sheet 19 Rev. 2.3, 2009-05-04 TLE6368-G2 Read Bit meaning Function Type Bit Combination D0 0: normal operation 0 1: fail function Not latched D1 0: normal operation 0 1: prewarning Not latched D2 D3 D4 D5 D6 D7 1 1: settled output voltage 0:Tracker turned off or shorted output. Also open load may possibly be indicated as 0.1) Indication of cold start/ warm start, Q_LDO1 Latched D8 0: cold start 1: warm start 0 Indication of cold start/ warm start, Q_LDO2 Latched D9 0: cold start 1: warm start 0 Indication for open or closed window Not latched D10 0: open window 1: closed window 0 Reset condition at output Q_LDO1 Not latched D11 0: normal operation 0 1: Reset R1 Reset condition at output Q_LDO2 Not latched D12 0: normal operation 0 1: Reset R2 Reset condition at output Q_LDO3 Not latched D13 0: normal operation 0 1: Reset R3 Watchdog Error Latched DC/DC converter status Not latched D15 Error indication, Latched explanation see below this table Overtemperature warning Status of Tracker Output Q_T[1:6],only if output is ON 1) D14 Default 0: normal operation 1: WD error 0: off 1: on 0 1 Min. load current to avoid '0' signal caused by open load is 2mA. Data Sheet 20 Rev. 2.3, 2009-05-04 TLE6368-G2 2.12.4 SPI Timings CS High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register CS CS Low to High: Data from Register are transferred to e.g. Trackers CLK 0 1 2 3 13 14 15 Data In (N) DI D0 D1 D2 D13 D14 D15 D3 time 0 1 Data In (N+1) D0 + D1 + DI: Data will be accepted on the falling edge of CLK-Signal Data Out (N-1) DO D0 D1 D2 D3 D13 D14 D15 Data Out (N) D0 D1 DO: State will change on the rising edge of CLK-Signal e.g. Trackercontrol Setting (N) Setting (N-1) e.g. Trackerstatus Status (N) Status (N-1) Figure 10 SPI Data Transfer Timing Data Sheet 21 Rev. 2.3, 2009-05-04 TLE6368-G2 Figure 11 SPI-Input Timing WU,1 WI,1QV 94B/'2 &/. 94B/'2 WU'2 '2 ORZWRKLJK W9$'2 WI'2 '2 KLJKWRORZ Figure 12 DO Valid Data Delay Time and Valid Time Data Sheet 22 Rev. 2.3, 2009-05-04 TLE6368-G2 tfIN trIN <10ns 0.7 VQ_LDO1 CS 50% 0.2 VQ_LDO1 10k 50% Pullup to VQ_LDO1 DO tENDO tDISDO 10k Pulldown 50% to GND DO Figure 13 DO Enable and Disable Time Data Sheet 23 Rev. 2.3, 2009-05-04 TLE6368-G2 3 Characteristics 3.1 Absolute Maximum Ratings Item Parameter Symbol Limit Values Min. Max. Unit Test Condition 3.1.1 Supply Voltage Input IN Voltage VIN -0.5 60 V - Voltage VIN -1.0 60 V Tj = -40 C Current IIN - - - 3.1.2 Buck-Switch Output SW Voltage VSW -2 VS+0.5 V Current ISW - - - - 3.1.3 Feedback and Linear Voltage Regulator Input Voltage VFB/L_IN -0.5 8 V Current IFB/L_IN - - - - 3.1.4 Bootstrap Connector Bootstrap Voltage VBootstrap VSW0.5V VSW+ 10V V Voltage VBootstrap -0.5 70 V Current IBootstrap - - - Internally limited Voltage VBoost -0.5 60 V - Current IBoost - - - Internally limited 3.1.5 Boost Input 3.1.6 Slope Control Input Slew Voltage VSlew -0.5 6 V - Current ISlew - - - Internally limited 3.1.7 Charge Pump Capacitor Connector CVoltage VCL -0.5 VFB/L_IN +0.5 V Current ICL -150 +150 mA Data Sheet 24 Rev. 2.3, 2009-05-04 TLE6368-G2 3.1.8 Charge Pump Capacitor Connector C+ Voltage VCH -0.5 13 V Current ICH -150 +150 mA 3.1.9 Charge Pump Storage Capacitor CCP Voltage VCCP -0.5 12 V Current ICCP -150 - mA 3.1.10 Standby Voltage Regulator output Q_STB Voltage VQ_Stb -0.5 6 V - Current IQ_Stb - - - Internally limited 3.1.11 Voltage Regulator output voltage Q_LDO1 Voltage VQ_LDO1 -0.5 6 V - Current IQ_LDO1 - - - Internally limited 3.1.12 Voltage Regulator output voltage Q_LDO2 Voltage VQ_LDO2 -0.5 6 V - Current IQ_LDO2 - - - Internally limited 3.1.13 Voltage Regulator output voltage Q_LDO3 Voltage VQ_LDO3 -0.5 6 V - Current IQ_LDO3 - - - Internally limited 3.1.14 Voltage Tracker output voltage Q_T1 Voltage VQ_T1 -4 40 V - Current IQ_T1 - - mA Internally limited 3.1.15 Voltage Tracker output voltage Q_T2 Voltage VQ_T2 -4 40 V - Current IQ_T2 - - mA Internally limited 3.1.16 Voltage Tracker output voltage Q_T3 Voltage VQ_T3 -4 40 V - Current IQ_T3 - - mA Internally limited 3.1.17 Voltage Tracker output voltage Q_T4 Voltage VQ_T4 -4 40 V - Current IQ_T4 - - mA Internally limited Data Sheet 25 Rev. 2.3, 2009-05-04 TLE6368-G2 3.1.18 Voltage Tracker output voltage Q_T5 Voltage VQ_T5 -4 40 V - Current IQ_T5 - - mA Internally limited 3.1.19 Voltage Tracker output voltage Q_T6 Voltage VQ_T6 -4 40 V - Current IQ_T6 - - mA Internally limited 3.1.20 Select Input SEL Voltage VSEL -0.5 6 V - Current ISEL - - - Internally limited - 3.1.21 Wake Up Input Wake Voltage VWake -0.5 60 V Current IWake - - - 3.1.22 Reset Output R1 Voltage VR1 -0.5 6 V Current IR1 - - - - 3.1.23 Reset Output R2 Voltage VR2 -0.5 6 V Current IR2 - - - - 3.1.24 Reset Output R3 Voltage VR3 -0.5 6 V Current IR3 - - - - 3.1.25 SPI Data Input DI Voltage VDI -0.5 6 V Current IDI - - - - 3.1.26 SPI Data Output DO Voltage VDO -0.5 6 V - Current IDO - - - Internally limited - 3.1.27 SPI Clock Input CLK Voltage VCLK -0.5 6 V Current ICLK - - - Data Sheet 26 Rev. 2.3, 2009-05-04 TLE6368-G2 3.1.28 SPI Chip Select Not Input CS Voltage VCS -0.5 6 V Current ICS - - - - 3.1.29 Error Output Pin Voltage VERR -0.5 6 V - Current IERR - - - Internally limited 3.1.30 Thermal Resistance Junctionambient Rthja 37 K/W 1) Junctionambient Rthja 29 K/W 1) Junctioncase Rthjc - 2 K/W Junction temperature Tj -40 150 C Junction temperature transient Tjt 175 C Storage temperature Tstg -50 150 C VESD -1 1 kV PCB heat sink area 300mm2 PCB heat sink area 600mm2 3.1.31 Temperature lifetime=TBD 3.1.32 ESD ESD HBM-Model 1) Package mounted on FR4 47x50x1.5mm3; 70 Cu, zero airflow Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Data Sheet 27 Rev. 2.3, 2009-05-04 TLE6368-G2 3.2 Functional Range -40C < Tj < 150 C Item Parameter Symbol Limit Values min. Supply Voltage VIN, min Supply Voltage VIN, max Ripple at FB/L_IN VFB/L_IN Condition V VIN increased from 0V; VWAKE =5V; IQ_LDO1=400mA; IQ_LDO2=200mA max. 5.5 0 Unit 60 V 150 mVPP ripple Note: Within the functional range the IC can be operated. The electrical characteristics, however, are not guaranteed over this full functional range. Data Sheet 28 Rev. 2.3, 2009-05-04 TLE6368-G2 3.3 Recommended Operation Range -40C < Tj < 150 C Item Parameter Symbol Limit Values min. 1) typ. Unit Condition H 1) ESR <0.15 , ceramic capacitor (X7R) recommended1) max. Buck Inductor LB 18 Buck Capacitor CB 10 F Bootstrap Capacitor CBTP 2 % of CB SLEW resistor RSLEW 0 Linear regulator capacitors CQ_LDO1-3 470 nF ceramic capacitor (X7R) Tracker bypass capacitors CQ_T1-6 F ceramic capacitor (X7R) SPI rise and fall timings, CS, DI, CLK tr,f 100 20 1 200 k ns CB, min needs about LB=47H to avoid instabilities Data Sheet 29 Rev. 2.3, 2009-05-04 TLE6368-G2 3.4 Electrical Characteristics The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical values represent the median values at room temperature, which are related to production processes. -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. max. 280 370 425 Unit Test Conditions Buck regulator 3.4.1 Switching frequency fSW 3.4.2 Current transition time, min., rising edge tr_I_SW 20 ns RSL=0; 1) 3.4.3 Current transition time, max., rising edge tr_I_SW 100 ns RSL=20k; 1) 3.4.4 Current transition time, min., falling edge tf_I_SW 20 ns RSL=0; 1) 3.4.5 Current transition time, max., falling edge tf_I_SW 100 ns RSL=20k; 1) 3.4.6 Voltage rise / tf_V_SW fall time 25 ns 1) 3.4.7 Static on resistance RON 160 m Tj=25C in static operation 3.4.8 Static on resistance RON 280 400 m Tj=150C in static operation 3.4.9 Current limit IMAX 1.5 3.2 A VFB/L_IN=5.4V 3.4.10 Output voltage VOUT 5.40 6.05 V IOUT=1.5A VIN=13.5 V Data Sheet 30 kHz Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. Unit Test Conditions 6.3 V IOUT=0.1A VIN=13.5 V 220 A max. 3.4.11 Output voltage VOUT 5.4 3.4.12 Bootstrap charging current at start-up IBTSTR 80 3.4.13 Bootstrap voltage (internal charge pump) VBTSTR 10 15 V 5 9 V 3.4.14 Bootstrap VBTSTR, undervoltage turn on lockout, Buck turn on threshold 2.5 3.4.15 Bootstrap VBTSTR, undervoltage turn on VBTSTR, lockout, hysteresis turn off 3.4.16 External charge pump voltage VCCP 3.4.17 Max. Duty Cycle dutymax 3.4.18 Min. Duty Cycle dutymin 160 7.9 VFB/L_IN=6.5V, Buck converter off V 11.0 V IQ_LDO1 = 800mA, VFB/L_IN=6.0V, CFLY=100nF, CCCP=220nF % Switching operation 0 % Static-off operation 5.1 V 100mA < IQ_LDO1 < 800mA V IQ_LDO1 = 800mA 95 Voltage Regulator Q_LDO1 3.4.19 Output voltage VQ1 3.4.20 Output voltage VQ1 Data Sheet 4.9 5.0 31 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. 3.4.21 Load Regulation VQ_LDO1 typ. 3.4.22 Current limit IQ_LDO1limit 800 1050 PSRR1 26 40 3.4.24 Output Capacitor CQ_LDO1 470 Test Conditions mV 100mA< IQ_LDO1 <800mA; VFB/L_IN=5.5V max. 40 3.4.23 Ripple rejection Unit 1400 mA VQ_LDO1=4V dB f=330kHz; 1) nF Ceramic type, value for stability V 50mA < IQ_LDO2 < 400mA; 3.3V mode V IQ_LDO2 =400mA; 3.3V mode V 50mA < IQ_LDO2 < 400mA; 2.6V mode V IQ_LDO2 =400mA; 2.6V mode V 85mA < IQ_LDO2 < 400mA; 2.6V mode Voltage Regulator Q_LDO2 3.4.25 Output voltage 3.3V VQ_LDO2 3.4.26 Output voltage 3.3V VQ_LDO2 3.4.27 Output voltage 2.6V VQ_LDO2 3.4.28 Output voltage 2.6V VQ_LDO2 3.4.29 Output voltage 2.6V VQ_LDO2 3.4.30 Load Regulation VQ_LDO2 50 mV 50mA< IQ_LDO2 <400mA; VFB/L_IN=5.5V 3.3V mode 3.4.31 Load Regulation VQ_LDO2 50 mV 50mA< IQ_LDO2 <400mA; VFB/L_IN=5.5V 2.6V mode 3.4.32 Current limit IQ_LDO2limit 500 650 850 mA VQ_LDO2= 2.8V; 3.3V mode 3.4.33 Current limit IQ_LDO2limit 500 650 850 mA VQ_LDO2= 2V; 2.6V mode Data Sheet 3.14 3.46 3.32 2.500 2.750 2.62 2.50 2.70 32 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. 40 3.4.34 Ripple rejection PSRR2 26 3.4.35 Output Capacitor CQ_LDO2 470 Unit Test Conditions dB f=330kHz; 1) nF Ceramic type, value for stability V 20mA < IQ_LDO3 < 300mA; 3.3V mode V IQ_LDO3 =300mA; 3.3V mode V 20mA < IQ_LDO3 < 300mA; 2.6V mode max. Voltage Regulator Q_LDO3 3.4.36 Output voltage 3.3V VQ_LDO3 3.4.37 Output voltage 3.3V VQ_LDO3 3.4.38 Output voltage 2.6V VQ_LDO3 3.4.39 Output voltage 2.6V VQ_LDO3 2.625 V IQ_LDO3 =300mA; 2.6V mode 3.4.40 Load Regulation VQ_LDO3 30 mV 20mA< IQ_LDO3 <300mA; VFB/L_IN=5.5V 3.3V mode 3.4.41 Load Regulation VQ_LDO3 30 mV 20mA< IQ_LDO3 <300mA; VFB/L_IN=5.5V 2.6V mode 3.4.42 Current limit IQ_LDO3 3.14 3.46 3.32 2.500 2.750 350 500 600 mA VQ_LDO3=2.8V; 3.3V mode 350 500 600 mA VQ_LDO3=2V; 2.6V mode 40 dB f=330kHz; 1) nF Ceramic type, value for stability limit 3.4.43 Current limit IQ_LDO3 limit 3.4.44 Ripple rejection PSRR3 26 3.4.45 Output Capacitor CQ_LDO3 470 Voltage Tracker Q_T1 Data Sheet 33 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. max. -15 -2 5 Unit Test Conditions mV VQ_T1-VQ_LDO1; 1mA < IQ_T1 < 17mA 3.4.46 Output voltage tracking accuracy VQ_T1 3.4.47 Output voltage tracking accuracy VQ_T1 -10 mV VQ_T1-VQ_LDO1; IQ_T1 = 17mA 3.4.48 Overvoltage threshold VOVQ_T1 VQ_T1, mV IQ_T1 = 0mA; 1) mV 1) mA VQ_T1=4V nom 3.4.49 Undervoltage VUVQ_T1 threshold VQ_T115mV 3.4.50 Current limit IQ_T1 limit 17 3.4.51 Ripple rejection PSRR 26 dB f=330kHz; 1) 1 F Ceramic type, minimum for stability mV VQ_T2-VQ_LDO1; 1mA < IQ_T2 < 17mA 3.4.52 Tracker load CQ_T1 capacitor 30 Voltage Tracker Q_T2 3.4.53 Output voltage tracking accuracy VQ_T2 3.4.54 Output voltage tracking accuracy VQ_T2 -10 mV VQ_T2-VQ_LDO1; IQ_T2 = 17mA 3.4.55 Overvoltage threshold VOVQ_T2 VQ_T2, mV IQ_T2 = 0mA; 1) mV 1) mA VQ_T2=4V dB f=330kHz; 1) -15 5 nom 3.4.56 Undervoltage VUVQ_T2 threshold VQ_T215mV 3.4.57 Current limit IQ_T2 limit 17 3.4.58 Ripple rejection PSRR 26 Data Sheet -2 30 34 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. 3.4.59 Tracker load CQ_T2 capacitor typ. Unit Test Conditions F Ceramic type, minimum for stability mV VQ_T3-VQ_LDO1; 1mA < IQ_T3 < 17mA max. 1 Voltage Tracker Q_T3 3.4.60 Output voltage tracking accuracy VQ_T3 3.4.61 Output voltage tracking accuracy VQ_T3 -10 mV VQ_T3-VQ_LDO1; IQ_T3 = 17mA 3.4.62 Overvoltage threshold VOVQ_T3 VQ_T3, mV IQ_T3 = 0mA; 1) mV 1) -15 -2 5 nom 3.4.63 Undervoltage VUVQ_T3 threshold VQ_T315mV 3.4.64 Current limit IQ_T3 limit 17 mA VQ_T3=4V 3.4.65 Ripple rejection PSRR 26 dB f=330kHz; 1) 1 F Ceramic type, minimum for stability mV VQ_T4-VQ_LDO1; 1mA < IQ_T4 < 17mA 3.4.66 Tracker load CQ_T3 capacitor 30 Voltage Tracker Q_T4 3.4.67 Output voltage tracking accuracy VQ_T4 3.4.68 Output voltage tracking accuracy VQ_T4 -8 mV VQ_T4-VQ_LDO1; IQ_T4 = 17mA 3.4.69 Overvoltage threshold VOVQ_T4 VQ_T4, mV IQ_T4 = 0mA; 1) Data Sheet -15 -2 5 nom 35 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. 3.4.70 Undervoltage VUVQ_T4 threshold typ. Unit Test Conditions mV 1) mA VQ_T4=4V max. VQ_T415mV 3.4.71 Current limit IQ_T4 limit 17 3.4.72 Ripple rejection PSRR 26 dB f=330kHz; 1) 1 F Ceramic type, minimum for stability mV VQ_T5-VQ_LDO1; 1mA < IQ_T5 < 17mA 3.4.73 Tracker load CQ_T4 capacitor 30 Voltage Tracker Q_T5 3.4.74 Output voltage tracking accuracy VQ_T5 3.4.75 Output voltage tracking accuracy VQ_T5 -9 mV VQ_T5-VQ_LDO1; IQ_T5 = 17mA 3.4.76 Overvoltage threshold VOVQ_T5 VQ_T5, mV IQ_T5 = 0mA; 1) mV 1) mA VQ_T5=4V -15 -1 5 nom 3.4.77 Undervoltage VUVQ_T5 threshold VQ_T515mV 3.4.78 Current limit IQ_T5 limit 17 3.4.79 Ripple rejection PSRR 26 dB f=330kHz; 1) 1 F Ceramic type, minimum for stability mV VQ_T6-VQ_LDO1; 1mA < IQ_T6 < 17mA 3.4.80 Tracker load CQ_T5 capacitor 30 Voltage Tracker Q_T6 3.4.81 Output voltage tracking accuracy Data Sheet VQ_T6 -15 -1 36 5 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. Unit Test Conditions max. 3.4.82 Output voltage tracking accuracy VQ_T6 -9 mV VQ_T6-VQ_LDO1; IQ_T6 = 17mA 3.4.83 Overvoltage threshold VOVQ_T6 VQ_T6 mV IQ_T6 = 0mA; 1) VQ_T615mV mV 1) mA VQ_T6=4V 3.4.84 Undervoltage VUVQ_T6 threshold 3.4.85 Current limit IQ_T6 limit 17 3.4.86 Ripple rejection PSRR 26 dB f=330kHz; 1) 1 F Ceramic type, minimum for stability 3.4.87 Tracker load CQ_T6 capacitor 30 Standby Regulator 2.2 3.4.88 Output voltage VQ_STB 3.4.89 Current limit IQ_STB limit 1 3.4.90 Standby load capacitor CQ_STB 2.4 2.6 V 0A <IQ_STB<500A 3 6 mA VQ_STB=2V nF Ceramic type, minimum for stability 100 Current consumption in off-mode and Wake block 3.4.91 Supply current from battery Iq,off 10 30 A VIN=13.5V, Vwake=0 IQ_STB=0A 3.4.92 Supply current from battery Iq,off 10 30 A VIN=42V, Vwake=0 IQ_STB=0A 3.4.93 Turn on Wake-up threshold Vwake th, on 2.4 2.8 V Vwake increasing Data Sheet 37 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. Unit Test Conditions V Vwake decreasing max. 3.4.94 Turn off Wake-up threshold Vwake th, off 1.8 2.35 3.4.95 Wake-up input current Iwake 50 150 A Vwake=5V 4 10 50 s Vwake > Vwake th, max; 1) 4.5 4.65 4.8 V VQ_LDO1 decreasing 4.55 4.70 4.9 V VQ_LDO1 increasing 3.4.99 Reset output VR1 L low voltage 0.4 V IR1=1.6mA; VQ_LDO1 =5V 3.4.100 Reset output VR1 L low voltage 0.3 V IR1=0.3mA; VQ_LDO1 =1V A VQ_LDO1 =0.75V; Tj > 25C 3.4.96 Wake up twake,min input on time Reset R1 3.4.97 Reset threshold Q_LDO1 3.4.98 Reset threshold Q_LDO1 VRTH Q_LDO1, de VRTH Q_LDO1, in 3.4.101 Reset output IR1 L low sink current 3.4.102 Reset High leakage current 10 IR1 H 1 A 3.0 V 3.3V mode; VQ_LDO2 decreasing mV 3.3V mode Reset R2 3.4.103 Reset threshold Q_LDO2 Q_LDO2, de 3.4.104 Reset threshold hysteresis Q_LDO2 Q_LDO2, in Data Sheet VRTH 2.6 2.8 40 VRTH - VRTH Q_LDO2, de 38 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol 3.4.105 Reset threshold Q_LDO2 VRTH 3.4.106 Reset threshold hysteresis Q_LDO2 VRTH Limit Values min. typ. max. 2.3 2.4 2.5 Unit Test Conditions V 2.6V mode; VQ_LDO2 decreasing mV 2.6V mode Q_LDO2, de Q_LDO2, in 40 - VRTH Q_LDO2, de 3.4.107 Reset output VR2 L low voltage 0.4 V IR2=1.6mA; VQ_LDO2 =2.5V 3.4.108 Reset output VR2 L low voltage 0.3 V IR2=0.3mA; VQ_LDO2 =1V A VQ_LDO2 =0.75V; Tj > 25C 3.4.109 Reset output IR2 L low sink current 3.4.110 Reset High leakage current 10 IR2 H 1 A 3.0 V 3.3V mode; VQ_LDO3 decreasing mV 3.3V mode V 2.6V mode; VQ_LDO3 decreasing mV 2.6V mode V IR3=1.6mA; VQ_LDO3 =3.3V Reset R3 3.4.111 Reset threshold Q_LDO3 VRTH 2.7 2.85 Q_LDO3, de 3.4.112 Reset threshold hysteresis Q_LDO3 VRTH 3.4.113 Reset threshold Q_LDO3 VRTH 3.4.114 Reset threshold hysteresis Q_LDO3 VRTH 40 Q_LDO3, in VRTH Q_LDO3, de 2.3 2.35 Q_LDO3, de 40 Q_LDO3, in VRTH Q_LDO3, de 3.4.115 Reset output VR3 L low voltage Data Sheet 2.5 0.4 39 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. 3.4.116 Reset output VR3 L low voltage 3.4.118 Reset High leakage current 10 IR3 H 3.4.119 Reset trr reaction time 1 2 Test Conditions V IR3=0.3mA; VQ_LDO3 =1V A VQ_LDO3 =0.75V; Tj > 25C max. 0.3 3.4.117 Reset output IR3 L low sink current Unit 1 A 10 s 1) Valid for R1, R2 and R3 3.4.120 Reset Delay Norm factor tNORM,RES 0.75 1 1.25 1 3.4.121 Reset Delay time tRES 0.75 1 1.25 tRES(SPI) Valid for R1, R2 and R3; tRES (SPI) is defined by the SPI word (see section 2.12) 3.4.122 VQ1 threshold VTh Q1 2.3 2.8 3.3 V 3.4.123 VQ2 threshold VTh Q2 1.2 1.4 1.7 V 3.3V mode 3.4.124 VQ2 threshold VTh Q2 1.2 1.4 1.7 V 2.6V mode; 1) RAM Good Window Watchdog 3.4.125 Closed window time tolerance tCW_tol 0.75 1 1.25 Multiply with watchdog window time set by SPI to obtain the limits (2.12) 3.4.126 Open window time tolerance tOW_tol 0.75 1 1.25 Multiply with watchdog window time set by SPI to obtain the limits (2.12) Data Sheet 40 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values min. typ. 3.4.127 Watchdog reset low time tWRL tRES 3.4.128 Watchdog reset delay time tSR tCW/2 Unit Test Conditions - V IERR, H = 1 mA 0.5 V IERR, L = - 1.6 mA 2.5 MHz Production test up to 1MHz; For 2.5MHz: 1) % of - max. Error Output ERR VQ_LDO1 VQ_LDO1 - 2.0 - 0.7 VERR,L - 0.3 fCLK 0 3.4.132 H-input voltage threshold VIH - 3.4.133 L-input voltage threshold VIL 3.4.129 H-output voltage level VERR,H 3.4.130 L-output voltage level SPI 3.4.131 SPI clock frequency SPI Input DI 40 70 VQ_LDO1 20 36 - % of - VQ_LDO1 3.4.134 Hysteresis of VIHY input voltage 50 200 500 mV 1) 3.4.135 Pull down current II 5 25 100 A VDI = 0.2 * VQ_LDO1 3.4.136 Input capacitance CI - 10 15 pF 0 V < VQ_LDO1 < 5.25 V 3.4.137 Input signal rise time tr - - 200 ns 1) 3.4.138 Input signal fall time tf - - 200 ns 1) SPI Clock Input CLK Data Sheet 41 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol 3.4.139 H-input voltage threshold VIH 3.4.140 L-input voltage threshold VIL Limit Values min. typ. max. - 40 70 Unit Test Conditions % of - VQ_LDO1 20 36 - % of - VQ_LDO1 3.4.141 Hysteresis of VIHY input voltage 50 200 500 mV 1) 3.4.142 Pull down current II 5 25 100 A VCLK = 0.2 * VQ_LDO1 3.4.143 Input capacitance CI - 10 15 pF 0 V < VQ_LDO1 < 5.25 V 3.4.144 Input signal rise time tr - - 200 ns 1) 3.4.145 Input signal fall time tf - - 200 ns 1) - 39 70 % of - SPI Chip Select Input CS 3.4.146 H-input voltage threshold VIH 3.4.147 L-input voltage threshold VIL VQ_LDO1 20 35 - % of - VQ_LDO1 3.4.148 Hysteresis of VIHY input voltage 50 200 500 mV 1) 3.4.149 Pull up II, CS current at pin CS - 100 - 25 -5 A VCS = 0.2 * VQ_LDO1 3.4.150 Input capacitance CI - 10 15 pF 0 V < VQ_LDO1 < 5.25 V 3.4.151 Input signal rise time tr - - 200 ns 1) 3.4.152 Input signal fall time tf - - 200 ns 1) Data Sheet 42 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max. VQ_LDO1 VQ_LDO1 - V - 1.0 - 0.8 IDOH = 1 mA Logic Output DO 3.4.153 H-output voltage level VDOH 3.4.154 L-output voltage level VDOL - 0.2 0.4 V IDOL = - 1.6 mA 3.4.155 Tri-state leakage current IDO_TRI - 10 - 10 A VCS = VQ_LDO1; 0 V < VDO < VQ_LDO1 3.4.156 Tri-state input capacitance CDO - 10 15 pF VCS = VQ_LDO1 0 V < VQ_LDO1 < 5.25 V tpCLK tCLKH 400 - - ns 1) 100 - - ns 1) 3.4.159 Clock low time tCLKL 100 - - ns 1) 3.4.160 Clock low before CS low tbef 500 - - ns 1) 3.4.161 CS setup time tlead 500 - - ns 1) 3.4.162 CLK setup time tlag 500 - - ns 1) 3.4.163 Clock low tbeh after CS high 500 - - ns 1) 3.4.164 DI setup time tDISU 50 - - ns 1) tDIHO 50 - - ns 1) Data Input Timing 3.4.157 Clock period 3.4.158 Clock high time 3.4.165 DI hold time Data Output Timing Data Sheet 43 Rev. 2.3, 2009-05-04 TLE6368-G2 -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max. 3.4.166 DO rise time trDO - 50 100 ns CL = 100 pF 3.4.167 DO fall time tfDO tENDO - 50 100 ns CL = 100 pF - - 250 ns low impedance tDISDO - - 250 ns high impedance 3.4.170 DO valid time tVADO - 100 200 ns VDO < 10% VDO > 90% CL = 100 pF C 2) C 2) 3.4.168 DO enable time 3.4.169 DO disable time General 3.4.171 Temperature TJ,Flag warning flag 140 3.4.172 Over TJ,Shutdown 150 Temperature shutdown 170 3.4.173 OverTsd_hys Temperature shutdown Hysteresis 30 K 3.4.174 Delta of TWF TJ,Shutdown to TSD - TJ,Flag 20 K 1) Specified by design, not subject to production test 2) Simulated at wafer test only, not absolutely measured Data Sheet 44 200 Rev. 2.3, 2009-05-04 TLE6368-G2 4 Typical characteristics performance Buck converter DMOS on-resistance vs. junction temperature Buck converter switching frequency vs. junction temperature fSW kHz 420 RON m 400 400 350 380 300 360 250 340 200 320 150 300 100 280 -50 -20 10 40 70 100 130 Tj 50 -50 160 -20 10 40 70 100 130 Tj 160 C C Buck converter output voltage at 1.5A load Buck converter current limit vs. junction temperature vs. junction temperature VFB/L_IN V 6.0 IMAX A 4.0 5.9 3.5 5.8 3.0 5.7 2.5 5.6 2.0 5.5 1.5 5.4 1.0 5.3 -50 -20 10 40 70 100 130 Tj 160 -20 10 40 70 100 130 Tj 160 C C Data Sheet 0.5 -50 45 Rev. 2.3, 2009-05-04 TLE6368-G2 Bootstrap UV lockout, turn on threshold vs. junction temperature Start-up bootstrap charging current vs. junction temperature IBTSTR A V BTSTR, 8.5 280 turn on V 240 8.0 200 7.5 160 7.0 120 6.5 80 6.0 40 5.5 0 -50 -20 10 40 70 100 130 Tj 5.0 -50 160 -20 10 40 70 100 130 Device wake up thresholds vs. junction temperature Device start-up voltage (acc. to spec. 3.2) vs. junction temperature V 6.0 V wake th V 2.8 5.5 2.7 5.0 2.6 4.5 2.5 4.0 2.4 3.5 2.3 3.0 2.2 2.5 -50 V wake th, on V wake th, off -20 10 40 70 100 130 Tj 160 C Data Sheet 160 C C VIN Tj 2.1 -50 -20 10 40 70 100 130 Tj 160 C 46 Rev. 2.3, 2009-05-04 TLE6368-G2 Q_LDO1 current limit vs. junction temperature Q_LDO1 output voltage at 800mA load vs. junction temperature VQ_LDO1 V 5.20 IQ_LDO1 V 5.15 1400 1300 5.10 1200 5.05 1100 5.00 1000 4.95 900 4.90 800 4.85 -50 -20 10 40 70 100 130 Tj 700 -50 160 -20 10 40 70 100 C 4.80 VQ_LDO2 V 2.80 4.75 2.75 4.70 2.70 4.65 2.65 4.60 2.60 4.55 2.55 4.50 2.50 4.45 -50 -20 10 40 70 100 130 Tj 160 C Data Sheet 160 Q_LDO2 output voltage at 400mA load (2.6V mode) vs. junction temperature Q_LDO1, de V Tj C Reset1 threshold at decreasing V_LDO1 vs. junction temperature VRTH 130 2.45 -50 -20 10 40 70 100 130 Tj 160 C 47 Rev. 2.3, 2009-05-04 TLE6368-G2 Reset2 threshold at decreasing V_LDO2 (2.6V mode) vs. junction temperature Q_LDO2 current limit (2.6V mode) vs. junction temperature IQ_LDO2 V VRTH 850 2.60 Q_LDO2, de V 800 2.55 750 2.50 700 2.45 650 2.40 600 2.35 550 2.30 500 -50 -20 10 40 70 100 130 Tj 2.25 -50 160 -20 10 40 70 100 130 C C Q_LDO3 current limit (3.3V mode) vs. junction temperature Q_LDO3 output voltage at 300mA load (3.3V mode) vs. junction temperature VQ_LDO3 V 3.50 IQ_LDO3 V 3.45 600 550 3.40 500 3.35 450 3.30 400 3.25 350 3.20 300 3.15 -50 -20 10 40 70 100 130 Tj 160 C Data Sheet 160 Tj 250 -50 -20 10 40 70 100 130 Tj 160 C 48 Rev. 2.3, 2009-05-04 TLE6368-G2 Tracker accuracy with respect to V_LDO1 vs. junction temperature Reset3 threshold at decreasing V_LDO3 (3.3V mode) vs. junction temperature VRTH 3.00 dVQ_Tx Q_LDO3, de V mV 4 2.95 2 2.90 0 2.85 -2 2.80 -4 2.75 -6 2.70 -8 2.65 -50 -20 10 40 70 100 130 Tj -10 -50 160 -20 10 40 70 100 130 C mA Q_STB output voltage at 500A load vs. junction temperature 32 V Q_STB V 30 2.8 2.7 28 2.6 26 2.5 24 2.4 22 2.3 20 2.2 18 -50 -20 10 40 70 100 130 Tj 160 C Data Sheet 160 C Tracker current limit vs. junction temperature IQ_Tx Tj 2.1 -50 -20 10 40 70 100 130 Tj 160 C 49 Rev. 2.3, 2009-05-04 TLE6368-G2 Q_STB current limit vs. junction temperature IQ_STB mA Device current consumption in off mode vs. junction temperature 4.0 Iq, off A 3.5 35 30 3.0 25 2.5 20 2.0 15 1.5 10 1.0 5 0.5 -50 -20 10 40 70 100 130 Tj 160 C Data Sheet 0 -50 -20 10 40 70 100 130 Tj 160 C 50 Rev. 2.3, 2009-05-04 TLE6368-G2 5 Application Information 5.1 Application Diagram RBoost 22 TLE 6368 DBOOST Battery CI1 CSTB BOOST 100 nF Up to 47 H Q_STB 100 nF CBOOST LI Standby Regulator 2.5 V 2* IN + 100 nF CI3 CI2 0 to 20 k ErrorAmplifier OSZ 680 nF BOOTSTRAP Driver RSlew 47 H + DB 3 A, 60 V CBTSTR Buck Regulator 10 to 100 nF SLEW 47 F PWM Buck Output LB SW 2* CB > 10 F ceramic or > 20 F low ESR tantalum Internal Reference Feedback To IGN FB/L_IN 2* C+ CFLY Protection 10 k Charge Pump Q_LDO1 WAKE 10 k 10 k 10 k Power Down Logic R2 100 nF CCP CCCP SEL R1 To C C- Reset Logic R3 Lin. Reg. 5V Q_LDO1 Lin. Reg. 3.3/2.6 V Q_LDO2 Lin. Reg. 5/3.3 V Q_LDO3 220 nF CLDO1,1 + CLDO1,2 CLDO2,1 + CLDO2,2 CLDO3,1 + CLDO3,2 470 nF 470 nF 470 nF Ref Window Watchdog To C 10 k CLK 10 k CS 10 k DI 1 k DO Ref Ref Ref SPI 16 Bit Ref Ref ERR Tracker 5V Q_T1 Tracker 5V Q_T2 Tracker 5V Q_T3 Tracker 5V Q_T4 Tracker 5V Q_T5 Tracker 5V Q_T6 4.7 F 4.7 F -Controller/ Memory Supply 4.7 F CT1 1 F CT2 1 F CT3 1 F CT4 1 F Sensor Supplies (off board supplies) CT5 1 F CT6 1 F GND 4* AEA03380ZR.VSD Figure 14 Application Diagram Data Sheet 51 Rev. 2.3, 2009-05-04 TLE6368-G2 5.2 Buck converter circuit A typical choice of external components for the buck converter is given in figure 14. For basic operation of the buck converter the input capacitor CI2, the bootstrap capacitor CBTP, the catch diode DB, the inductance LB, the output capacitor CB and the charge pump capacitors CFLY and CCCP are necessary. A Zener Diode at the FB/L_IN input is recommended as a protection against overvoltage spikes. The additional components shown on top of the circuit lower the electromagnetic emission (LI, CI1, CI3, RSlew) and the switching losses (RBoost, CBoost, DBoost). For 12V battery systems the switching loss minimization feature might not be used. The Boost pin (33) is connected directly to the IN pins (32, 30) in that case and the components RBoost, CBoost and DBoost are left away. 5.2.1 Buck inductance (LB) selection: The inductance value determines together with the input voltage, the output voltage and the switching frequency the current ripple which occurs during normal operation of the step down converter. This current ripple is important for the all over ripple at the output of the switching converter. As a rule of thumb this current ripple I is chosen between 10% and 50% of the load current. ( V I - V OUT ) V OUT L = -------------------------------------------------f SW V I I For optimum operation of the control loop of the Buck converter the inductance value should be in the range indicated in section 3.3, recommended operation range. When picking finally the inductance of a certain supplier (Epcos, Coilcraft etc.) the saturation current has to be considered. With a maximum current limit of the Buck converter of 3.2A an inductance with a minimum saturation current of 3.2A has to be chosen. Data Sheet 52 Rev. 2.3, 2009-05-04 TLE6368-G2 5.2.2 Buck output capacitor (CB) selection: The choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of the buck converter. In continuous conduction mode the ripple of the output voltage equals: 1 V Ripple = I R ESRCB + ---------------------------- C 8f SW B From the formula it is recognized that the ESR has a big influence in the total ripple at the output, so ceramic types or low ESR tantalum capacitors are recommended for the application. One other important thing to note are the requirements for the resonant frequency of the output LC-combination. The choice of the components L and C have to meet also the specified range given in section 3.3 otherwise instabilities of the regulation loop might occur. 5.2.3 Input capacitor (CI2) selection: At high load currents, where the current through the inductance flows continuously, the input capacitor is exposed to a square wave current with its duty cycle VOUT/VI. To prevent a high ripple to the battery line a capacitor with low ESR should be used. The maximum RMS current which the capacitor has to withstand is calculated to: 2 V OUT 1 I I RMS = I LOAD ------------- 1 + --- ----------------------- 3 2 ILOAD V IN 5.2.4 Freewheeling diode / catch diode (DB) For lowest power loss in the freewheeling path Schottky diodes are recommended. With those types the reverse recovery charge is negligible and a fast handover from freewheeling to forward conduction mode is possible. Depending on the application (12V battery systems) 40V types could be also used instead of the 60V diodes. A fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance values (smaller spikes) are desired, the slew resistor should be set in this case between 10 and 20kW. Data Sheet 53 Rev. 2.3, 2009-05-04 TLE6368-G2 5.2.5 Bootstrap capacitor (CBTP) The voltage at the Bootstrap capacitor does not exceed 15V, a ceramic type with a minimum of 2% of the buck output capacitance and voltage class 16V would be sufficient. 5.2.6 External charge pump capacitors (CFLY, CCCP) Out of the feedback voltage the charge pump generates a voltage between 8 and 10V. The fly capacitor connected between C+ and C- is charged with the feedback voltage level and discharged to achieve the (almost) double voltage level at CCP. CFLY is chosen to 100nF and CCCP to 220nF, both ceramic types. The connection of CCP to a voltage source of e.g. 7V (take care of the maximum ratings!) via a diode improves the start-up behavior at very low battery voltage. The diode with the cathode on CCP has to be used in order to avoid any influence of the voltage source to the device's operation and vice versa. 5.2.7 Input filter components for reduced EME (CI1, CI2, CI3, LI, RSlew) At the input of Buck converters a square wave current is observed causing electromagnetical interference on the battery line. The emission to the battery line consists on one hand of components of the switching frequency (fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the current slope. For proper attenuation of those interferers a -type input filter structure is recommended which is built up with inductive (LI) and capacitive components (CI1, CI2, CI3). The inductance can be chosen up to the value of the Buck converter inductance, higher values might not be necessary, CI1 and CI3 should be ceramic types and for CI2 an input capacitance with very low ESR should be chosen and placed as close to the input of the Buck converter as possible. Inexpensive input filters show due to their parasitics a notch filter characteristic, which means basically that the lowpass filter acts from a certain frequency as a highpass filter and means further that the high frequency components are not attenuated properly. For that reason the TLE6368-G2 offers the possibility of current slope adjustment. The current transition time can be set by the external resistor (located on the SLEW pin) to times between 20ns and 80ns by varying the resistor value between 0 (fastest transition) and 20k (slowest transition). 5.2.8 Feedback circuit for minimum switching loss (RBoost, CBoost, DBoost) To decrease the switching losses to a minimum the external components RBoost, CBoost and DBoost are needed. The current though the feedback resistor RBoost is about a few mA where the Diode DBoost and the capacitor CBoost run a part of the load current. If this feature is not needed the three components are not needed and the Boost pin (33) can be connected directly to the IN pins(32, 30). Data Sheet 54 Rev. 2.3, 2009-05-04 TLE6368-G2 5.3 Reverse polarity protection The Buck converter is due to the parasitic source drain diode of the DMOS not reverse polarity protected. Therefore, as an example, the reverse polarity diode is shown in the application circuit, in general the reverse polarity protection can be done in different ways. 5.4 Linear voltage regulators (CLDO1, 2, 3) As indicated before the linear regulators show stable operation with a minimum of 470nF ceramic capacitors. To avoid a high ripple at the output due to load steps this output cap might have to be increased to some few F capacitors. 5.5 Linear voltage trackers (CT1,2,3,4,5,6) The voltage trackers require at their outputs 1F ceramic capacitors each to avoid some oscillation at the output. If needed the tracker outputs can be connected in parallel, in that the output capacitor increases linear according to the number of parallel outputs. 5.6 Reset outputs (R1,2,3) The undervoltage/watchdog reset outputs are open drain structures and require external pull up resistors in the range of 10k to the C I/O voltage rail. Data Sheet 55 Rev. 2.3, 2009-05-04 TLE6368-G2 5.7 Components recommendation - overview Device Type Supplier Remark LI B82479 EPCOS 22H, 3.5A, 47m DO3340P-473 Coilcraft 47H, 3.8A, 110m DO5022P-683 Coilcraft 68H, 3.5A, 130m DS5022P-473 Coilcraft 47H, 4.0A, 97m SLF12575T-330M3R2H TDK 33H, 3.2A CI1 Ceramic various 100nF, 60V CI2 Low ESR tantalum various 47F, 60V CI3 Ceramic various 10nF to 100nF, 60V DBoost S3B various LB B82479 EPCOS 22H, 3.5A, 47m DO3340P-473 Coilcraft 47H, 3.8A, 110m DO5022P-683 Coilcraft 68H, 3.5A, 130m DS5022P-473 Coilcraft 47H, 4.0A, 97m SLF12575T-330M3R2H TDK 33H, 3.2A CBTSR Ceramic various 680nF, 10V DB MBRD360 ON Schottky, 60V, 3A MBRD340 ON Schottky, 40V, 3A SS34 FCH Schottky, 40V, 3A B45197-A2226 EPCOS Low ESR Tantalum, 22F, 10V, C-case 2 * LMK316BJ475ML Taiyo Yuden 2* Ceramic X7R, 4.7F, 10V CB C3216X7R1C106M TDK Ceramic X7R, 10F, 16V TPSC476K010R350 AVX Low ESR Tantalum, 47F, 10V, C-case CLDOx Ceramic various 470nF, 10V CTx Ceramic various 1F, 60V Data Sheet 56 Rev. 2.3, 2009-05-04 TLE6368-G2 5.8 Layout recommendation The most sensitive points for Buck converters - when considering the layout - are the nodes at the input and the output of the Buck switch, the DMOS transistor. For proper operation the external catch diode and Buck inductance have to be connected as close as possible to the SW pins (29, 31). Best suitable for the connection of the cathode of the Schottky diode and one terminal of the inductance would be a small plain located next to the SW pins. The GND connection of the catch diode must be also as short as possible. In general the GND level should be implemented as surface area over the whole PCB as second layer, if necessary as third layer. The pin FB/L_IN is sensitive to noise. With an appropriate layout the Buck output capacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at the supply voltage pin e.g. as shown in the application diagram is mandatory. CI2 may either be a low ESR Tantalum capacitor or a ceramic capacitor. A minimum capacitance of 10F is recommended for CI2. To obtain the optimum filter capability of the input -filter it has to be located also as close as possible to the IN pins, at least the ceramic capacitor CI3 should be next to those pins. Data Sheet 57 Rev. 2.3, 2009-05-04 TLE6368-G2 6 Package Outlines PG-DSO-36-26 SMD = Surface Mounted Device 1.3 15.74 0.1 (Heatslug) 0.25 +0.07 -0 5 3 .02 6.3 Heatslug 0.1 C 36x 0.95 0.15 0.25 M A B C 17 x 0.65 = 11.05 14.2 0.3 0.25 B Bottom View 19 36 19 5.9 0.1 0.25 +0.13 36 B 2.8 3.2 0.1 0.65 11 0.15 1) 3.5 MAX. 0 +0.1 1.1 0.1 3.25 0.1 2) Dimensions in mm Index Marking 1 x 45 1 18 15.9 0.1 1) 10 13.7 -0.2 1 Heatslug A 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Stand off Green Product (RoHs compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 58 Rev. 2.3, 2009-05-04 TLE6368-G2 TLE6368-G2 Revision History: 2009-05-04 Previous Version: 2.2 Page Rev. 2.3 Subjects (major changes since last revision) 1 added new coverpage all Green version from the TLE6368-G1 data sheet 42, 43 Improvement of parameter 3.4.157, 3.4.158, 3.4.159, 3.4.164, 3.4.165 and 3.4.170 to be consistent with parameter 3.4.131. No modification of component or change in test specification 22 Figure 12: Drawing improved to be consistent with parameter 3.4.131 Data Sheet 59 Rev. 2.3, 2009-05-04 TLE6368-G2 Edition 2009-05 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet 60 Rev. 2.3, 2009-05-04