Features e Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer e Fast Write Cycle Times Page Write Cycle Time: 3.0 ms or 10 ms maximum 1 to 64 Byte Page Write Operation Low Power Dissipation 80 mA Active Current 200 1A CMOS Standby Current e Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 10 or 10 Cycles Data Retention: 10 years Single 5 V+ 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Full Military, Commercial, and Industrial Temperature Ranges Description The AT28C256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 LA. The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 (continued on next page) : . . . Pin Configurations TSOP Top View Eq 1 Bb AiO. Ait qd 2 27 B cE a 9H 3 os E oe =~ AIDQ 5 24 POS WE de ab vos voc Hy, 7 2 B vo3 Ata ya 21 6 GND a2zd "9 20" B woe a7 gq 10 19 P vol asg 18 - B VO0 AS g 12 7B AO a Eu Bis BA ' AT A14VCG_A13 Pin Name Function > vee A12 NC WE AO-A14 Addresses 3 a CE : 5 a9 CE Chip Enable Ait aE 7 OE OE Output Enable 8 Ato ME : 9 cE WE Write Enable 0 196 yo7 18D Vos VOO - VO7 Data Inputs/Outputs 17 B vos 16 B wa , NC No Connect 15 B vos W's 1 2 we 345 Note: PLCC package pins 1 and 17 are DONT CONNECT. AT28C256 256K (32K x 8) Paged CMOS EPROM 2-147Amer Description (Continued) bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations, Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be de- tected by DATA polling of 1/07. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmels 28C256 has additional features to ensure high quality and manufacturability. The device utilizes internat error correc- tion for extended endurance and improved data retention char- acteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EPROM for device identification or tracking. Block Diagram VCC __ DATA INPUTS/OUTPUTS GND VO0 - VO7 a | _ peeeeeee OeE> a= OE, CE AND WE DATA LATCH WE * LOGIC INPUT/OUTPUT cE > BUFFERS | YDECODER Y-GATING ADDRESS | * INPUTS CELL MATRIX L X DECODER + IDENTIFICATION Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature... -65C to +150C Ail Input Voltages (including N.C. Pins) with Respect to Ground ................. -0.6 V fo +6.25 V All Output Voltages with Respect to Ground ............-0.6 V to Vec +0.6 V Voltage on OE and AQ with Respect to Ground .........0.0..... -0.6Vto +13.5V 2-148 *NOTICE: Stresses beyond those listed under "Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the de- vice at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT28C256 meusDevice Operation READ: The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the mem- ory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OF is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. PAGE WRITE: The page write operation of the AT28C256 al- lows one to sixty-four bytes of data to be written into the device during a single internal programming period. A page write op- eration is initiated in the same manner as a byte write; the first byte written can then be followed by one to sixty-three addi- tional bytes. Each successive byte must be written within 150 ps (tpLc) of the previous byte. If the tgic limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6- A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The AO to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on 1/07. Once the write cycle has been completed, true data is valid on all out- puts, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, 1/06 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power Pin Capacitance (f= 1 MHz, T = 25C) supply. Atmel has incorporated both hardware and software fea- tures that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8 V the device will automatically time out 5 ms (typ- ical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be en- abled or disabled by the user; the AT28C256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three spe- cific addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after twc the entire AT28C256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C256. This is done by preceding the data to be written by the same three byte com- mand sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C256 during power-up and power- down conditions, All command sequences must conform to the page write timing specifications. The data in the enable and dis- able command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write tim- ers. No data will be written to the device; however, for the dura- tion of twc, read operations will effectively be polling opera- tions. DEVICE IDENTIFICATION: An extra 64 bytes of EPROM memory are available to the user for device identification. By raising A9 to 12 V + 0.5 V and using address locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. Typ Max Units Conditions CIN 4 6 pF Vin =0V Cout 8 12 pF Vout =0V Note: 1. This parameter is characterized and is not 100% tested. AIMEL 2-149AImEt D.C. and A.C. Operating Range AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35 ; Com. 0C - 70C 0C - 70C 0c - 70C Temperature (Case) Ind. -40C - 85C -40C - 85C -40C - 85C Mil. -55C - 125C 55C - 125C -55C - 125C -55C - 125C Vcc Power Supply 5V+10% 5V+10% 5V+10% 5V+10% Operating Modes Mode CE OE WE vo Read Vit VIL ViH Dout Write?) Vit Vin Vit Din Standby/Write Inhibit Vin x) x High Z Write Inhibit x x VIH Write Inhibit x VIL x Output Disable xX ViH X High Z Chip Erase Vit Vy Vit High Z Notes: 1. X can be Vz. or Vin. 3. Vu = 12.0 V+0.5 V. 2. Refer to A.C. Programming Waveforms. D.C. Characteristics Symbol Parameter Condition Min Max _ Units tu Input Load Current Vin=0VtoVeco+1V 10 pA ILo Output Leakage Current Vivo = 0 V to Vcc 10 LA Iset Voc Standby Current CMOS GE=Vec-0.3VtoVec +1 Vv om: Ind. 200 __ HA Mil. 300 pA Ispe Vec Standby Current TTL CE =2.0VtoVec+1V 3 mA Icc Voc Active Current f =5 MHz; lout =0mA 80 mA Vit Input Low Voltage 0.8 Vv ViH Input High Voltage 2.0 Vv VoL Output Low Voltage loL = 2.1mMA 45 v VoH Output High Voltage loH = -400 HA 2.4 Vv 2-150 ATV28C256 cqueees ATSC 256 A.C. Read Characteristics AT28C256-15 | AT28C256-20 | AT28C256-25 | AT28C 256-35 Symbol | Parameter Min Max Min Max Min Max Min Max Units tacc Address to Output Delay 150 200 250 350 ns tce | CE to Output Delay 150 200 250 350 ns toe | OE to Output Delay 0 70 80 0 100 0 100 ns tor | CE or OE to Output Float 0 50 0 55 0 60 0 70 ns Output Hold from OE, CE toH or Address, whichever 0 0 0 0 ns occurred first A.C. Read Waveforms ADDRESS >< ADDRESS VALID CE OE OUTPUT HIGH Z OUTPUT VALID Notes: 1. CE may be delayed up to tacc - tc after the address transition without impact on tacc. 2. OE may be delayed up to tcx - tox after the falling edge of CE without impact on tcg or by tacc - tog after an address change without impact on tacc. Input Test Waveforms and Measurement Level 3.0V AC AC DRIVING 1.5V MEASUREMENT LEVELS LEVEL 0.0V tr, tr< 5ns 3. tpg is specified from OE or CE whichever occurs first (CL =5 pF). 4, This parameter is characterized and is not 100% tested. Output Test Load 5.0V 1.8K OUTPUT PIN 1.3K Tt 100pF ANMEL 216iA.C. Write Characteristics ADE Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns TAH Address Hold Time 50 ns tcs Chip Select Set-up Time 0 ns tcH Chip Select Hold Time 0 ns twe Write Pulse Width (WE or CE) 100 ns tos Data Set-up Time 50 ns toH.toEH Data, OE Hold Time ) ns tov Time to Data Valid NRO two Write Cycle Time AT28C256 10 ms AT28C256F 3.0 ms Note: 1. NR = No Restiction A.C. Write Waveforms- WE Controlled OE 4 tOES 10EH ADDRESS tAS| |. tAH CE _ tCH _ ics | WE OO. tWPH DATA IN twe~ tDS| t+- tDV A.C. Write Waveforms- CE Controlled 2-152 OE I-tDH ADDRESS WE | tAS| LtAH a tCH TN ics CE IN Kx \ |- tWPH-] DATA IN AT28C256 {WwP. }+- tDV. iDS {DH |Page Mode Characteristics Symbol Parameter Min Max Units twe Write Cycle Time AT28C256 10 ms AT28C256F 3.0 ms tas Address Set-up Time 0 ns taH Address Hold Time 50 ns tps Data Set-up Time 50 ns tou Data Hold Time 0 ns twp Write Pulse Width 100 ns tic Byte Load Cycle Time 150 pis twPH Write Pulse Width High 50 ns Page Mode Write Waveforms a 9 1 tWPH B RRA Le tDH y , XK 7, {f}- tDS /f-$- DATA _Xvauio pats K x tL cc > aa BYTE 0 BYTE 1 BYTE 2 BYTE 37 BYTE 62 BYTE 63 T 3 4 Notes: A6 through A14 must specify the same page address during each high to low transition of WE Cor CE). OE must be high only when WE and CE are both low. Chip Erase Waveforms ts = ty = 5 psec (min.) tw = 10 msec (min.) Vo =12.0V1L05V 2-153Software Data AImEt other data is loaded. yr ; a) Software Data w) Protection Enable Algorithm Protection Disable Algorithm LOAD DATA AA LOAD DATA AA TO TO ADDRESS 5555 ADDRESS 5555 LOAD DATA 55 LOAD DATA 55 TO TO ADDRESS 2AAA ADDRESS 2AAA } LOAD DATA AO LOAD DATA 80 ADDRESS 5555 WRITES ENABLED 2) ADDRESS 5555 } i LOAD DATA XxX LOAD DATA AA TO (4) ANY ADDRESS ADDRESS 5555 } 1 LOAD LAST BYTE LOAD DATA 55 TO LAST ADDRESS ENTER DATA ADDRESS 2AAA PROTECT STATE 1 LOAD DATA 20 TO ADDRESS 5555 EXIT DATA Notes for software program code: PROTECT STATE 1. Data Format: 1/07 - 1/00 (Hex); LOAD DATA XX Address Format: A14 - AO (Hex). 4 2. Write Protect state will be activated at end of write even if no ANY Appress ) 3. Write Protect state will be deactivated at end of write period LOAD LAST BYTE even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. LAST ADDRESS Software Protected Write Cycle Waveforms (i OE (L rr 2 A __ tWPH tBLC , WE [~~] tDH , A0-A5 X ayTe ADDRESS x y 5555 ( A6-A14 A pace ADDRESS ( DATA Xs { = Kw X XX BYTE 0 BYTE 62 BYTE 63 e two Notes: A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. OE must be high only when WE and CE are both low. 2-154 AT28C256 @)ees A T2830 256 Data Polling Characteristics Symbol Parameter Min Typ Max Units tou Data Hold Time 0 ns toEH OE Hold Time ) ns tOE OE to Output Delay 100 ns twR Write Recovery Time 0 ns Note: 1, These parameters are characterized and not 100% tested. Data Polling Waveforms Toggle Bit Characteristics Symbol Parameter Min Typ Max Units {DH Data Hold Time 10 ns toEH OE Hold Time 10 ns toe OE to Output Delay 100 ns loEHP OE High Puise 150 ns twa Write Recovery Time 0 ns Note: 1. These parameters are characterized and not 100% tested. Toggle Bit Waveforms WE tWR Notes: 1, Toggling either OE or CE or both OE and CE will Operate toggle bit. 2. Beginning and ending state of 1/06 will vary. 3. Any address location may be used but the address should not vary. ATMEL 2-155AINE? NORMALIZED SUPPLY CURRENT vs. NORMALIZED SUPPLY CURRENT vs. 3 TEMPERATURE va SUPPLY VOLTAGE nt nt tak 2 TN 2 ! 11 aw | i . ' Oo 7 40 MN : 0.9 PS 08 LL | ( ~~] l C os pS c 06 -55 -25, 5 35 65 95 125 450 47 5.00 .25 .50 Temperature (C) Supply Voltage (V) NORMALIZED SUPPLY CURRENT vs. ADDRESS FREQUENCY N m 1.0 a _ | 09g aconaeggeennnnnny i z e 08 Vcc = 5V T=25C | 07 c C os 0 1 2 3 4 Frequency (MHz) 2-156 AT28C256 que .ens A 1230256 Ordering Information (e A = dby Ordering Code Package Operation Range 150 80 0.2 AT28C256(E,F)-15DC 28D6 Commercial AT28C256(E,F)-15JC 32J (0C to 70C) AT28C256(E,F)-15PC 28P6 AT28C256(E,F)-15TC 28T AT28C256(E,F)-15UC 28U AT28C256(E,F)-15DI 28D6 industrial AT28C256(E,F)-15ul 32J (-40C to 85C) AT28C256(E,F)-15P! 28P6 AT28C256(E,F)-15T! 28T AT28C256(E,F)-15Ul 28U 150 80 0.3 AT28C256(E,F)-15DM/883 28D6 Military/883C AT28C256(E,F)-15FM/883 28F Class B, Fully Compliant AT28C256(E,F)-15LM/383 32aL (-55C to 125C) AT28C256(E,F)-15UM/883 28U 200 80 0.2 AT28C256(E,F)-20DC 28D6 Commercial AT28C256(E,F)-20JC 32J (0C to 70C) AT28C256(E,F)-20PC 28P6 AT28C256(E,F)-20UC 28U AT28C256(E,F)-20DI 28D6 industrial AT28C256(E,F)-20u1 32J (-40C to 85C) AT28C256(E,F)-20PI 28P6 AT28C256(E,F)-20UI 28U 200 80 0.3 AT28C256(E,F)-20DM/883 28D6 Military/883C AT28C256(E,F)-20FM/883 28F Class B, Fully Compliant AT28C256(E,F)-20LM/883 32L (-55C to 125C) AT28C256(E,F)-20UM/883 28U 250 80 0.2 AT28C256(E,F)-25DC 28D6 Commercial AT28C256(E,F)-255C 32J (0C to 70C) AT28C256(E,F)-25PC 28P6 AT28C256(E,F)-25UC 28U AT28C256-W DIE AT28C256(E,F)-25DI 28D6 industrial AT28C256(E,F)-25uI 32J (-40C to 85C) AT28C256(E,F)-25PI 28P6 AT28C256(E,F)-25Ul 28U 250 80 0.3 AT28C256(E,F)-25DM/883 28D6 Military/883C AT28C256(E, F)-25FM/883 28F Class B, Fully Compliant AT28C256(E, F)-25LM/883 32L (-55C to 125C) AT28C256(E, F)-25UM/883 28U 300") 80 0.3 AT28C256(E,F)-30DM/883 28D6 Military/883C AT28C256(E,F)-30FM/883 28F Class B, Fully Compliant AT28C256(E,F)-30LM/883 32L (-55C to 125C) AT28C256(E,F)-30UM/883 28U 350 80 0.3 AT28C256(E,F)-35DM/883 28D6 Military/883C AT28C256(E,F)-35FM/883 28F Class B, Fully Compliant AT28C256(E, F)-35LM/883 32L (-55C to 125C) AT28C256(E,F)-35UM/883 28uU AIMEL 2-157Aline? Ordering Information ta loc (mA (ne) ee sendby Ordering Code Package Operation Range 150 80 0.35 5962-88525 07 UX 28U Military/883C 5962-88525 07 XX 28D6 Class B, Fully Compliant 5962-88525 07 YX 32L (-55C to 125C) 5962-88525 07 ZX 28F 5962-88525 06 UX 28U Military/883C 5962-88525 06 XX 28D6 Class B, Fully Compliant 5962-88525 06 YX 32L (-55C to 125C) 5962-88525 06 ZX 28F 200 80 0.35 5962-88525 04 UX 28U Military/883C 5962-88525 04 XX 28D6 Class B, Fully Compliant 5962-88525 04 YX 32L (-55C to 125C) 5962-88525 04 ZX 28F 250 80 0.35 5962-88525 03 UX 28U Military/883C 5962-88525 03 XX 28D6 Class B, Fully Comptiant 5962-88525 03 YX 32L (-55C to 125C) 5962-88525 03 ZX 28F 5962-88525 05 UX 28U Military/883C 5962-88525 05 XX 28D6 Class B, Fully Compliant 5962-88525 05 YX 32L (-55C to 125C) 5962-88525 05 ZX 28F 300") 80 0.35 5962-88525 02 UX 28U Military/883C 5962-88525 02 XX 28D6 Class B, Fully Compliant 5962-88525 02 YX 32L (-55C to 125C) 5962-88525 02 ZX 28F 350 80 0.35 5962-88525 01 UX 28U Military/883C 5962-88525 01 XX 28D6 Class B, Fully Compliant 5962-88525 01 YX 32L (-55C to 125C) 5962-88525 01 ZX 28F Notes: 1. Electrical specifications for these speeds are defined by Standardized Military Drawing 5962-88525. Package Type 28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadiess Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28T 28 Lead, Plastic Thin Smal! Outline Package (TSOP) 28U 28 Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 2-158 AT28C256 uummmmn