PD - 94818 IRF520NPbF Advanced Process Technology Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated Lead-Free HEXFET(R) Power MOSFET D VDSS = 100V RDS(on) = 0.20 G Description ID = 9.7A S Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. TO-220AB Absolute Maximum Ratings ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Parameter Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew 9.7 6.8 38 48 0.32 20 91 5.7 4.8 5.0 -55 to + 175 Units A W W/C V mJ A mJ V/ns C 300 (1.6mm from case ) 10 lbf*in (1.1N*m) Thermal Resistance Parameter RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Typ. Max. Units --- 0.50 --- 3.1 --- 62 C/W 11/5/03 IRF520NPbF Electrical Characteristics @ TJ = 25C (unless otherwise specified) RDS(on) VGS(th) gfs Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 100 --- --- 2.0 2.7 --- --- --- --- --- --- --- --- --- --- --- IDSS Drain-to-Source Leakage Current LD Internal Drain Inductance --- LS Internal Source Inductance --- Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance V(BR)DSS V(BR)DSS/TJ IGSS --- --- --- Typ. --- 0.11 --- --- --- --- --- --- --- --- --- --- 4.5 23 32 23 Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.20 VGS = 10V, ID = 5.7A 4.0 V VDS = VGS, ID = 250A --- S VDS = 50V, ID = 5.7A 25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 25 ID = 5.7A 4.8 nC VDS = 80V 11 VGS = 10V, See Fig. 6 and 13 --- VDD = 50V --- ID = 5.7A ns --- RG = 22 --- RD = 8.6, See Fig. 10 Between lead, 4.5 --- 6mm (0.25in.) nH G from package 7.5 --- and center of die contact 330 --- VGS = 0V 92 --- pF VDS = 25V 54 --- = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Min. Typ. Max. Units --- --- 9.7 --- --- 38 --- --- --- --- 99 390 1.3 150 580 A V ns nC Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = 5.7A, VGS = 0V TJ = 25C, IF = 5.7A di/dt = 100A/s Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25C, L = 4.7mH RG = 25, IAS = 5.7A. (See Figure 12) ISD 5.7A, di/dt 240A/s, VDD V(BR)DSS, TJ 175C Pulse width 300s; duty cycle 2%. D S IRF520NPbF 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I , Drain-to-Source Current (A) D I , Drain-to-Source Current (A) D 10 4.5V 20s PULSE WIDTH TC = 25C 1 0.1 1 10 A 10 4.5V 3.0 R DS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) TJ = 25C TJ = 175C V DS= 50V 20s PULSE WIDTH 5 6 7 8 9 10 100 A Fig 2. Typical Output Characteristics 100 1 1 VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 10 20s PULSE WIDTH TC = 175C 1 0.1 100 VDS , Drain-to-Source Voltage (V) 4 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP TOP 10 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics A I D = 9.5A 2.5 2.0 1.5 1.0 0.5 VGS = 10V 0.0 -60 -40 -20 0 20 40 60 A 80 100 120 140 160 180 TJ , Junction Temperature (C) Fig 4. Normalized On-Resistance Vs. Temperature IRF520NPbF 600 Ciss V GS , Gate-to-Source Voltage (V) 500 C, Capacitance (pF) 20 V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd I D = 5.7A 16 400 12 Coss 300 200 Crss 100 0 1 10 100 A 8 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 VDS , Drain-to-Source Voltage (V) 5 10 15 20 25 A Q G , Total Gate Charge (nC) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 100 100 OPERATION IN THIS AREA LIMITED BY R DS(on) 10s I D , Drain Current (A) ISD , Reverse Drain Current (A) VDS = 80V VDS = 50V VDS = 20V TJ = 175C 10 TJ = 25C VGS = 0V 1 0.4 0.6 0.8 1.0 1.2 VSD , Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage A 1.4 10 100s 1ms 1 10ms TC = 25C TJ = 175C Single Pulse 0.1 1 10 100 A 1000 VDS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area IRF520NPbF RD VDS 10.0 VGS D.U.T. RG + - VDD ID , Drain Current (A) 8.0 10V Pulse Width 1 s Duty Factor 0.1 % 6.0 Fig 10a. Switching Time Test Circuit 4.0 VDS 90% 2.0 0.0 25 50 75 100 125 150 TC , Case Temperature ( C) 10% VGS 175 td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Fig 9. Maximum Drain Current Vs. Case Temperature Thermal Response (Z thJC ) 10 D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 0.01 0.00001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 0.1 IRF520NPbF D.U.T. RG + V - DD IAS 10 V tp 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp VDD EAS , Single Pulse Avalanche Energy (mJ) L VDS 200 TOP BOTTOM 160 120 80 40 0 VDD = 25V 25 VDS ID 2.3A 4.0A 5.7A 50 75 100 125 A 150 175 Starting TJ , Junction Temperature (C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F 10 V QGS QGD D.U.T. VGS VG 3mA Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit + V - DS IRF520NPbF Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + RG * * * * Driver Gate Drive P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Period D= - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS ISD * IRF520NPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) 10.54 (.415) 10.29 (.405) 2.87 (.113) 2.62 (.103) -B- 3.78 (.149) 3.54 (.139) 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 6.47 (.255) 6.10 (.240) 4 15.24 (.600) 14.84 (.584) LEAD ASSIGNMENTS 1.15 (.045) MIN 1 2 3 4- DRAIN 14.09 (.555) 13.47 (.530) 4- COLLECTOR 4.06 (.160) 3.55 (.140) 3X 3X LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 2 - DRAIN 1- GATE 1- GATE 3 - SOURCE 2- COLLECTOR 2- DRAIN 3- SOURCE 3- EMITTER 4 - DRAIN HEXFET 1.40 (.055) 1.15 (.045) 0.93 (.037) 0.69 (.027) 0.36 (.014) 3X M B A M 0.55 (.022) 0.46 (.018) 2.92 (.115) 2.64 (.104) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 ASSEMBLED O N WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIO NAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.11/03 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/