HUF75339P3_NL - Fairchild Semiconductor

HUF75339G3, HUF75339P3, HUF75339S3S

75A, 55 V, 0.012 Ohm, N-Channel Ul traFET

Power MOSFETs

These N-Channel power MOSFETs

are manufactured using the

inno vat ive UltraFET ® process . This

advanced process technology

achieves the lowest possible on-resistance per silicon area,

resulting in outstandi ng p erformance. T his device is c apa ble

of withstanding high energy in the avalan ch e mode and the

diode exhibits very low rever se rec ov ery time and stor ed

charge. It was designed for use in applications where power

efficiency is important, such as switching regulators,

switching converters, motor drivers, relay drivers, low-

v oltage bus switches , and pow er manag em ent in port able

and battery-operated products.

Formerly developmental type TA75339.

Features

• 75A, 55V

• Simulation Models

- Temperature Compensated PSPICE® and SABER™

Models

- SPICE and SABER Thermal Impedance Models

A vailable on the WEB at: www.fairchildsemi.com

• Peak Current vs Pulse Wi dth Curve

• UIS Rating Curve

• Related Literature

- TB334, “G uid eli ne s for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

For severe environments, see our Autom otive HUFA series.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75339G3 TO-247 75339G

HUF75339P3 TO-220AB 75339P

HUF75339S3S TO-263AB 75339S

NOTE: When ordering, use the entire part number. Add the suffix T to

obtain the TO-263AB variant in tape and reel, e.g., HUF75339S3ST.

JEDEC STYLE TO-247 JEDEC TO-220AB

JEDEC TO -263AB

SOURCE

DRAIN

GATE

DRAIN

(TAB)

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

(FLANGE)

Data Sheet December 2001

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR 55 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 75

Figure 4 A

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 14, 15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

1.35 W

W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC

Maximum Temper ature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V

Zero Gate Vo ltage Drain C urrent IDSS VDS = 50V, VGS = 0V - - 1 µA

VDS = 45V, VGS = 0V, TC = 150oC--250µA

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V

Drain to Source On Resist ance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 0.010 0.012 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case RθJC (Figure 3) - - 0.74 oC/W

Thermal Resistance Junction to Ambient RθJA TO-247 - - 30 oC/W

TO-220, TO-263 - - 62 oC/W

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time tON VDD = 30V, ID ≅ 75A,

RL = 0.4Ω, VGS = 10V,

RGS = 5.1Ω

--110ns

Turn-On De lay Time td(ON) -15- ns

Rise Time tr-60- ns

Turn-Off De lay Time td(OFF) -20- ns

Fall Time tf-25- ns

Turn-Off T ime tOFF - - 70 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,

ID ≅ 75A,

RL = 0.4Ω

Ig(REF) = 1.0mA

(Figure 13)

- 110 130 nC

Gate Charge at 10V Qg(10) VGS = 0V to 10V - 60 75 nC

Threshold Gate Charge Qg(TH) VGS = 0 V to 2V - 3.7 4.5 nC

Gate to Source Gate C harge Qgs -9-nC

Reverse Transfer Capacitance Qgd -23-nC

HUF75339G3, HUF75339P3, HUF75339S3S

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V,

f = 1MHz

(Figure 12)

- 2000 - pF

Output Capacitance COSS - 700 - pF

Reverse Transfer Capacitance CRSS - 160 - pF

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to D rain Diode Volt age VSD ISD = 75A - - 1.25 V

Reverse Recovery Time trr ISD = 75A, dISD/dt = 100A/µs--85ns

Reverse Recovered Charge QRR ISD = 75A, dISD/dt = 100A/µs - - 160 nC

Typical Performance Curves

FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 150

0.2

0.4

0.6

0.8

1.0

1.2

125 17

, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

50 75 100 125 150 17

025

t, RECTANGULAR PULSE DURATION (s)

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

10-4 10-3 10-2 10-1 100101

10-5

0.1

0.01

ZθJC, NORMALIZED

THERMAL IMPEDANCE

HUF75339G3, HUF75339P3, HUF75339S3S

FIGURE 4. PEAK CURRENT CAPABILITY

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

FIGURE 7. SATURATION CHARA CTERISTICS FIGURE 8. TRANSFER CHARA C TERISTICS

Typical Performance Curves (Continued)

101

100

10-1

10-2

10-3

10-4

10-5

100

1000 TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 10V

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

100

500

10 100

1120

, DRAIN TO SOURCE VOLTAGE (V)

, DRAIN CURRENT (A)

= MAX RATED

= 25

100

10ms

1ms

DSS(MAX)

= 55V

LIMITED BY r

DS(ON)

AREA MAY BE

OP E RATION IN THIS

100

0.001 0.01 0.1 1 1

tAV = (L)(IAS)/(1.3*RATED B VDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*R ATED BVDSS - VDD) +1]

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

STARTING TJ = 150oC

500

120

150

0123

PULSE DURATION = 80µs

TC = 25oC

VGS = 5V

VGS = 6V

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

VGS = 10V

VGS = 20V

VGS = 7V

DUTY CYCLE = 0.5% MAX 0

120

150

0 1.5 3.0 4.5 6.0 7.

-55oC

175oC

VGS, GATE TO SO URCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

25oC

VDD = 15V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

HUF75339G3, HUF75339P3, HUF75339S3S

FIGURE 9. NORMALIZED DRAIN T O SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLT AGE vs

JUNCTION TEMPERATURE

FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE V OLTAGE

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Typical Performance Curves (Continued)

1.0

1.5

2.0

2.5

-40 0 40 80 120 160 200

0.5-80

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

PULSE DURATION = 80µs

VGS = 10V, ID = 75A

DUTY CYCLE = 0.5% MAX

0.8

1.0

1.2

-40 0 40 80 120 160 200

0.4-80

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VO LTAGE

VGS = VDS, ID = 250µA

0.6

1.0

1.1

1.2

-40 0 40 80 120 160 200

0.9-80

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

BREAKDOWN VOLTAGE

750

1500

2250

3000

3750

0 102030405060

C, CAPACITANCE (pF)

VDS, DRA IN TO SOURCE VOLTAGE (V)

COSS

CRSS

CISS

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

10 20 30 40 50 600

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 30V

Qg, GATE CHARGE (nC)

ID = 75A

ID = 56A

ID = 37.5A

ID = 18A

WAVEFORMS IN

DESCENDING ORDER:

HUF75339G3, HUF75339P3, HUF75339S3S

Test Circuits and Wa veforms

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

IG(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10)

VGS = 10V

Qg(TOT)

VGS = 20

VDS

VGS

g(REF)

Qgs Qgd

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

HUF75339G3, HUF75339P3, HUF75339S3S

PSPICE Ele ctrical Model

.SUBCKT HUF75339 2 1 3 ; rev 23 February 1999

CA 12 8 2.80e-9

CB 15 14 2.80e-9

CIN 6 8 1.77e-9

DBODY 7 5 DBODYMOD

DBRE AK 5 11 D B REAK MOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 59.2

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTH R ES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRA IN 2 5 1.0e - 9

LGATE 1 9 2.0e-9

LSOURCE 3 7 4.7e-10

K1 LSO URCE LGATE 0.0302

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 1.95e-3

RGATE 9 20 0.34

RLDRAIN 2 5 10

RLGATE 1 9 20

RLSOURCE 3 7 4.7

RSLC1 5 51 RSLCMOD 1.0e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 6.0e-3

RVTHRES 22 8 RVTHRESMOD 1

RVTE M P 18 19 RVTEMPM O D 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMO D

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2B MOD

VBAT 22 1 9 DC 1

ESL C 51 50 VALUE= {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*230),4))}

.MODEL DBOD YMOD D (IS = 3.5e-12 R S = 3.02 e-3 N = 1.0 2 XTI = 5.5 TRS1 = 3.0e-3 TRS2 = 4.0 e-6 CJO = 2.9e-9 TT = 4.35e-8 M = 0 .5)

.MODEL DBREAKMOD D (RS = 8.5e-2 TRS1 = 8.0e- 4TRS2 = 1.0e-7)

.MODEL DPLCA PMOD D (CJO = 2.25e- 9IS = 1e-30 M = 0.8 )

.MODEL MMEDMOD NMOS (VTO = 3.1 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG=0.34)

.MODEL MSTROMOD NMOS (VTO = 3.73 KP = 86.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODE L M WEAKMOD NMOS ( V TO = 2.7 KP = 0.01 IS = 1e-30 N = 1 0 T OX = 1 L = 1u W = 1u RG=3.4)

.MODE L RB REAKM OD RE S (TC1 = 1.08e- 3TC 2 = -2.5e-7)

.MODEL RDRAINMOD RES (TC1 = 2.05e-2 TC2 = 1.6e-5)

.MODEL RSLCMOD RES (TC1 = 6.0e-3 TC2 = -2.8e-6)

.MODEL RSOURCEM OD RES (TC1 = 5.5e-4 TC2 = 1 .75e-5)

.MODEL RVTHRESMOD RES (TC1 = -3.65e-3 TC2 = -6.0e-6)

.MODEL RVTEMPMOD RES (TC1 = -2.3e- 3TC2 = -4.0e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -9 VOFF= -5.5)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -9)

.MODEL S2A MOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOF F= 2.1)

.MODEL S2B MOD VSWITCH (RON = 1 e-5 ROFF = 0.1 VON = 2.1 VOFF = 0 )

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PS PI CE Sub-C ircuit for the Power M OSFET Featurin g Glob al

Temperature Options; IEEE Power El ectronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF75339G3, HUF75339P3, HUF75339S3S

SABER Electrical Model

REV 23 February 1999

template huf75339 n2, n1, n3

electrical n2, n1, n3

{

var i iscl

d..model dbodymod = (is = 3.5e-12, n = 1.02, xti = 5.5, cjo = 2.9e-9, tt = 4.35e-8, m = 0.5)

d..model dbreakmod = ()

d..model dplcapmod = (cjo = 2.25e-9, is = 1e-30, n = 10, m = 0.8 )

m..model mmedmod = (type=_n, vto = 3.1, kp = 1.5, is = 1e-30, tox = 1)

m..model mstrongmod = (type=_n, vto = 3.73, kp = 86.5, is = 1e-30, tox = 1)

m..model mweakmod = (type=_n, vto = 2.7, kp = 0.01, is = 1e-30, tox = 1)

sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -9, voff = -5.5)

sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -9)

sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 2.1)

sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.1, voff = 0)

c.ca n12 n8 = 2.8e-9

c.cb n15 n14 = 2.8e-9

c.cin n6 n8 = 1.77e-9

d.dbody n7 n71 = model=dbodymod

d.dbreak n72 n11 = model=dbreakmod

d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1.0e-9

l.lgate n1 n9 = 2.0e-9

l.lsourc e n3 n7 = 4.7e-10

k.kl i (l.lgate) i (l.lsource) = l(l.lgate), l(l.lsource), 0.0302

m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u

res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = -2.5e-7

res.rdbody n71 n5 = 3.02e-3, tc1 = 3.0e-3, tc2 = 4.0e-6

res.rdbreak n72 n5 = 8.5e-2, tc1 = 8.0e-4 , tc2 = 1.0e-7

res.rdrain n50 n16 = 1.95e-3, tc1 = 2.05e-2, tc2 = 1.6e-5

res.rgate n9 n20 = 0.34

res.r ldrain n2 n5 = 10

res. rl g ate n1 n9 = 20

res.rlsource n3 n7 = 4.7

res.rslc1 n5 n51 = 1e-6, tc1 = 6.0e-3, tc2 = -2.8e-6

res.r slc2 n5 n50 = 1e3

res.rsour ce n8 n7 = 6e-3, tc1 = 5.5e-4, t c 2 = 1.75e-5

res.rvtemp n18 n19 = 1, tc1 = -2.3e-3, tc2 = -4.0e-6

res.rvthres n22 n8 = 1, tc1 = -3.65e-3, tc2 = -6.0e-6

spe.ebreak n11 n7 n17 n18 = 59.2

spe.e ds n14 n8 n5 n8 = 1

spe.e gs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc = 1

equations {

i (n51->n50) + = iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n 51))))*((abs(v(n5, n51)*1e6/230))** 4.0))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURC

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RDBODY

RDBREAK

HUF75339G3, HUF75339P3, HUF75339S3S

SPICE Thermal Model

REV 11 February 1999

HUF75339

CTHERM1 th 6 5.00e-3

CTHERM2 6 5 1 .90e-2

CTHERM3 5 4 7 .95e-3

CTHERM4 4 3 9 .00e-3

CTHERM5 3 2 2 .95e-2

CTHERM6 2 tl 12.55

RTHERM1 th 6 5.04e-3

RTHERM2 6 5 1 .25e-2

RTHERM3 5 4 3 .54e-2

RTHERM4 4 3 1 .98e-1

RTHERM5 3 2 2 .99e-1

RTHERM6 2 tl 3.97e-2

SABER Thermal Model

SABER thermal model HUF75339

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm 1 t h 6 = 5.00e-3

ctherm.ctherm 2 6 5 = 1.90e-2

ctherm.ctherm 3 5 4 = 7.95e-3

ctherm.ctherm 4 4 3 = 9.00e-3

ctherm.ctherm 5 3 2 = 2.95e-2

ctherm.ctherm6 2 tl = 12.55

rtherm.rtherm1 th 6 = 5.04e-3

rtherm.rtherm2 6 5 = 1.25e-2

rtherm.rtherm3 5 4 = 3.54e-2

rtherm.rtherm4 4 3 = 1.98e-1

rtherm.rtherm5 3 2 = 2.99e-1

rtherm.rtherm6 2 t l = 3.97e- 2

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

HUF75339G3, HUF75339P3, HUF75339S3S

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIG HT TO MAKE C HANGES WITHOUT FURTHER NOTICE TO AN Y PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY AR ISING OUT O F THE

APPLICATION OR USE O F ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICEN SE UNDER ITS

PATENT RIGH TS, NOR THE R IGHTS OF OTH ERS. THESE SPECIFIC ATIONS DO N OT EX PAND THE TER MS OF FAIRCHILD’S

WORLD WIDE TERMS AN D CON DITIONS, SPECIFIC ALLY THE WARRANTY THER EIN, WHICH COVERS TH ESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EX PRESS WRITTEN APPROVAL O F FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result i n a signifi cant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to c ause the failure of t he life support

device or system , or to aff ect it s safety or effec tiveness.

PRODUCT STATUS DEFINITI ONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Format i ve or I n Design This datasheet cont ai ns the desi gn specifi cations for product

development. Spec i ficat i ons may change in any m anner without notice.

Preliminary First Production

This datasheet contains preliminary data; s upplementary data will be

published at a l ater date. Fairchild Semiconductor reserves the right t o

mak e changes at any tim e without notice t o i mprove desi gn.

No Identif i cation Needed Full Production This datasheet cont ai ns final s pecifications. Fairchil d S emic onductor

reserves t he ri ght to make changes at any ti me without not i ce to improve

the design.

Obsolete Not In Production This datasheet contains speci ficati ons on a product that has been

discontinued by Fairchil d Semi conductor. The datasheet is printed f or

reference information only.

Rev. I32