1
FEATURES
WPACKAGE
(TOP VIEW)
SN55LVDS33W
DESCRIPTION/ORDERING INFORMATION
SN55LVDS33-SP
SGLS393 – MARCH 2008www.ti.com
HIGH-SPEED DIFFERENTIAL RECEIVER
•400-Mbps Signaling Rate and 200-Mxfr/s DataTransfer Rate
(1)
•Operates With a Single 3.3-V Supply•– 4 V to 5 V Common-Mode Input VoltageRange
•Differential Input Thresholds < ± 50 mV With50 mV of Hysteresis Over EntireCommon-Mode Input Voltage Range•Complies With TIA/EIA-644 (LVDS)•Active Failsafe Assures a High-Level OutputWith No Input•Bus-Pin ESD Protection Exceeds 15-kV HBM•Input Remains High-Impedance On PowerDown
•TTL Inputs Are 5-V Tolerant•Pin-Compatible With the AM26LS32,SN65LVDS32B, µA9637, SN65LVDS9637B•QML-V Qualified, SMD 5962-07248•Military Temperature Range ( – 55 °C to 125 °C)(1) The signaling rate of a line is the number of voltagetransitions that are made per second expressed in the unitsbps (bits per second).
These LVDS data line receivers offers the widest common-mode input voltage range in the industry. Thesereceivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overallincreased ground-noise tolerance. They are in industry standard footprints with integrated termination as anoption.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresisto improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mVover the full input common-mode voltage range.
The receivers can withstand ± 15-kV Human-Body Model (HBM) and ± 600-V Machine Model (MM) electrostaticdischarges to the receiver input pins with respect to ground without damage. This provides reliability in cabledand other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns afterloss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, orpowered-down transmitters. The failsafe circuit prevents noise from being received as valid data under thesefault conditions. This feature may also be used for wired-OR bus signaling. See The Active Failsafe Feature ofthe SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmissionover controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit boardtraces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuationcharacteristics of the media and the noise coupling to the environment.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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SN55LVDS33-SP
SGLS393 – MARCH 2008
The SN55LVDS33 is characterized for operation from – 55 °C to 125 °C.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
– 55 °C to 125 °C CFP - W Tube 5962-0724801VFA 5962-0724801VFA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
FUNCTION TABLE
(1)
SN55LVDS33
DIFFERENTIAL INPUT ENABLES OUTPUT
V
ID
= V
A
– V
B
G G Y
H X HV
ID
≥– 32 mV
X L HH X ?– 100 mV < V
ID
≤– 32 mV
X L ?H X LV
ID
≤– 100 mV
X L LX L H ZH X HOpen
X L H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
37 Ω
7 V
Y Output
7 V
300 kΩ
100 Ω
VCC
Enable
Inputs
300 kΩ
(G Only)
(G Only)
7 V
VCC
Attenuation
Network
A Input
Attenuation
Network
B Input
7 V7 V
7 V
6.5 kΩ6.5 kΩ
VCC
Attenuation
Network
60 kΩ
250 kΩ
200 kΩ
1 pF
3 pF
SN55LVDS33-SP
SGLS393 – MARCH 2008
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
SN55LVDS33-SP
SGLS393 – MARCH 2008
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Supply voltage range, V
CC
(2)
– 0.5 V to +4 VEnables or Y – 1 V to +6 VVoltage range
A or B – 5 V to +6 VElectrostatic discharge A, B, and GND
(3)
Class 3, A: 15 kV, B: 500 VCharged-device mode All pins
(4)
± 500 VStorage temperature range – 65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage Enables 2 5 VV
IL
Low-level input voltage Enables 0 0.8 V|V
ID
| Magnitude of differential input voltage 0.1 3 VV
I
or V
IC
Voltage at any bus terminal (separately or common-mode) – 4 5
°CT
A
Operating free-air temperature – 55 125
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ELECTRICAL CHARACTERISTICS
SN55LVDS33-SP
SGLS393 – MARCH 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT1
Positive-going differential input voltage threshold
(2)
50V
IB
= – 4 V or 5 V, See Figure 2 mVV
IT2
Negative-going differential input voltage – 50threshold
(2)
V
IT3
Differential input failsafe voltage threshold
(2)
See Table 1 and Figure 5 – 32 – 100 mV
Differential input voltage hysteresis,V
ID(HYS)
50 VV
IT1
– V
IT2
V
OH
High-level output voltage I
OH
= – 4 mA 2.4 V
V
OL
Low-level output voltage I
OL
= 4 mA 0.4 V
G at V
CC
, No load, Steady state 16 25I
CC
Supply current mAG at GND 1.1 6
V
I
= 0 V, Other input open ± 25
V
I
= 2.4 V, Other input open ± 25Input currentI
I
µA(A or B inputs)
V
I
= – 4 V, Other input open ± 80
V
I
= 5 V, Other input open ± 45
I
IO
Differential input current (I
IA
– I
IB
) V
ID
= 100 mV, V
IC
= – 4 V or 5 V ± 5 µA
V
A
or V
B
= 0 V or 2.4 V, V
CC
= 0 V ± 25I
I(OFF)
Power-off input current (A or B inputs) µAV
A
or V
B
= – 4 or 5 V, V
CC
= 0 V ± 60
I
IH
High-level input current (enables) V
IH
= 2 V 12 µA
I
IL
Low-level input current (enables) V
IL
= 0.8 V 12 µA
I
OZ
High-impedance output current – 10 12 µA
C
I
Input capacitance, A or B input to GND V
I
= 0.4 sin (4E6 πt) + 0.5 V 5 pF
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) Not production tested but guaranteed to the limit.
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SWITCHING CHARACTERISTICS
VID
A
B
Y
VO
VIB
VIA
VIC
(VIA + VIB)/2 IIB
IIA VO
SN55LVDS33-SP
SGLS393 – MARCH 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH(1)
Propagation delay time, low-to-high level output 1.8 4 8 nsSee Figure 3t
PHL(1)
Propagation delay time, high-to-low level output 1.8 4 8 nst
d1
Delay time, failsafe deactivate time
(2)
11 nsC
L
= 10 pF,See Figure 3 and Figure 6t
d2
Delay time, failsafe activate time
(2)
0.2 2 µst
sk(p)
Pulse skew (|t
PHL(1)
– t
PLH(1)
|) 200 pst
sk(o)
Output skew
(3)
150 pst
sk(pp)
Part-to-part skew
(4)
See Figure 3 1.2 nst
r
Output signal rise time 0.8 nst
f
Output signal fall time 0.8 nst
PHZ
Propagation delay time, high level-to-high impedance output 5.5 12 nst
PLZ
Propagation delay time, low level-to-high impedance output 4.4 12 nsSee Figure 4t
PZH
Propagation delay time, high impedance-to-high level output 3.8 12 nst
PZL
Propagation delay time, high impedance-to-low level output 7 12 ns
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) Not production tested but guaranteed to the limit.(3) t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all receivers of a single device with all of their inputs driventogether.
(4) t
sk(pp)
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when bothdevices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Figure 1. Voltage and Current Definitions
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VID
VO
10 pF,
2 Places 10 pF
100 Ω
1000 Ω
1000 Ω
100 Ω
VIC
VID
VO
VID
VO
VIT1
0 V
−100 mV
100 mV
0 V
VIT2
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
+
−
SN55LVDS33-SP
SGLS393 – MARCH 2008
Figure 2. V
IT1
and V
IT2
Input Voltage Threshold Test Circuit and Definitions
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VID
VO
VIB
VIA CL = 10 pF
tPHL tPLH
tftr
80%
20%
80%
20%
VIA
VIB
VID
VO
1.4 V
1 V
0.4 V
0 V
−0.4 V
VOH
1.4 V
VOL
SN55LVDS33-SP
SGLS393 – MARCH 2008
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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B
A
G
G
VO±
500 Ω
VTEST
10 pF
1.2 V
tPZL
tPLZ
tPZL
tPLZ
tPZH
tPHZ
tPZH
tPHZ
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL +0.5 V
VOL
0
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
VOH
VOH −0.5 V
1.4 V
0
VTEST
A
G
G
Y
VTEST
A
G
Y
Inputs
G
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
SN55LVDS33-SP
SGLS393 – MARCH 2008
Figure 4. Enable/Disable Time Test Circuit and Waveforms
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VIA
VIB
VO
−100 mV @ 250 KHz
a) No Failsafe
−32 mV @ 250 KHz
Failsafe Asserted
VIA
VIB
VO
b) Failsafe Asserted
SN55LVDS33-SP
SGLS393 – MARCH 2008
Table 1. Receiver Minimum and Maximum V
IT3
Input Threshold Test Voltages
APPLIED VOLTAGES
(1)
RESULTANT INPUTS
V
IA
(mV) V
IB
(mV) V
ID
(mV) V
IC
(mV) Output
– 4000 – 3900 – 100 – 3950 L– 4000 – 3968 – 32 – 3984 H4900 5000 – 100 4950 L4968 5000 – 32 4984 H
(1) These voltages are applied for a minimum of 1.5 µs.
Figure 5. V
IT3
Failsafe Threshold Test
Figure 6. Waveforms for Failsafe Activate and Deactivate
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TYPICAL CHARACTERISTICS
0IOL − Low-Level Output Current − mA
4
3
020 30
2
10
VCC = 3.3 V
TA = 25°C
1
VOL − Low-Level Output Voltage − V
5
40
IOH − High-Level Output Current − mA
VOH− High-Level Output Voltage − V
4
3
0
2
1
−30 −20−40 0−10
VCC = 3.3 V
TA = 25°C
4.5
4
3.5
3
−50 0 50
5
100
TA − Free-Air Temperature − °C
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
− Low-To-High Propagation Delay Time − ns
tPLH
4.5
4
3.5
3
−50 0 50
5
100
TA − Free-Air Temperature − °C
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
− High-To-Low Propagation Delay Time − ns
tPHL
SN55LVDS33-SP
SGLS393 – MARCH 2008
LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 7. Figure 8.
LOW-TO-HIGH PROPAGATION DELAY TIME HIGH-TO-LOW PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
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80
60
20
00 100
100
120
150 200
40
− Supply Current − mAICC
f − Switching Frequency − MHz
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
140
SN55LVDS33-SP
SGLS393 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vsFREQUENCY
Figure 11.
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APPLICATION INFORMATION
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100 Ω
100 Ω
100 Ω
(see Note B)
100 Ω
VCC
See Note C
≈3.6 V
0.1 µF
(see Note A) 1N645
(2 places)
0.01 µF
5 V
RELATED INFORMATION
SN55LVDS33-SP
SGLS393 – MARCH 2008
A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
CC
and the groundplane. The capacitor should be located as close as possible to the device terminals.B. The termination resistance value should match the nominal characteristic impedance of the transmission media with± 10%.C. Unused enable inputs should be tied to V
CC
or GND as appropriate.
Figure 12. Operation With 5-V Supply
IBIS modeling is available for this device. Contact the local Texas Instruments sales office or the TexasInstruments Web site at www.ti.com for more information.
For more application guidelines, see the following documents:•Low-Voltage Differential Signalling Design Notes (SLLA014 )•Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038 )•Reducing EMI With LVDS (SLLA030 )•Slew Rate Control of LVDS Circuits (SLLA034 )•Using an LVDS Receiver With RS-422 Data (SLLA031 )•Evaluating the LVDS EVM (SLLA033 )
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ACTIVE FAILSAFE FEATURE
_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
BR
SN55LVDS33-SP
SGLS393 – MARCH 2008
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. CurrentLVDS failsafe solutions require either external components with subsequent reductions in signal quality orintegrated solutions with limited application. This family of receivers has a new integrated failsafe that solves thelimitations seen in present solutions. A detailed theory of operation is presented in application note, The ActiveFailsafe Feature of the SN65LVDS32B (SLLA082A ).
Figure 13 shows one receiver channel with active failsafe. It consists of a main receiver that can respond to ahigh-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a windowcomparator. The window comparator has a much slower response than the main receiver and it detects when theinput differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator outputs. When failsafeis asserted, the failsafe logic drives the main receiver output to logic high.
Figure 13. Receiver With Active Failsafe
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ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
R3 R3
VCCICC
5 Meters
of CAT-5
R1 R1
VEE R2
VCCICC
R3 = 240 Ω
R1 = 50 Ω
R2 = 50 Ω
VB
VBLVDSLV/PECL
SN55LVDS33-SP
SGLS393 – MARCH 2008
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer ofchoice for system designers. Designers know of the established technology and that it is capable of high-speeddata transmission. In the past, system requirements often forced the selection of ECL. Now technologies likeLVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a designoption, designers have been able to take advantage of LVDS by implementing a small resistor divider network atthe input of the LVDS receiver. Texas Instruments has taken the next step by introducing a wide common-modeLVDS receiver (no divider network required) which can be connected directly to an ECL driver with only thetermination bias voltage required for ECL termination (V
CC
– 2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving five meters of CAT-5 cable and beingreceived by Texas Instruments wide common-mode receiver and the resulting eye-pattern. The values for R3 arerequired in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simplyneeds to match the characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended tominimize any possible common-mode current reflections.
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1)
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TEST CONDITIONS
EQUIPMENT
Tektronix PS25216
Programmable
Power Supply
Bench Test Board
Tektronix HFS 9003
Stimulus System
Tektronix TDS 784D 4-Channel
Digital Phosphor Oscilloscope
− DPO
Trigger
100 Mbit/s 200 Mbit/s
SN55LVDS33-SP
SGLS393 – MARCH 2008
•V
CC
= 3.3 V•T
A
= 25 °C (ambient temperature)•All four channels switching simultaneously with NRZ data. The scope is pulse-triggered simultaneously withNRZ data.
•Tektronix PS25216 programmable power supply•Tektronix HFS 9003 stimulus system•Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Figure 16. Equipment Setup
Figure 17. Typical Eye Pattern SN65LVDS33
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-0724801VFA ACTIVE CFP W 16 1 TBD A42 SNPB N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
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