© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 6
1Publication Order Number:
MC14557B/D
MC14557B
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability.
The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.
•1−64 Bit Programmable Length
•Q and Q Serial Buffered Outputs
•Asynchronous Master Reset
•All Inputs Buffered
•No Limit On Clock Rise and Fall Times
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−power TTL Loads or one Low−power
Schottky TTL Load Over the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10 mA
PDPower Dissipation,
per Package (Note 2)
500 mW
TAAmbient Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
TLLead Temperature
(8−Second Soldering)
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/°C From 65°C To 125°C
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SO−16 WB
DW SUFFIX
CASE 751G
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14557B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
16
1
MC14557BCP
AWLYYWWG
16
1
1
16
1
14557B
AWLYYWWG
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MC14557B
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2
Figure 1. Logic Diagram
A/B
SELECT
B
A
RESET
CLOCK
CE
9
6
7
3
4
5
CR
32 BIT
12
L32
CR
2 BIT
1
L2
2
L1
CR
1 BIT
CR
16 BIT
13
L16
14
L8
CR
1 BIT
CR
8 BIT
10
11
Q
Q
15
L4
CR
4 BIT
VDD= PIN 16
VSS = PIN 8
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Figure 2. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
L32
L16
L8
L4
VDD
A/B SEL
Q
Q
CLOCK
RESET
L1
L2
VSS
A
B
CE
Figure 3. Block Diagram
12
13
14
1
15
2
9
7
6
5
4
3
11
10
RESET
CLOCK
CE
B
A
A/B SELECT
L1
L2
L4
L8
L16
L32
Q
Q
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs Output
Rst A/B Clock CE Q
0 0 0 B
0 1 0 A
0 0 1 B
0 1 1 A
1 X X X 0
Q is the output of the first selected shift
register stage.
X = Don’t Care
LENGTH SELECT TRUTH TABLE
L32 L16 L8 L4 L2 L1 Register Length
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1 Bit
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
33 Bits
34 Bits
61 Bits
62 Bits
63 Bits
64 Bits
NOTE: Length equals the sum of the binary length control
subscripts plus one.
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4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Symbol Characteristic
VDD
Vdc
− 55°C 25°C 125°C
Unit
Min Max Min
Typ
(Note 3) Max Min Max
VOL Output Voltage “0” Level
Vin = VDD or 0
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH “1” Level
Vin = 0 or VDD
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
VIL Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH “1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
IOH Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
mAdc
IOL (VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
Iin Input Current 15 −±0.1 −±0.00001 ±0.1 −±1.0 mAdc
Cin Input Capacitance
(Vin = 0)
− − − − 5.0 7.5 − − pF
IDD Quiescent Current
(Per Package)
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.010
0.020
0.030
5.0
10
20
−
−
−
150
300
600
mAdc
ITTotal Supply Current (Notes 4, 5)
(Dynamic plus Quiescent, Per Package)
(CL = 50 pF on all outputs, all buffers switching)
5.0
10
15
IT = (1.75 mA/kHz) f + IDD
IT = (3.50 mA/kHz) f + IDD
IT = (5.25 mA/kHz) f + IDD
mAdc
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25°C.
5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25°C)
Symbol Characteristic VDD Min
Typ
(Note 7) Max Unit
tTLH,
tTHL
Rise and Fall Time, Q or Q Output
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
5
10
15
−
−
−
100
50
40
200
100
80
ns
tPLH,
tPHL
Propagation Delay, Clock or CE to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
5
10
15
−
−
−
300
130
90
600
260
180
ns
tPLH,
tPHL
Propagation Delay, Reset to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns
5
10
15
−
−
−
300
130
95
600
260
190
ns
tWH(cl) Pulse Width, Clock 5
10
15
200
100
75
95
45
35
−
−
−
ns
tWH(rst) Pulse Width, Reset 5
10
15
300
140
100
150
70
50
−
−
−
ns
fcl Clock Frequency (50% Duty Cycle) 5
10
15
−
−
−
3.0
7.5
13.0
1.7
5.0
6.7
MHz
tsu Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
5
10
15
700
290
145
350
130
85
−
−
−
ns
Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
10
15
400
165
60
45
5
0
−
−
−
thHold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
5
10
15
200
100
10
–150
–60
–50
−
−
−
ns
Worst case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
10
15
400
185
85
50
25
22
−
−
−
tr,
tf
Rise and Fall Time, Clock 5
10
15
No Limit
−
tr,
tf
Rise and Fall Time, Reset or CE 5
10
15
−
−
−
−
−
−
15
5
4
ms
trem Removal Time, Reset to Clock or CE 5
10
15
160
80
70
80
40
35
−
−
−
ns
6. The formulas given are for the typical characteristics only at 25°C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14557B
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6
Figure 4. Timing Diagram
1−bit length:
CE = 0
A/B = 1
L1 = L2 = L4 = L8 = L16 = L32 = 0
PWR
50%
tWH(cl)
th
50%
tsu
trem
50%
tTLH tTHL
tPHL
tPHL
tPLH
90%
50%
10%
A INPUT
CLOCK
RESET
Q
VDD
VSS
VDD
VSS
VDD
VSS
VOH
VOL
1/fcl
ORDERING INFORMATION
Device Package Shipping†
MC14557BFELG SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
MC14557BDWR2G SO−16 (WB) 1000 / Tape & Reel
MC14557BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MC14557BDWG SO−16 (WB) 47 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC14557B
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7
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
SO−16 WB
DW SUFFIX
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
MC14557B
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8
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC14557B/D
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