User's GuideSLVU197B – March 2007 – Revised September 2007
TPS2376HEVM
This user’s guide describes the characteristics, operation, and use of the TPS2376HEVM, demonstratinghigh-power, Power-over-Ethernet (PoE). Typical PoE applications consist of two parts:•Power Sourcing Equipment (PSE) that injects power into the Ethernet Category 5 (CAT5) cable and•Powered Devices (PD) that connect to the CAT5 cable to receive power.
This evaluation board demonstrates a complete PD solution including detection, classification, and currentlimiting required for many PoE applications and delivers an isolated 5 V at 5 A to the load.
The theory and general application of PoE is beyond the scope of this User’s Guide, so for a broaderdescription see the application material listed in the Related Materials from Texas Instruments section.This User’s Guide includes setup instructions, a schematic diagram, a bill of materials (BOM) andPCB-layout drawings for the TPS2376HEVM.
Contents1 Related Documentation From Texas Instruments ....................................................................... 22 Introduction ................................................................................................................... 23 Setup .......................................................................................................................... 24 Board Layout ................................................................................................................. 75 Bill of Materials and Schematics ......................................................................................... 10
List of Figures
1 5-V Output Startup Waveform .............................................................................................. 42 TP13 Waveform, 5-V Output Ripple Voltage ............................................................................. 43 Efficiency ...................................................................................................................... 54 Booster Circuit Current Distribution ....................................................................................... 55 Loop Gain and Phase Margin .............................................................................................. 66 Top-Side Layout ............................................................................................................. 77 Bottom-Side Layout.......................................................................................................... 8
List of Tables
1 Bill of Materials ............................................................................................................. 10
PowerPAD is a trademark of Texas Instruments.
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1 Related Documentation From Texas Instruments
2 Introduction
3 Setup
3.1 Input / Output Connector Descriptions
3.1.1 J1 – Data Port Output
Related Documentation From Texas Instruments
•TPS2376-H data sheet (SLVS646 )•UCC3809-2 data sheet (SLUS166 )•TPS2375 data sheet (SLVS525 )•TPS2384 data sheet (SLUS634 )•Application report, High Power PoE Using TPS2375/77-1 (SLVA225 )•Application report, Achieving High Efficiency with a Multi-Output CCM Flyback Supply UsingSelf-Driven Synchronous Rectifiers (SLUP204 )•Application report, Reference Design: Isolated 50W Flyback Converter Using the UCC3809 PrimarySide Controller (SLUU096 ).
Traditionally, PoE has followed the standard IEEE 802.3af for specifying PD design and performance thatincludes a maximum power allotment of 15.4 W per port by the PSE. Due to resistive losses in the CAT5cable, the effective power to the PD input is limited to approximately 13 W. Additionally, most applicationsrequire a power supply after the PD input that further reduces the system efficiency and limits actualpower to the load to approximately 11 W. As the drive for more complex end equipment increases, manyend equipment types requires more power than the IEEE 802.3af standard allows. This evaluation boarddemonstrates how a PD can deliver up to 25 W to the load, and can be interfaced to any PSE that followsdetection and classification procedures defined by the IEEE 802.3af standard. For details on PDoperation, read the Application Information section in the datasheet for the TPS2375, IEEE 802.3af PoEPowered Device Controllers (SLVS525 ). For details on PSE operation, read the Application Informationsection in the data sheet for the TPS2384, Quad Integrated Power Sourcing Equipment Power Manager(SLUS634 ).
Note that from a system-level perspective, the amount of power that can be delivered to the load isdependent on both the PD and PSE. This evaluation board is intended to demonstrate how a PD candeliver 25 W to the load. Because this PD evaluation board is intended for power levels greater than whatthe IEEE 802.3af specification allows, a PSE designed to meet only the IEEE 802.3af standard will not beable to source enough power, because it will go into current limit once the port current goes higher than350 mA. For additional details, read the application report, High Power PoE Using TPS2375/77-1(SLVA225 ).
The DC/DC power supply used in this evaluation board uses a Continuous Conduction ModeSynchronous Flyback topology using the UCC3809-2 Economy Primary Side Controller. For details on thistopology, see the application reports, Achieving High Efficiency with a Multi-Output CCM Flyback SupplyUsing Self-Driven Synchronous Rectifiers (SLUP204 ) and, Reference Design: Isolated 50 W FlybackConverter Using the UCC3809 Primary Side Controller (SLUU096 ). For details on the UCC3809, see thedata sheet (SLUS166 ).
This section describes the jumpers and connectors on the TPS2376HEVM EVM as well as how toproperly connect, setup, and use TPS2376HEVM.
J1 is the RJ-45 adapter jack for the Data Port output for Ethernet data transmission. CAT5 cable can beconnected here to transmit Gigabit Ethernet data; however, this is beyond the scope of this referencedesign and does not have any bearing on the PoE functionality. For PoE operation, J1 is not used.
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3.1.2 J2 – Ethernet Power
3.1.3 J3 – DC/DC Input Power
3.1.4 J4 – 5V Output Power
3.1.5 J5 – Powered-Device DC/DC Disconnect
3.2 Electrical Specifications
Setup
J2 is the RJ-45 adapter jack for connecting Ethernet Power to the evaluation board. Plug in the CAT5cable from the PSE here to deliver power to the board. Only apply power to either J3 or J4 at one time;never apply power at both J3 and J4 at the same time. When applying power at J2, place the shortingjumper on J5 for proper operation.
In some cases it is beneficial to test the DC/DC power supply without using the front-end PD. J3 is thepower connector used when testing the DC/DC power supply without the front-end PD functionality. Apply+48 V to the TP1 side of the header, and connect the return GND path to the TP2 side. Only apply powerto either J3 or J4 at one time; never apply power at both J3 and J4 at the same time. While applyingpower at J3, remove the shorting jumper on J5 to ensure proper functionality.
J4 is the 5-V output of the DC/DC power supply. Connect a load between the two terminals of this header.The positive polarity is closest to TP5, and the negative polarity is closest to TP9.
This jumper connects the PG output of the TPS2376-H to the timing capacitor of the UCC3809-2. Holdingthis node low disables the UCC3809-2 and prevents the 5-V output from turning on. When applying powerat J2 and testing the PD functionality of this board, place the shorting jumper on J5 so that the powersupply is disabled until the PG signal of the TPS2376-H is released. When applying power at J3 andtesting only the DC/DC power supply without PD functionality, remove this shorting jumper.
PARAMETER CONDITION MIN TYP MAX UNIT
POWER INTERFACE
Input voltage, V
IN
Applied to the power pins of connectors J2 or J3 0 57 VOperating voltage After startup 41 57 VRising input voltage 40.5 VInput UVLO
Falling input voltage 29 VDetection voltage 1.4 10.1 VClassification voltage 10.2 23 VClassification current 2.2 2.4 2.8 mA
DC/DC CONVERTER
Output voltage 41 V < V
IN
< 57 V, Up to full load 4.75 5 5.25 VOutput current 41 V < V
IN
< 57 V 5 AOutput ripple voltage, peak-to-peak V
IN
= 48 V, Load = 5 A 50 mVEfficiency, end-to-end V
IN
= 48 V, Load = 3 A 83%Switching frequency 270 330 kHz
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3.3 Test Results
Setup
The test results for this EVM at T
A
= 25 °C follow.
Figure 1 shows the 5-V output startup waveform at J4 (Bottom, 2 V/div) after the application of 48 Vdc atJ3 (Top, 20 V/div). The output at J4 was loaded to 0 A (500 ms / div).
Figure 1. 5-V Output Startup Waveform
The waveform at TP13 on the drain of the primary side FET (Top, 50 V/div) and the 5 V output ripplevoltage at J4 (Bottom, 50 mV/div) are shown in the figures below. The images were taken with the outputloaded to 5 A at J4 and the input voltage set to 48 Vdc at J3 (2 μs/div).
Figure 2. TP13 Waveform, 5-V Output Ripple Voltage
The converter efficiency and regulation over load are shown in Figure 3 . Two conditions are shown; 1) 48V is applied at J2 and 2) 48 V is applied at J3.
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60
65
70
75
80
85
90
95
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
I -OutputCurrent- A
O
Efficiency-%
J2,(RJ-45)
J3(Flyback)
V =48V
I
RJ-45=48V
0
0.1
0.2
0.3
0.4
0.5
0.6
0 5 10 15 20 25 30
PowertoLoad-W
Current- A
R15Current
R19Current
Setup
Figure 3. Efficiency
To avoid current limiting at the TPS2376-H PD, a current booster circuit composed of Q1, Q2, R15, andR19 is used to create a secondary return path for the input current. Figure 4 shows the current distributionbetween the two paths. Detailed explanation on this circuit is provided in the TI application report,High-Power PoE Using TPS2375/77-1 (SLVA225 ).
Figure 4. Booster Circuit Current Distribution
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1SideBar:
3.187kFrequency(Hz)
0Gain(dB)
75.33Phase(deg)
-0.991Slope(20dB/decade)
Setup
Figure 5 shows the loop gain and phase margin with input voltage set to 48 V at J3. The output wasloaded to 5 A at J4. Bandwidth ≈3.19 kHz, Phase Margin ≈75.3 °.
Figure 5. Loop Gain and Phase Margin
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4.2 Layout Considerations
Board Layout
The layout of the PoE front end must use good practices for power and EMI/ESD. A basic set ofrecommendations include:•The parts placement must be arranged by the power flow in a point-to-point manner such as RJ-45 →Ethernet transformer →diode bridges →TVS and 0.1- μF capacitor →TPS2376-H →bulk capacitor →DC/DC power supply.•Avoid crossovers of signals from one part of the flow to another.•Keep all leads as short as possible, with wide power traces and paired signal and return paths.•Spacing consistent with safety standards like IEC60950 must be observed between the 48-V inputvoltage rails, and between the input and an isolated converter output.•The TPS2376-H should be referenced to a local ground plane V
SS
. The UCC3809-2 should bereferenced to a local ground plane RTN.•Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces oroverlay copper fills should be used in the power path.
Converter layout benefits from basic rules such as:1. Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses,including the power semiconductors and magnetics.2. Minimize the length of all the traces in step 1.3. Where possible, use vertical pairing.4. Use care if using the ground plane for the switching currents.5. Keep the high-current and high-voltage switching paths away from low-level sensing circuits, includingthose outside the power supply.6. Pay special attention to spacing around the high-voltage sections of the converter.
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5 Bill of Materials and Schematics
5.1 Bill of Materials
Bill of Materials and Schematics
This section provides the TPS2376HEVM bill of materials and schematics.
Table 1. Bill of MaterialsCount RefDes Value Description Size Part Number MFR
2 C1, C6 1000 pF Capacitor, Ceramic, 2 kV, X7R, 10% 1210 Std TDK
C10, C11, 0.1 μF Capacitor, Ceramic, 100 V, X7R, 10% 08053 Std TDKC12
C13, C14, 47 μF Capacitor, Ceramic, 10 V, X5R, 15% 12103 Std TDKC15
2 C16, C17 220 μF Capacitor, Aluminum, 6.3 V, ±20% 0.260 ×0.276 inch EEVFK0J221P Panasonic
C18, C24, 1 μF Capacitor, Ceramic, 16 V, X7R, 10% 06033 Std TDKC33
1 C19 0.22 μF Capacitor, Ceramic, 25 V, X7R, 10% 0603 Std TDK
C2, C3, C4, 0.01 μF Capacitor, Ceramic, 100 V, X7R, 10% 06034 Std TDKC5
1 C20 22 μF Capacitor, Aluminum, 25 V, ±20% 0.201 ×0.262 inch EEVFK1E220R Panasonic
1 C21 1000 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
2 C22, C23 0.47 μF Capacitor, Ceramic, 25 V, X7R, 10% 0805 Std TDK
1 C25 0.01 μF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
1 C26 270 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
1 C27 100 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
0 C28 Not Used Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
1 C29 0.1 μF Capacitor, Ceramic, 25 V, X7R, 10% 0603 Std TDK
1 C30 1200 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
1 C31 2200 pF Capacitor, Ceramic, 2 kV, X7R, 10% 1812 Std TDK
1 C32 0.082 μF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std TDK
1 C7 47 μF Capacitor, Aluminum, 100 V, 20% 0.543 ×0.543 EEVFK2A470Q Panasonic
2 C8, C9 1 μF Capacitor, Ceramic, 100 V, X7R, 10% 1210 Std Vishay
1 D1 MURA120 Diode, Rectifier, 1 A, 200 V SMA MURA120 On Semi
D2, D3 HD01-T Bridge Rectifier, 400 V, 0.8 A, Glass Passivated, MINI DIP42 HD01-T Diodes, Inc.SMD
1 D4 SMAJ58A Diode, SMT TVS 400 W, 4.3-A, 58-V SMA SMAJ58A Diodes
2 D5, D7 BAS16 Diode, Switching, 150-mA, 75-V, 350 mW SOT23 BAS16 Vishay-Liteon
2 D6, D8 BAV99 Diode, Dual Ultra Fast, Series, 200-mA, 70-V SOT23 BAV99 Fairchild
FB1, FB2 Bead, Ferrite, SMT 0805 MI0805K110R-10
Steward or2 or
TDKMMZ2012R150A
2 J1, J2 520252-4 Connector, Jack, Modular, 8 POS 0.705 ×0.820 inch 520252-4 AMP
1 J3 ED1514 Terminal Block, 2-pin, 6-A, 3,5 mm 0.27 ×0.25 inch ED1514 OST
1 J4 ED1609-ND Terminal Block, 2-pin, 15-A, 5,1 mm 0.40 ×0.35 inch ED1609 OST
1 L1 3.3 μH Inductor, SMT, 2A, 80 m Ω0.26 ×0.09 inch DO1608-332 Coilcraft
1 L2 0.33 μH Inductor, SMT, 6.26A, 7.4 m Ω0.300 sq" DR74-R33 Coiltronics
1 Q1 BCP53T1 Bipolar, PNP, 100-V, 1.5-A, 1.5-W SOT-223 BCP53T1 On Semi
1 Q2 MMBT2907ALT1 Transistor, PNP, –60V, –600mA, 225-W SOT23 MMBT2907ALT1 On Semi
1 Q3 Si7848DP MOSFET, NChannel, 60V, 15.8 A, 11 m ΩPWRPAK S0-8 Si7848DP Vishay-Siliconix
3 Q4, Q6, Q7 MMBT3906 Bipolar, PNP, 40-V, 200-mA, 222-mW SOT23 MMBT3906LT1 On Semi
1 Q5 Si7450DP MOSFET, NChannel, 200 V, 5.3 A, 90 m ΩPWRPAK S0-8 Si7450DP Vishay-Siliconix
8 R1–R8 75 ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R10 15 k ΩResistor, Chip, 1 W, 1% 2512 Std Std
1 R11 909 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R12 357 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R13 4.42 k ΩResistor, Chip, 1/16W, 1% 0603 Std Std
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Bill of Materials and Schematics
Table 1. Bill of Materials (continued)Count RefDes Value Description Size Part Number MFR
1 R14 61.9 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R15 2.2 ΩResistor, Chip, 1 W, 1% 2512 Std Std
1 R16 30.1 k ΩResistor, Chip, 1/10 W, 1% 0805 Std Std
1 R17 20 ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R18 10 ΩResistor, Chip, 1/2 W, 1% 2010 Std Std
1 R19 2.2 ΩResistor, Chip, 1/4 W, 1% 1210 Std Std
2 R20, R25 49.9 ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
R21, R30, 10 k ΩResistor, Chip, 1/16 W, 1% 06033 Std StdR31
1 R22 24.9 ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R23 10.7 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R24 4.64 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
3 R26, r29, R33 1 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R27 0.33 ΩResistor, Chip, 1 W, 1% 2512 Std Std
1 R28 4.99 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
2 R32, R34 41.2 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R35 13.3 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
1 R9 25.5 k ΩResistor, Chip, 1/16 W, 1% 0603 Std Std
2 T1, T2 ETH1-230LD XFMR, Mid-Power PoE Magnetics S0 14 Wide ETH1-230LD Coilcraft
1 T3 POE300F-50L Transformer, SMT for PoE/PD, xW, zzA 0810 ×1.181 inch POE300F-50L Coilcraft
1 T4 330 μH Transformer, Driver, 330 μH Ip, 1500V insolation 0.210 ×0.210 inch P0926 Pulse
TP1, TP5, 5012 Test Point, White, Thru Hole 0.125 ×0.125 inch3 5012 KeystoneTP9
1 J5 Header 1x2 100 mils TH TH Std
2 TP2, TP11 5001 Test Point, Black, Thru Hole Color Keyed 0.100 ×0.100 inch 5001 Keystone
TP4, TP8, 5000 Test Point, Red, Thru Hole Color Keyed 0.100 ×0.100 inch6 TP10, TP12, 5000 KeystoneTP13, TP15
1 U1 TPS2376DDA-H IC, IEEE 802.3af Power Device Controller S0-8 PowerPAD™ TPS2376DDA-H TI
1 U2 UCC3809D2 IC, Economy Primary-Side Controller, xx-V startup S08 UCC3809D-2 TI
1 U3 TCMT1107 IC< Photocoupler MF4 TCMT1107 Vishay
1 U4 TLV431ACDBVR IC, Shunt Regulator, 1.24-V ref, 6-V, 10-mA, 1% SOT23-5 TLV431ACDBVR TI
1 NA NA PCB, 2-Layer, 4.75" ×2.440" ×0.062" HPA244 Any
1 NA NA Shunt STC02SYAN Sullins
NA NA Rubber Bumper SPC4 2563
Technology
Notes: 1 These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk (**) cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Bumpers, to be installed on bottom of PCB, at four corners, of four sides, and approximate center of board.
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V to 57 V and the output voltage range of 4.75 V to 5.25 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 70 °C. The EVM is designed to operateproperly with certain components above 70 °C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. Thisnotice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/orsafety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
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