LTC2415-1IGN#PBF - ANALOG DEVICES

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TYPICAL APPLICATION

FEATURES DESCRIPTION

24-Bit No Latency ∆Σ™

ADCs with Differential Input and

Differential Reference

The LTC

2415/2415-1 are micropower 24-bit differential

∆Σ analog to digital converters with integrated oscillator,

2ppm INL, 0.23ppm RMS noise and a 2.7V to 5.5V supply

range. They use delta-sigma technology and provide single

cycle settling time for multiplexed applications. Through a

single pin, the LTC2415 can be configured for better than

110dB input differential mode rejection at 50Hz or 60Hz

±2%, or it can be driven by an external oscillator for a

user defined rejection frequency. The LTC2415-1 can be

configured for better than 87dB input differential mode

rejection over the range of 49Hz to 61.2Hz (50Hz and 60Hz

±2% simultaneously). The internal oscillator requires no

external frequency setting components.

The converters accept any external differential reference

voltage from 0.1V to VCC for flexible ratiometric and re-

mote sensing measurement configurations. The full-scale

differential input range is from –0.5VREF to 0.5VREF. The

reference common mode voltage, VREFCM, and the input

common mode voltage, VINCM, may be independently set

anywhere within the GND to VCC range of the LTC2415/

LTC2415-1. The DC common mode input rejection is

better than 140dB.

The LTC2415/LTC2415-1 communicate through a flexible

3-wire digital interface which is compatible with SPI and

MICROWIRE protocols.

n 2× Speed Up Version of the LTC2410/LTC2413:

15Hz Output Rate, 50Hz or 60Hz Notch—LTC2415;

13.75Hz Output Rate, Simultaneous 50Hz/60Hz

Notch—LTC2415-1

n Differential Input and Differential Reference with

GND to VCC Common Mode Range

n 2ppm INL, No Missing Codes

n 2.5ppm Gain Error

n 0.23ppm Noise

n Single Conversion Settling Time for Multiplexed

Applications

n Internal Oscillator—No External Components

Required

n 24-Bit ADC in Narrow SSOP-16 Package

(SO-8 Footprint)

n Single Supply 2.7V to 5.5V Operation

n Low Supply Current (200µA) and Auto Shutdown

APPLICATIONS

n Direct Sensor Digitizer

n Weight Scales

n Direct Temperature Measurement

n Gas Analyzers

n Strain Gage Transducers

n Instrumentation

n Data Acquisition

n Industrial Process Control

n 6-Digit DVMs

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and C-Load

and No Latency ∆Σ are trademarks of Linear Technology Corporation. All other trademarks are

the property of their respective owners.

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

= INTERNAL OSC/50Hz REJECTION (LTC2415)

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION (LTC2415)

= INTERNAL 50Hz/60Hz REJECTION (LTC2415-1)

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

2415 TA01

VCC

LTC2415/

LTC2415-1

IN+

REF+VCC

REF–

GND FO

IN–

1µF

SDO

3-WIRE

SPI INTERFACE

SCK

2415 TA02

1, 7, 8

9, 10,

15, 16

BRIDGE

IMPEDANCE

100

Ω TO 10k

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) to GND ....................... –0.3V to 7V

Analog Input Pins Voltage

to GND ......................................–0.3V to (VCC + 0.3V)

Reference Input Pins Voltage

to GND ......................................–0.3V to (VCC + 0.3V)

Digital Input Voltage to GND .........–0.3V to (VCC + 0.3V)

Digital Output Voltage to GND ....... –0.3V to (VCC + 0.3V)

Operating Temperature Range

LTC2415C/LTC2415-1C ............................ 0°C to 70°C

LTC2415I/LTC2415-1I ..........................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

(Note 1)

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

GND

VCC

F+

F–

IN+

IN–

GND

SCK

SDO

GND

TJMAX = 125°C, θJA = 95°C/W

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2415CGN#PBF LTC2415CGN#TRPBF 2415 16-Lead Plastic SSOP 0°C to 70°C

LTC2415IGN#PBF LTC2415IGN#TRPBF 2415I 16-Lead Plastic SSOP –40°C to 85°C

LTC2415-1CGN#PBF LTC2415-1CGN#TRPBF 24151 16-Lead Plastic SSOP 0°C to 70°C

LTC2415-1IGN#PBF LTC2415-1IGN#TRPBF 24151I 16-Lead Plastic SSOP –40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) ●24 Bits

Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)

5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)

REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)

●

14 ppm of VREF

ppm of VREF

Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,

GND ≤ IN+ = IN– ≤ VCC, (Note 14)

●0.5 2 mV

Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,

GND ≤ IN+ = IN– ≤ VCC

20 nV/°C

Positive Gain Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,

IN+ = 0.75REF+, IN– = 0.25 • REF+●2.5 12 ppm of VREF

Positive Gain Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,

IN+ = 0.75REF+, IN– = 0.25 • REF+0.03 ppm of VREF/°C

Negative Gain Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,

IN+ = 0.25 • REF+, IN– = 0.75 • REF+●2.5 12 ppm of VREF

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Negative Gain Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,

IN+ = 0.25 • REF+, IN– = 0.75 • REF+0.03 ppm of VREF/°C

Output Noise 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND,

GND ≤ IN– = IN+ ≤ VCC, (Note 13) 1.1 µVRMS

CONVERTER CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND,

GND ≤ IN– = IN+ ≤ VCC

l130 140 dB

Input Common Mode Rejection

60Hz ±2% (LTC2415) 2.5V ≤ REF+ ≤ VCC, REF– = GND,

GND ≤ IN– = IN+ ≤ VCC, (Note 7)

l140 dB

Input Common Mode Rejection

50Hz ±2% (LTC2415) 2.5V ≤ REF+ ≤ VCC, REF– = GND,

GND ≤ IN– = IN+ ≤ VCC, (Note 8)

l140 dB

Input Normal Mode Rejection

60Hz ±2% (LTC2415) (Note 7) l110 140 dB

Input Normal Mode Rejection

50Hz ±2% (LTC2415) (Note 8) l110 140 dB

Input Common Mode Rejection

49Hz to 61.2Hz (LTC2415-1) 2.5V ≤ REF+ ≤ VCC, REF– = GND, l140 dB

Input Normal Mode Rejection

49Hz to 61.2Hz (LTC2415-1) FO = GND l87 dB

Input Normal Mode Rejection

External Clock fEOSC/2560 ±14%

(LTC2415-1)

External Oscillator l87 dB

Input Normal Mode Rejection

External Clock fEOSC/2560 ±4%

(LTC2415-1)

External Oscillator l110 140 dB

Reference Common Mode

Rejection DC 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,

VREF = 2.5V, IN– = IN+ = GND

l130 140 dB

Power Supply Rejection, DC REF+ = VCC, REF– = GND, IN– = IN+ = GND 100 dB

Power Supply Rejection, 60Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB

Power Supply Rejection, 50Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) 120 dB

ANALOG INPUT AND REFERENCE

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN+Absolute/Common Mode IN+ Voltage ●GND – 0.3V VCC + 0.3V V

IN–Absolute/Common Mode IN– Voltage ●GND – 0.3V VCC + 0.3V V

VIN Input Differential Voltage Range

(IN+ – IN–)

●–VREF/2 VREF/2 V

REF+Absolute/Common Mode REF+ Voltage ●0.1 VCC V

REF–Absolute/Common Mode REF– Voltage ●GND VCC – 0.1V V

VREF Reference Differential Voltage Range

(REF+ – REF–)

●0.1 VCC V

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CS (IN+) IN+ Sampling Capacitance 18 pF

CS (IN–) IN– Sampling Capacitance 18 pF

CS (REF+) REF+ Sampling Capacitance 18 pF

CS (REF–) REF– Sampling Capacitance 18 pF

IDC_LEAK (IN+) IN+ DC Leakage Current CS = VCC, IN+ = GND ●–10 1 10 nA

IDC_LEAK (IN–) IN– DC Leakage Current CS = VCC, IN– = GND ●–10 1 10 nA

IDC_LEAK (REF+) REF+ DC Leakage Current CS = VCC, REF+ = 5V ●–10 1 10 nA

IDC_LEAK (REF–) REF– DC Leakage Current CS = VCC, REF– = GND ●–10 1 10 nA

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the specifications which apply

over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage

CS, FO

2.7V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 3.3V

●2.5

2.0 V

VIL Low Level Input Voltage

CS, FO

4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

●0.8

0.6 V

VIH High Level Input Voltage

SCK 2.7V ≤ VCC ≤ 5.5V (Note 9)

2.7V ≤ VCC ≤ 3.3V (Note 9)

●2.5

2.0 V

VIL Low Level Input Voltage

SCK 4.5V ≤ VCC ≤ 5.5V (Note 9)

2.7V ≤ VCC ≤ 5.5V (Note 9)

●0.8

0.6 V

IIN Digital Input Current

CS, FO

0V ≤ VIN ≤ VCC ●–10 10 µA

IIN Digital Input Current

SCK 0V ≤ VIN ≤ VCC (Note 9) ●–10 10 µA

CIN Digital Input Capacitance

CS, FO

10 pF

CIN Digital Input Capacitance

SCK (Note 9) 10 pF

VOH High Level Output Voltage

SDO IO = –800µA ●VCC – 0.5 V

VOL Low Level Output Voltage

SDO IO = 1.6mA ●0.4 V

VOH High Level Output Voltage

SCK IO = –800µA (Note 10) ●VCC – 0.5 V

VOL Low Level Output Voltage

SCK IO = 1.6mA (Note 10) ●0.4 V

IOZ Hi-Z Output Leakage

SDO

●–10 10 µA

POWER REQUIREMENTS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l2.7 5.5 V

ICC Supply Current

Conversion Mode

Sleep Mode

CS = 0V (Note 12)

CS = VCC (Note 12)

200

300

µA

ANALOG INPUT AND REFERENCE

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TIMING CHARACTERISTICS

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Notes 3,4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fEOSC External Oscillator Frequency Range l2.56 500 kHz

tHEO External Oscillator High Period l0.25 390 µs

tLEO External Oscillator Low Period l0.25 390 µs

tCONV Conversion Time (LTC2415) FO = 0V

FO = VCC

External Oscillator (Note 11)

65.43

78.52 66.77

80.12 68.1

81.72 ms

10278/fEOSC (in kHz)

Conversion Time (LTC2415-1) FO = 0V

External Oscillator (Note 11)

71.3 72.8 74.3 ms

10278/fEOSC (in kHz)

f ISCK Internal SCK Frequency Internal Oscillator (Note 10), LTC2415

Internal Oscillator (Note 10), LTC2415-1

External Oscillator (Notes 10, 11)

19.2

17.5

fEOSC/8

kHz

DISCK Internal SCK Duty Cycle (Note 10) l45 55 %

fESCK External SCK Frequency Range (Note 9) l2000 kHz

tLESCK External SCK Low Period (Note 9) l250 ns

tHESCK External SCK High Period (Note 9) l250 ns

tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12), LTC2415

Internal Oscillator (Notes 10, 12), LTC2415-1

External Oscillator (Notes 10, 11)

1.64

1.80 1.67

1.83 1.70

1.86 ms

256/fEOSC (in kHz)

tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 9) l32/fESCK (in kHz) ms

t1CS ↓ to SDO Low Z l0 200 ns

t2 CS ↑ to SDO High Z l0 200 ns

t3 CS ↓ to SCK ↓(Note 10) l0 200 ns

t4 CS ↓ to SCK ↑(Note 9) l50 ns

tKQMAX SCK ↓ to SDO Valid l220 ns

tKQMIN SDO Hold After SCK ↓(Note 5) l15 ns

t5SCK Set-Up Before CS ↓l50 ns

t6SCK Hold After CS ↓l50 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: VCC = 2.7 to 5.5V unless otherwise specified.

VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;

VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.

Note 4: FO pin tied to GND or to VCC or to external conversion clock source

with fEOSC = 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2% (external

oscillator).

Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external

oscillator).

Note 9: The converter is in external SCK mode of operation such that the

SCK pin is used as digital input. The frequency of the clock signal driving

SCK during the data output is fESCK and is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that the

SCK pin is used as digital output. In this mode of operation the SCK pin

has a total equivalent load capacitance CLOAD = 20pF.

Note 11: The external oscillator is connected to the FO pin. The external

oscillator frequency, fEOSC, is expressed in kHz.

Note 12: The converter uses the internal oscillator.

FO = 0V or FO = VCC.

Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 14: Refer to Offset Accuracy and Drift in the Applications Information

section.

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TYPICAL PERFORMANCE CHARACTERISTICS

(V)

–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5

TUE (ppm OF V

REF

)

2415 G01

106.5

106.0

105.5

105.0

104.5

104.0

103.5

= 5V

REF

= 5V

INCM

= 2.5V

REF

= 5V

REF

–

= GND

= 90°C

= 25°C

= –45°C

VIN (V)

–1.25 –0.75 –0.25 0.25 0.75

1.25

TUE (ppm OF V

REF

)

2415 G02

215

213

211

209

207

205

VCC = 5V

VREF = 2.5V

VINCM = 1.25V

REF+ = 2.5V

REF– = GND

FO = GND

TA = 90°C

TA = –45°C

TA = 25°C

VIN (V)

–1.25 –0.75 –0.25 0.25 0.75

1.25

TUE (ppm OF V

REF

)

2415 G03

125

121

117

113

109

105

VCC = 2.7V

VREF = 2.5V

VINCM = 1.25V

REF+ = 2.5V

REF– = GND

FO = GND

TA = –45°C

TA = 25°C

TA = 90°C

VIN (V)

–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5

INL ERROR (ppm OF V

REF

)

2415 G04

1.5

1.0

0.5

–0.5

–1.0

–1.5

VCC = 5V

VREF = 5V

VINCM = 2.5V

REF+ = 5V

REF– = GND

FO = GND

TA = 25°C

TA = –45°C

TA = 90°C

VIN (V)

–1.25 –0.75 –0.25 0.25 0.75

1.25

INL ERROR (ppm OF V

REF

)

2415 G05

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

–2.5

VCC = 5V

VREF = 2.5V

VINCM = 1.25V

REF+ = 2.5V

REF– = GND

FO = GND

TA = –45°C

TA = 25°C

TA = 90°C

VIN (V)

–1.25 –0.75 –0.25 0.25 0.75

1.25

INL ERROR (ppm OF V

REF

)

2415 G06

–2

–4

–6

–8

–10

VCC = 2.7V

VREF = 2.5V

VINCM = 1.25V

REF+ = 2.5V

REF– = GND

FO = GND

TA = 90°C

TA = –45°C

TA = 25°C

OUTPUT CODE (ppm OF VREF)

–105.5 –104.8 –104 –103.3

–102.5

NUMBER OF READINGS (%)

2415 G07

GAUSSIAN

DISTRIBUTION

m = –103.5ppm

σ = 0.27ppm

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = 2.5V

FO = GND

TA = 25°C

OUTPUT CODE (ppm OF VREF)

–105 –104.5 –104 –103.5

–103

NUMBER OF READINGS (%)

2415 G08

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = 2.5V

FO = 460800Hz

TA = 25°C

GAUSSIAN

DISTRIBUTION

m = –104.0ppm

σ = 0.25ppm

OUTPUT CODE (ppm OF VREF)

–212 –210.5 –209 –207.5

–206

NUMBER OF READINGS (%)

2415 G10

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 2.5V

VIN = 0V

REF+ = 2.5V

REF– = GND

IN+ = 1.25V

IN– = 1.25V

FO = GND

TA = 25C

GAUSSIAN

DISTRIBUTION

m = –209.2ppm

σ = 0.56ppm

Total Unadjusted Error Over

Temperature (VCC = 5V,

VREF = 5V)

Total Unadjusted Error Over

Temperature (VCC = 5V,

VREF = 2.5V)

Total Unadjusted Error Over

Temperature (VCC = 2.7V,

VREF = 2.5V)

Integral Nonlinearity Over

Temperature (VCC = 5V,

VREF = 5V)

Integral Nonlinearity Over

Temperature (VCC = 5V,

VREF = 2.5V)

Integral Nonlinearity Over

Temperature (VCC = 2.7V,

VREF = 2.5V)

Noise Histogram

(Output Rate = 15Hz,

VCC = 5V, VREF = 5V)

Noise Histogram

(Output Rate = 45Hz,

VCC = 5V, VREF = 5V)

Noise Histogram

(Output Rate = 15Hz,

VCC = 5V, VREF = 2.5V)

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT CODE (ppm OF VREF)

–211.5 –210.5 –209.5 –208.5

–207.5

NUMBER OF READINGS (%)

2415 G11

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 2.5V

VIN = 0V

REF+ = 2.5V

REF– = GND

IN+ = 1.25V

IN– = 1.25V

FO = 460800Hz

TA = 25°C

GAUSSIAN

DISTRIBUTION

m = –209.3ppm

σ = 0.49ppm

OUTPUT CODE (ppm OF VREF)

–116 –114.5 –113 –111.5

–110

NUMBER OF READINGS (%)

2415 G13

10,000 CONSECUTIVE

READINGS

VCC = 2.7V

VREF = 2.5V

VIN = 0V

REF+ = 2.5V

REF– = GND

IN+ = 1.25V

IN– = 1.25V

FO = GND

TA = 25°C

GAUSSIAN

DISTRIBUTION

m = –113.1ppm

σ = 0.59ppm

OUTPUT CODE (ppm OF VREF)

–112 –110.9 –109.8 –108.6

–107.5

NUMBER OF READINGS (%)

2415 G14

10,000 CONSECUTIVE

READINGS

VCC = 2.7V

VREF = 2.5V

VIN = 0V

REF+ = 2.5V

REF– = GND

IN+ = 1.25V

IN– = 1.25V

FO = 460800Hz

TA = 25°C

GAUSSIAN

DISTRIBUTION

m = –109.8ppm

σ = 0.50ppm

OUTPUT CODE (ppm OF VREF)

–103 –103.5 –104 –104.5

–105

NUMBER OF READINGS (%)

2415 G16

VCC = 5V

VREF = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = 2.5V

FO = GND

TA = 25°C

GAUSSIAN

DISTRIBUTION

m = –103.9ppm

σ = 0.27ppm

TIME (HRS)

0 5 10 15 20 25 30 35 40 45 50 55 60

ADC READINGS (ppm OF V

REF

)

2415 G17

–101.0

–101.5

–102.0

–102.5

–103.0

–103.5

–104.0

–104.5

–105.0

–105.5

VCC = 5V

VREF = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = 2.5V

FO = GND

TA = 25°C

INPUT DIFFERENTIAL VOLTAGE (V)

–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5

RMS NOISE (ppm OF V

REF

)

2415 G18

0.5

0.4

0.3

0.2

0.1

VCC = 5V

VREF = 5V

VINCM = 2.5V

REF+ = 5V

REF– = GND

FO = GND

TA = 25°C

VINCM (V)

–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

RMS NOISE (nV)

2415 G19

1800

1600

1400

1200

1000

IN+ = VINCM

IN– = VINCM

FO = GND

TA = 25°C

VCC = 5V

VREF = 5V

VIN = 0V

REF+ = 5V

REF– = GND

TEMPERATURE (°C)

–50 –25 0 25 50 75

100

RMS NOISE (nV)

2415 G20

1400

1250

1100

950

800

VCC = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = 2.5V

FO = GND

VCC (V)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

RMS NOISE (nV)

2415 G21

1560

1520

1480

1440

1400

1360

1320

1280

VREF = 2.5V

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

FO = GND

TA = 25°C

Noise Histogram

(Output Rate = 45Hz,

VCC = 5V, VREF = 2.5V)

Noise Histogram

(Output Rate = 15Hz,

VCC = 2.7V, VREF = 2.5V)

Noise Histogram

(Output Rate = 45Hz,

VCC = 2.7V, VREF = 2.5V)

Long-Term Histogram

(60Hrs)

Consecutive ADC Readings vs

Time

RMS Noise vs Input Differential

Voltage

RMS Noise vs VINCM RMS Noise vs Temperature (TA) RMS Noise vs VCC

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TYPICAL PERFORMANCE CHARACTERISTICS

VINCM (V)

–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

OFFSET ERROR (ppm OF V

REF

)

2415 G23

–103.0

–103.4

–103.8

–104.2

–104.6

–105.0

VCC = 5V

VREF = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = VINCM

IN– = VINCM

FO = GND

TA = 25°C

TEMPERATURE (°C)

–50 –25 0 25 50 75

100

OFFSET ERROR (ppm OF V

REF

)

2415 G24

–103.8

–104.0

–104.2

–104.4

–104.6

VCC = 5V

VIN = 0V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = 2.5V

FO = GND

VCC (V)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

OFFSET ERROR (ppm OF V

REF

)

2415 G25

–110

–130

–150

–170

–190

–210

–230

VREF = 2.5V

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

FO = GND

TA = 25°C

VCC AND VREF (V)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

OFFSET ERROR (ppm OF V

REF

)

2415 G26

–103.2

–103.6

–104.0

–104.4

–104.8

–105.2

REF– = GND

IN+ = GND

IN– = GND

FO = GND

TA = 25°C

TEMPERATURE (°C)

–45 –30 –15 0 15 30 45 60 75 90

+FULL-SCALE ERROR (ppm OF V

REF

)

2415 G27

–1

–2

–3

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 2.5V

IN– = GND

FO = GND

VCC (V)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

+FULL-SCALE ERROR (ppm OF V

REF

)

2415 G28

VREF = 2.5V

REF+ = 2.5V

REF– = GND

IN+ = 1.25V

IN– = GND

FO = GND

TA = 25°C

VREF (V)

1 2 3 40.5 1.5 2.5 3.5 4.5 5

+FULL-SCALE ERROR (ppm OF V

REF

)

2415 G29

–4

–8

VCC = 5V

REF+ = VREF

REF– = GND

IN+ = 0.5 • REF+

IN– = GND

FO = GND

TA = 25°C

TEMPERATURE (°C)

–45 –30 –15 0 15 30 45 60 75 90

–FULL-SCALE ERROR (ppm OF V

REF

)

2415 G30

–1

–2

–3

–4

–5

–6

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = GND

IN– = 2.5V

FO = GND

VREF (V)

01 2 3 40.5 1.5 2.5 3.5 4.5 5

RMS NOISE (nV)

2415 G22

1600

1400

1200

1000

800

VCC = 5V

REF– = GND

IN+ = GND

IN– = GND

FO = GND

TA = 25°C

RMS Noise vs VREF Offset Error vs VINCM Offset Error vs Temperature (TA)

Offset Error vs VCC Offset Error vs VCC and VREF

+Full-Scale Error vs

Temperature (TA)

+Full-Scale Error vs VCC +Full-Scale Error vs VREF

–Full-Scale Error vs

Temperature (TA)

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TYPICAL PERFORMANCE CHARACTERISTICS

(V)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

–FULL-SCALE ERROR (ppm OF V

REF

)

2415 G31

–1

–2

–3

–4

–5

REF

= 2.5V

REF

= 2.5V

REF

–

= GND

–

= 1.25V

= GND

= 25°C

VREF (V)

1 2 3 40.5 1.5 2.5 3.5 4.5 5

–FULL-SCALE ERROR (ppm OF V

REF

)

2415 G32

–4

–8

–12

VCC = 5V

REF+ = VREF

REF– = GND

IN+ = GND

IN– = 0.5 • REF+

FO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

0 50 100 150 200

250

REJECTION (dB)

2415 G33

–20

–40

–60

–80

–100

–120

VCC = 4.1V DC + 1.4V AC

REF+ = 2.5V

REF– = GND

IN+ = IN– = GND

FO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

1 100 10000

1000000

REJECTION (dB)

2415 G34

–20

–40

–60

–80

–100

–120

REF+ = 2.5V

REF– = GND

IN+ = IN– = GND

FO = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

15200 15300 15400

15500

REJECTION (dB)

2415 G35

–20

–40

–60

–80

–100

–120

VCC = 4.1V DC + 0.7V AC

REF+ = 2.5V

REF– = GND

IN+ = IN– = GND

FO = GND

TA = 25°C

TEMPERATURE (°C)

–45 –30 –15 0 15 30 45 60 75 90

SUPPLY CURRENT (µA)

2415 G36

220

210

200

190

180

170

160

150

140

VREF+ = VCC

VREF– = GND

VIN+ = VIN– = GND

FO = GND

CS = GND

SCK = SDO = N/C

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

–Full-Scale Error vs VCC –Full-Scale Error vs VREF PSRR vs Frequency at VCC

PSRR vs Frequency at VCC PSRR vs Frequency at VCC

Conversion Current vs

Temperature (TA)

OUTPUT DATA RATE (READINGS/SEC)

0 10 20 30 40 50

SUPPLY CURRENT (µA)

2415 G37

1000

900

800

700

600

500

400

300

200

100

= 5V

REF

= 5V

REF

–

= GND

–

= GND

= EXT OSC

CS = GND

SCK =N/C

SDO = N/C

TEMPERATURE (°C)

–45 –30 –15 0 15 30 45 60 75 90

SUPPLY CURRENT (µA)

2415 G38

REF+

= V

REF–

= GND

IN+

= V

IN–

= GND

CS = V

SCK = SDO = N/C V

= 5.5V

= 4.1V

= 2.7V

Conversion Current vs Output

Data Rate

Sleep Current vs

Temperature (TA)

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GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground

pins internally connected for optimum ground current

flow and VCC decoupling. Connect each one of these pins

to a ground plane through a low impedance connection.

All seven pins must be connected to ground for proper

operation.

VCC (Pin 2): Positive Supply Voltage. Bypass to GND

(Pin1) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.

The voltage on these pins can have any value between

GND and VCC as long as the reference positive input, REF+,

is maintained more positive than the reference negative

input, REF –, by at least 0.1V.

IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The

voltage on these pins can have any value between

GND – 0.3V and VCC + 0.3V. Within these limits the con-

verter bipolar input range (VIN = IN+ – IN–) extends from

–0.5 • (VREF) to 0.5 • (VREF). Outside this input range the

converter produces unique overrange and underrange

output codes.

CS (Pin 11): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion, the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

SDO (Pin 12): Three-State Digital Output. During the Data

Output period, this pin is used as serial data output. When

the chip select CS is HIGH (CS = VCC) the SDO pin is in a

high impedance state. During the Conversion and Sleep

periods, this pin is used as the conversion status output.

The conversion status can be observed by pulling CS LOW.

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as digital output

for the internal serial interface clock during the Data Output

period. In External Serial Clock Operation mode, SCK is

used as digital input for the external serial interface clock

during the Data Output period. A weak internal pull-up is

automatically activated in Internal Serial Clock Operation

mode. The Serial Clock Operation mode is determined by

the logic level applied to the SCK pin at power up or during

the most recent falling edge of CS.

FO (Pin 14): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion time.

When the FO pin is connected to VCC (LTC2415 only), the

converter uses its internal oscillator and the digital filter

first null is located at 50Hz. When the FO pin is connected

to GND (FO = OV), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz (LTC2415)

or simultaneous 50Hz/60Hz (LTC2415-1). When FO is

driven by an external clock signal with a frequency fEOSC,

the converter uses this signal as its system clock and the

digital filter first null is located at a frequency fEOSC/2560.

PIN FUNCTIONS

LTC2415/LTC2415-1

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FUNCTIONAL BLOCK DIAGRAM

TEST CIRCUITS

Figure 1. Functional Block Diagram

AUTOCALIBRATION

AND CONTROL

DAC

DECIMATING FIR

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

ADC

∑

∫∫∫

GND

VCC

IN+

IN–

SDO

SCK

REF+

F–

(INT/EXT)

2415 FD

– +

–

1.69k

SDO

2415 TA03

Hi-Z TO VOH

VOL TO VOH

TO Hi-Z

CLOAD

= 20pF

1.69k

SDO

2415 TA04

Hi-Z TO VOL

VOH TO VOL

TO Hi-Z

CLOAD

= 20pF

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APPLICATIONS INFORMATION

Figure 2. LTC2415 State Transition Diagram

CONVERTER OPERATION

Converter Operation Cycle

The LTC2415/LTC2415-1 are low power, delta-sigma

analog-to-digital converters with an easy to use 3-wire

serial interface (see Figure 1). Their operation is made

up of three states. The converter operating cycle begins

with the conversion, followed by the sleep state and ends

with the data output (see Figure 2). The 3-wire interface

consists of serial data output (SDO), serial clock (SCK)

and chip select (CS).

Data is updated on the falling edge of SCK allowing the

user to reliably latch data on the rising edge of SCK (see

Figure 3). The data output state is concluded once 32 bits

are read out of the ADC or when CS is brought HIGH. The

device automatically initiates a new conversion and the

cycle repeats.

Through timing control of the CS and SCK pins, the

LTC2415/LTC2415-1 offer several flexible modes of

operation (internal or external SCK and free-running

conversion modes). These various modes do not require

programming configuration registers; moreover, they do

not disturb the cyclic operation described above. These

modes of operation are described in detail in the Serial

Interface Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz or 60Hz

plus their harmonics. The filter rejection performance is

directly related to the accuracy of the converter system

clock. The LTC2415/LTC2415-1 incorporate a highly

accurate on-chip oscillator. This eliminates the need for

external frequency setting components such as crystals

or oscillators. Clocked by the on-chip oscillator, the

LTC2415 achieves a minimum of 110dB rejection at the

line frequency (50Hz or 60Hz ±2%), while the LTC2415-1

achieves a minimum of 87db rejection at 50Hz ±2% and

60Hz ±2% simultaneously.

Ease of Use

The LTC2415/LTC2415-1 data output has no latency,

filter settling delay or redundant data associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog voltages is easy.

CONVERT

SLEEP

DATA OUTPUT

2415 F02

TRUE

FALSE CS = LOW

AND

SCK

Initially, the LTC2415/LTC2415-1 perform a conversion.

Once the conversion is complete, the device enters the

sleep state. While in this sleep state, power consumption

is reduced by an order of magnitude if CS is HIGH. The

part remains in the sleep state as long as CS is HIGH.

The conversion result is held indefinitely in a static shift

Once CS is pulled LOW, the device begins outputting the

conversion result. There is no latency in the conversion

result. The data output corresponds to the conversion

just performed. This result is shifted out on the serial data

out pin (SDO) under the control of the serial clock (SCK).

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APPLICATIONS INFORMATION

The LTC2415/LTC2415-1 perform a full-scale calibration

every conversion cycle. This calibration is transparent to

the user and has no effect on the cyclic operation described

above. The advantage of continuous calibration is extreme

stability of full-scale readings with respect to time, supply

voltage change and temperature drift.

Unlike the LTC2410 and LTC2413, the LTC2415 and

LTC2415-1 do not perform an offset calibration every

conversion cycle. This enables the LTC2415/LTC2415-1 to

double their output rate while maintaining line frequency

rejection. The initial offset of the LTC2415/LTC2415-1 is

within 2mV independent of VREF. Based on the LTC2415/

LTC2415-1 new modulator architecture, the temperature

drift of the offset is less then 0.01ppm/°C. More informa-

tion on the LTC2415/LTC2415-1 offset is described in the

Offset Accuracy and Drift section of this data sheet.

Power-Up Sequence

The LTC2415/LTC2415-1 automatically enter an internal

reset state when the power supply voltage VCC drops

below approximately 2.2V. This feature guarantees the

integrity of the conversion result and of the serial interface

mode selection. (See the 2-wire I/O sections in the Serial

Interface Timing Modes section.)

When the VCC voltage rises above this critical threshold, the

converter creates an internal power-on-reset (POR) signal

with a duration of approximately 0.5ms. The POR signal

clears all internal registers. Following the POR signal, the

LTC2415/LTC2415-1 start a normal conversion cycle and

follow the succession of states described above. The first

conversion result following POR is accurate within the

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

Reference Voltage Range

These converters accept a truly differential external

reference voltage. The absolute/common mode voltage

specification for the REF+ and REF– pins covers the entire

range from GND to VCC. For correct converter operation, the

REF+ pin must always be more positive than the REF– pin.

The LTC2415/LTC2415-1 can accept a differential reference

voltage from 0.1V to VCC. The converter output noise is

determined by the thermal noise of the front-end circuits,

and as such, its value in nanovolts is nearly constant with

reference voltage. A decrease in reference voltage will not

significantly improve the converter’s effective resolution.

On the other hand, a reduced reference voltage will improve

the converter’s overall INL performance.

Input Voltage Range

The analog input is truly differential with an absolute/

common mode range for the IN+ and IN– input pins

extending from GND – 0.3V to VCC + 0.3V. Outside

these limits, the ESD protection devices begin to turn

on and the errors due to input leakage current increase

rapidly. Within these limits, the LTC2415/LTC2415-1 con-

vert the bipolar differential input signal, VIN = IN+–IN–,

from –FS=–0.5 • VREF to +FS = 0.5 • VREF where

VREF=REF+–REF–. Outside this range, the converters

indicate the overrange or the underrange condition using

distinct output codes.

Input signals applied to IN+ and IN– pins may extend by

300mV below ground and above VCC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN+ and IN– pins without affecting the perfor-

mance of the device. In the physical layout, it is important

to maintain the parasitic capacitance of the connection

between these series resistors and the corresponding

pins as low as possible; therefore, the resistors should

be located as close as practical to the pins. The effect of

the series resistance on the converter accuracy can be

evaluated from the curves presented in the Input Current/

Reference Current sections. In addition, series resistors

will introduce a temperature dependent offset error due to

the input leakage current. A 1nA input leakage current will

develop a 1ppm offset error on a 5k resistor if VREF=5V.

This error has a very strong temperature dependency.

Output Data Format

The LTC2415/LTC2415-1 serial output data stream is 32

bits long. The first 3 bits represent status information

indicating the sign and conversion state. The next 24 bits

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are the conversion result, MSB first. The remaining 5 bits

are sub LSBs beyond the 24-bit level that may be included

in averaging or discarded without loss of resolution. The

third and fourth bit together are also used to indicate an

underrange condition (the differential input voltage is

below –FS) or an overrange condition (the differential

input voltage is above +FS).

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign

indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,

this bit is LOW.

Bit 28 (fourth output bit) is the most significant bit

(MSB) of the result. This bit in conjunction with Bit 29

also provides the underrange or overrange indication.

If both Bit 29 and Bit 28 are HIGH, the differential input

voltage is above +FS. If both Bit 29 and Bit 28 are LOW,

the differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2415/LTC2415-1 Status Bits

Input Range

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

VIN ≥ 0.5 • VREF 0 0 1 1

0V ≤ VIN < 0.5 • VREF 0 0 1 0

–0.5 • VREF ≤ VIN < 0V 0 0 0 1

VIN < –0.5 • VREF 0 0 0 0

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0

may be included in averaging or discarded without loss

of resolution.

Data is shifted out of the SDO pin under control of the

serial clock (SCK), see Figure 3. Whenever CS is HIGH,

SDO remains high impedance and any externally gener-

ated SCK clock pulses are ignored by the internal data

out shift register.

In order to shift the conversion result out of the device,

CS must first be driven LOW. EOC is seen at the SDO pin

of the device once CS is pulled LOW. EOC changes real

time from HIGH to LOW at the completion of a conversion.

This signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

rising edge of SCK. Bit 30 is shifted out of the device on

the first falling edge of SCK. The final data bit (Bit 0) is

shifted out on the falling edge of the 31st SCK and may

be latched on the rising edge of the 32nd SCK pulse. On

the falling edge of the 32nd SCK pulse, SDO goes HIGH

indicating the initiation of a new conversion cycle. This

bit serves as EOC (Bit 31) for the next conversion cycle.

Table 2 summarizes the output data format.

As long as the voltage on the IN+ and IN– pins is main-

tained within the –0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater

than +FS, the conversion result is clamped to the value

corresponding to the +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value corresponding to –FS – 1LSB.

Offset Accuracy and Drift

Unlike the LTC2410/LTC2413 and the entire LTC2400

family, the LTC2415/LTC2415-1 do not perform an offset

calibration every cycle. The reason for this is to increase the

data output rate while maintaining line frequency rejection.

While the initial accuracy of the LTC2415/LTC2415-1 offset

is within 2mV (see Figure 4) several unique properties

of the LTC2415/LTC2415-1 architecture nearly eliminate

the drift of the offset error with respect to temperature

and supply.

As shown in Figure 5, the offset variation with temperature

is less than 0.6ppm over the complete temperature range

of –50°C to 100°C. This corresponds to a temperature

drift of 0.004ppm/°C.

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Table 2. LTC2415/LTC2415-1 Output Data Format

Differential Input Voltage

VIN*

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

Bit 27 Bit 26 Bit 25 … Bit 0

VIN* ≥ 0.5 • VREF** 0011000…0

0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1

0.25 • VREF** 0010100…0

0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1

0 0010000…0

–1LSB 0 0 0 1 1 1 1 … 1

–0.25 • VREF** 0001100…0

–0.25 • VREF** – 1LSB 0 0 0 1 0 1 1 … 1

–0.5 • VREF** 0001000…0

VIN* < –0.5 • VREF** 0000111…1

*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.

Figure 3. Output Data Timing

MSBSIG“0”

1 2 3 4 5 26 27 32

BIT 0BIT 27 BIT 5

LSB24

BIT 28BIT 29BIT 30

SDO

SCK

EOC

BIT 31

SLEEP DATA OUTPUT CONVERSION

2415 F03

Hi-Z

VCC (V)

2.5

OFFSET (ppm)

–50

–100

–150

–200

–250 3.0 3.5 4.0 4.5

2415 F04

5.0

5.5

VREF = 2.5V

TA = 25°C

PART NO.1

PART NO.2

PART NO.3

TEMPERATURE (°C)

–50

OFFSET ERROR (ppm OF V

REF

)

–103.8

–104.0

–104.2

–104.4

–104.6 –25 0 25 50

2415 F05

100

VCC AND VREF (V)

2.7

OFFSET ERROR (ppm OF V

REF

)

–103.0

–103.5

–104.0

–104.5

–105.0

–105.5 3.5 4.3 4.7

2415 F06

3.1 3.9 5.1 5.5

VCC = 5V

VREF = 5V

REF+ = 5V

REF– = GND

VIN = 0V

IN+ = GND

IN– = GND

FO = GND

TA =100°C

TA = –50°C

TA =25°C

Figure 4. Offset vs VCC Figure 5. Offset vs Temperature Figure 6. Offset vs VCC (VREF = VCC)

While the variation in offset with supply voltage is propor-

tional to VCC (see Figure 4), several characteristics of this

variation can be used to eliminate the effects. First, the

variation with respect to supply voltage is linear. Second,

the magnitude of the offset error decreases with decreased

supply voltage. Third, the offset error increases with

increased reference voltage with an equal and opposite

magnitude to the supply voltage variation. As a result, by

tying VCC to VREF, the variation with supply can be nearly

eliminated, see Figure 6. The variation with supply is less

than 2ppm over the entire 2.7V to 5.5V supply range.

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APPLICATIONS INFORMATION

Frequency Rejection Selection LTC2415 (FO)

The LTC2415 internal oscillator provides better than 110dB

normal mode rejection at the line frequency and its har-

monics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection,

FO should be connected to GND while for 50Hz rejection

the FO pin should be connected to VCC.

The selection of 50Hz or 60Hz rejection can also be made

by driving FO to an appropriate logic level. A selection

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected.

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2415 can

operate with an external conversion clock. The converter

automatically detects the presence of an external clock

signal at the FO pin and turns off the internal oscillator.

The frequency fEOSC of the external signal must be at least

2560Hz (1Hz notch frequency) to be detected. The external

clock signal duty cycle is not significant as long as the

minimum and maximum specifications for the high and

low periods tHEO and tLEO are observed.

While operating with an external conversion clock of a

frequency fEOSC, the LTC2415 provides better than 110dB

normal mode rejection in a frequency range fEOSC/2560

±4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from fEOSC/2560

is shown in Figure 7a.

Whenever an external clock is not present at the FO pin,

the converter automatically activates its internal oscilla-

tor and enters the Internal Conversion Clock mode. The

LTC2415 operation will not be disturbed if the change of

conversion clock source occurs during the sleep state

or during the data output state while the converter uses

an external serial clock. If the change occurs during the

conversion state, the result of the conversion in progress

may be outside specifications but the following conver-

sions will not be affected. If the change occurs during the

data output state and the converter is in the Internal SCK

mode, the serial clock duty cycle may be affected but the

serial data stream will remain valid.

Table 3a summarizes the duration of each state and the

achievable output data rate as a function of FO.

Frequency Rejection Selection LTC2415-1 (FO)

The LTC2415-1 internal oscillator provides better than

87dB normal mode rejection over the range of 49Hz to

61.2Hz as shown in Figure 7b. For simultaneous 50Hz/60Hz

rejection, FO should be connected to GND.

In order to achieve 87dB normal mode rejection of 50Hz

±2% and 60Hz ±2%, two consecutive conversions must be

averaged. By performing a continuous running average of

the two most current results, both simultaneous rejection

is achieved and a 2× increase in throughput is realized rela-

tive to the LTC2413 (see Normal Mode Rejection, Output

Rate and Running Averages sections of this data sheet).

When a fundamental rejection frequency different from

the range 49Hz to 61.2Hz is required or when the con-

verter must be synchronized with an outside source, the

LTC2415-1 can operate with an external conversion clock.

The converter automatically detects the presence of an

external clock signal at the FO pin and turns off the internal

oscillator. The frequency fEOSC of the external signal must

be at least 2560Hz to be detected. The external clock signal

duty cycle is not significant as long as the minimum and

maximum specifications for the high and low periods,

tHEO and tLEO, are observed.

While operating with an external conversion clock of a

frequency fEOSC, the LTC2415-1 provides better than 110dB

normal mode rejection in a frequency range fEOSC/2560

±4%. The normal mode rejection as a function of the

input frequency deviation from fEOSC/2560 is shown in

Figure7a and Figure 7c shows the normal mode rejection

with running averages included.

Whenever an external clock is not present at the FO pin

the converter automatically activates its internal oscilla-

tor and enters the Internal Conversion Clock mode. The

LTC2415-1 operation will not be disturbed if the change

of conversion clock source occurs during the sleep state

or during the data output state while the converter uses

an external serial clock. If the change occurs during the

conversion state, the result of the conversion in progress

may be outside specifications but the following conver-

sions will not be affected. If the change occurs during the

LTC2415/LTC2415-1

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Table 3a. LTC2415 State Duration

State Operating Mode Duration

CONVERT Internal Oscillator FO = LOW, (60Hz Rejection) 66.6ms, Output Data Rate ≤ 15 Readings/s

FO = HIGH, (50Hz Rejection) 80ms, Output Data Rate ≤ 12.4 Readings/s

External Oscillator FO = External Oscillator with Frequency

fEOSC kHz (fEOSC/2560 Rejection) 10278/fEOSCs, Output Data Rate ≤ fEOSC/10278 Readings/s

SLEEP As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT Internal Serial Clock FO = LOW/HIGH, (Internal Oscillator) As Long As CS = LOW But Not Longer Than 1.67ms (32 SCK cycles)

FO = External Oscillator with Frequency

fEOSC kHz As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles)

External Serial Clock with Frequency fSCK kHz As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles)

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

–12 –8 –4 0 4 8 12

REJECTION (dB)

2415 F07a

–60

–70

–80

–90

–100

–110

–120

–130

–140

Figure 7c. LTC2415/LTC2415-1

Normal Mode Rejection When Using

an External Oscillator of Frequency

fEOSC with Running Averages

Figure 7b. LTC2415-1 Normal Mode

Rejection When Using an Internal

Oscillator with Running Averages

48 50 52 54 56 58 60 62

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

NORMAL MODE REECTION RATIO (dB)

2415 F07b

–80

–90

–100

–120

–130

–140

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY fEOSC

/2560(%)

–12 –8 –4 0 4 8 12

NORMAL MODE REJECTION (dB)

2415 F07c

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

Figure 7a. LTC2415/LTC2415-1 Normal Mode

Rejection When Using an External Oscillator

of Frequency fEOSC without Running Averages

data output state and the converter is in the Internal SCK

mode, the serial clock duty cycle may be affected but the

serial data stream will remain valid.

Table 3b summarizes the duration of each state and the

achievable output data rate as a function of FO.

Serial Interface Pins

The LTC2415/LTC2415-1 transmit the conversion results

and receive the start of conversion command through

a synchronous 3-wire interface. During the conversion

and sleep states, this interface can be used to assess the

converter status and during the data output state it is used

to read the conversion result.

Table 3b. LTC2415-1 State Duration

State Operating Mode Duration

CONVERT Internal Oscillator FO = LOW

Simultaneous 50Hz/60Hz Rejection 72.8ms, Output Data Rate ≤ 14 Readings/s

External Oscillator FO = External Oscillator with Frequency

fEOSC kHz (fEOSC/2560 Rejection) 10278/fEOSCs, Output Data Rate ≤ fEOSC/10278 Readings/s

SLEEP As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT Internal Serial Clock FO = LOW/HIGH, (Internal Oscillator) As Long As CS = LOW But Not Longer Than 1.83ms (32 SCK cycles)

FO = External Oscillator with

Frequency fEOSC kHz As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles)

External Serial Clock with Frequency fSCK kHz As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles)

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Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to

synchronize the data transfer. Each bit of data is shifted

out the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is

an output and the LTC2415/LTC2415-1 create their own

serial clock by dividing the internal conversion clock by

8. In the External SCK mode of operation, the SCK pin

is used as input. The internal or external SCK mode is

selected on power-up and then reselected every time a

HIGH-to-LOW transition is detected at the CS pin. If SCK

is HIGH or floating at power-up or during this transition,

the converter enters the internal SCK mode. If SCK is LOW

at power-up or during this transition, the converter enters

the external SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO

pin is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 11) is HIGH, the SDO driver is switched

to a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

during the conversion phase, the EOC bit appears HIGH on

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = LOW.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversion status and to enable the data output transfer

as described in the previous sections.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2415/LTC2415-1 will abort any

serial data transfer in progress and start a new conver-

sion cycle anytime a LOW-to-HIGH transition is detected

at the CS pin after the converter has entered the data

output state (i.e., after the first rising edge of SCK occurs

with CS=LOW).

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert at

the maximum output rate selected by FO. Tying a capacitor

to CS will reduce the output rate and power dissipation by

a factor proportional to the capacitor’s value, see Figures

15 to 17.

SERIAL INTERFACE TIMING MODES

The LTC2415/LTC2415-1 3-wire interface is SPI and

MICROWIRE compatible. This interface offers several

flexible modes of operation. These include internal/external

serial clock, 2- or 3-wire I/O, single cycle conversion and

auto-start. The following sections describe each of these

serial interface timing modes in detail. In all these cases,

the converter can use the internal oscillator (FO = LOW

or FO=HIGH) or an external oscillator connected to the

FOpin. Refer to Table4 for a summary.

Table 4. LTC2415/LTC2415-1 Interface Timing Modes

Configuration SCK Source Conversion Cycle

Control

Data Output

Control

Connection and

Waveforms

External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 8, 9

External SCK, 2-Wire I/O External SCK SCK Figure 10

Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 11, 12

Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 13

Internal SCK, Auto-start Conversion Internal CEXT Internal Figure 14

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EOC

BIT 31

SDO

SCK

(EXTERNAL)

TEST EOC

SUB LSBMSBSIG

BIT 0

LSB

BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30

SLEEP DATA OUTPUT CONVERSION

2415 F08

CONVERSION

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

Hi-ZHi-ZHi-Z

VCC

TEST EOCTEST EOC

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

3-WIRE

SPI INTERFACE

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift

out the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

The serial clock mode is selected on the falling edge of

CS. To select the external serial clock mode, the serial

clock pin (SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS

is HIGH. At any time during the conversion cycle, CS

may be pulled LOW in order to monitor the state of the

converter. While CS is pulled LOW, EOC is output to the

SDO pin. EOC=1 while a conversion is in progress and

EOC = 0 if the device is in the sleep state. Independent of

CS, the device automatically enters the sleep state once

the conversion is complete. While in the sleep state, if CS

is high, the LTC2415/LTC2415-1 power consumption is

reduced by an order of magnitude

When the device is in the sleep state (EOC = 0), its con-

version result is held in an internal static shift register.

The device remains in the sleep state until the first rising

edge of SCK is seen while CS is LOW. Data is shifted out

the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 32nd rising edge of SCK. On the 32nd falling edge of

SCK, the device begins a new conversion. SDO goes HIGH

(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time

in order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pull-

ing CS HIGH anytime between the first rising edge and

the 32nd falling edge of SCK, see Figure 9. On the rising

edge of CS, the device aborts the data output state and

immediately initiates a new conversion. This is useful for

systems not requiring all 32 bits of output data, aborting

an invalid conversion cycle or synchronizing the start of

a conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface.

The conversion result is shifted out of the device by an

externally generated serial clock (SCK) signal, see Figure

10. CS may be permanently tied to ground, simplifying

the user interface or isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

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Figure 9. External Serial Clock, Reduced Data Output Length

SDO

SCK

(EXTERNAL)

DATA OUTPUT

CONVERSIONSLEEP SLEEP

TEST EOC TEST EOC

DATA OUTPUT

Hi-Z Hi-ZHi-Z

CONVERSION

2415 F09

MSBSIG

BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30

EOC

BIT 31BIT 0

EOC

Hi-Z

TEST EOC

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

approximately 0.5ms after VCC exceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal

or external. SCK must be driven LOW prior to the end of

POR in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is ready.

EOC = 1 while the conversion is in progress and EOC=0

once the conversion enters the sleep state. On the falling

edge of EOC, the conversion result is loaded into an internal

static shift register. The device remains in the sleep state

until the first rising edge of SCK. Data is shifted out the

SDO pin on each falling edge of SCK enabling external

circuitry to latch data on the rising edge of SCK. EOC can

be latched on the first rising edge of SCK. On the 32nd

falling edge of SCK, SDO goes HIGH (EOC=1) indicating

a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift

out the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 11.

In order to select the internal serial clock timing mode,

the serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resis-

tor is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is automati-

cally selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC =

0), the device will exit the sleep state and enter the data

output state if CS remains LOW. In order to prevent the

device from exiting the sleep state, CS must be pulled

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time tEOCtest after the falling edge of CS

(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW

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Figure 10. External Serial Clock, CS = 0 Operation (2-Wire)

Figure 11. Internal Serial Clock, Single Cycle Operation

EOC

BIT 31

SDO

SCK

(EXTERNAL)

MSBSIG

BIT 0

LSB24

BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30

SLEEP DATA OUTPUT CONVERSION

2415 F10

CONVERSION

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

2-WIRE

INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

SDO

SCK

(INTERNAL)

MSBSIG

BIT 0

LSB24

BIT 5 TEST EOC

BIT 27 BIT 26BIT 28BIT 29BIT 30

EOC

BIT 31

SLEEP DATA OUTPUT CONVERSIONCONVERSION

2415 F11

<tEOCtest

10k

Hi-Z Hi-Z Hi-Z Hi-Z

TEST EOC

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

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of SCK, see Figure 12. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to the

SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2415/LTC2415-1 internal

pull-up at pin SCK is disabled. Normally, SCK is not exter-

nally driven if the device is in the internal SCK timing mode.

However, certain applications may require an external driver

on SCK. If this driver goes Hi-Z after outputting a LOW

signal, the LTC2415/LTC2415-1 internal pull-up remains

disabled. Hence, SCK remains LOW. On the next falling

edge of CS, the device is switched to the external SCK

timing mode. By adding an external 10k pull-up resistor

to SCK, this pin goes HIGH once the external driver goes

Hi-Z. On the next CS falling edge, the device will remain

in the internal SCK timing mode.

SDO

SCK

(INTERNAL)

>tEOCtest

MSBSIG

BIT 8

TEST EOCTEST EOC BIT 27 BIT 26BIT 28BIT 29BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP DATA OUTPUT

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DATA OUTPUT

CONVERSIONCONVERSIONSLEEP

2415 F12

<tEOCtest

10k

TEST EOC

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

during the falling edge of EOC). The value of tEOCtest is

23µs (LTC2415), 26µs (LTC2415-1) if the device is using

its internal oscillator (FO = logic LOW or HIGH). If FO is

driven by an external oscillator of (LTC2415-1) frequency

fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before

time tEOCtest, the device remains in the sleep state. The

conversion result is held in the internal static shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins

on this first rising edge of SCK and concludes after the

32nd rising edge. Data is shifted out the SDO pin on each

falling edge of SCK. The internally generated serial clock

is output to the SCK pin. This signal may be used to shift

the conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result on the 32nd rising edge of SCK.

After the 32nd rising edge, SDO goes HIGH (EOC = 1),

SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

Figure 12. Internal Serial Clock, Reduced Data Output Length

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SDO

SCK

(INTERNAL)

LSB24

MSBSIG

BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT CONVERSIONCONVERSION

2415 F13

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

2-WIRE

INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (EOC = 0),

SCK will go LOW. Once CS goes HIGH (within the time

period defined above as tEOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin,

the internal pull-up may not be adequate to return SCK

to a HIGH level before CS goes low again. This is not a

concern under normal conditions where CS remains LOW

after detecting EOC = 0. This situation is easily overcome

by adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. The conversion result is shifted out of the device

by an internally generated serial clock (SCK) signal, see

Figure 13. CS may be permanently tied to ground, sim-

plifying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after VCC exceeds 2.2V. An internal

weak pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting data. The data output

cycle begins on the first rising edge of SCK and ends after

the 32nd rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used to

shift the conversion result into external circuitry. EOC can

be latched on the first rising edge of SCK and the last bit

of the conversion result can be latched on the 32nd rising

edge of SCK. After the 32nd rising edge, SDO goes HIGH

(EOC = 1) indicating a new conversion is in progress. SCK

remains HIGH during the conversion.

Figure 13. Internal Serial Clock, Continuous Operation

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SDO

Hi-ZHi-Z

SCK

(INTERNAL)

VCC

GND

2415 F14

BIT 0

SIG

BIT 29BIT 30

SLEEP DATA OUTPUT CONVERSIONCONVERSION

EOC

BIT 31

VCC FO

REF+

REF–

SCK

IN+

IN–

SDO

GND

2 14

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

2-WIRE

INTERFACE

1µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

CEXT

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

Internal Serial Clock, Auto-start Conversion

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 14. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 15 and 16. Once the

voltage at CS falls below an internal threshold (≈1.4V),

the device automatically begins outputting data. The data

output cycle begins on the first rising edge of SCK and

ends on the 32nd rising edge. Data is shifted out the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.

After the 32nd rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-

cations requiring periodic monitoring and ultralow power.

Figure 17 shows the average supply current as a function

of capacitance on CS.

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the auto-start

mode, the analog voltage on the CS pin cannot be observed

without disturbing the converter operation using a regular

oscilloscope probe. When using this configuration, it is

important to minimize the external leakage current at

the CS pin by using a low leakage external capacitor and

properly cleaning the PCB surface.

The internal serial clock mode is selected every time the

voltage on the CS pin crosses an internal threshold voltage.

An internal weak pull-up at the SCK pin is active while CS

is discharging; therefore, the internal serial clock timing

mode is automatically selected if SCK is floating. It is

important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

Figure 14. Internal Serial Clock, Auto-start Operation

LTC2415/LTC2415-1

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APPLICATIONS INFORMATION

Figure 15. CS Capacitance vs tSAMPLE

Figure 16. CS Capacitance vs Output Rate

Figure 17. CS Capacitance vs Supply Current

CAPACITANCE ON CS (pF)

1000 10000

2415 F15

10 100

100000

tSAMPLE (SEC)

VCC = 5V

VCC = 3V

CAPACITANCE ON CS (pF)

SAMPLE RATE (Hz)

1000

100000

2415 F16

010 100 10000

VCC = 5V

VCC = 3V

CAPACITANCE ON CS (pF)

SUPPLY CURRENT (µA

RMS

)

100

150

200

250

300

10 100 1000 10000

2415 F17

100000

VCC = 5V

VCC = 3V

and the conversion time of the LTC2413 is 146ms, while

the LTC2415-1 is 73ms. In systems where the SDO pin is

monitored for the end-of-conversion signal (SDO goes low

once the conversion is complete) these two devices can

be interchanged. In cases where SDO is not monitored, a

wait state is inserted between conversions, the duration

of this wait state must be greater than 66.6ms for the

LTC2415, greater than 133ms for the LTC2410, greater

than 146ms for the LTC2413 and greater than 73ms for

the LTC2415-1.

PRESERVING THE CONVERTER ACCURACY

The LTC2415/LTC2415-1 are designed to reduce as much

as possible conversion result sensitivity to device decou-

pling, PCB layout, anti-aliasing circuits, line frequency

perturbations and so on. Nevertheless, in order to preserve

the extreme accuracy capability of this part, some simple

precautions are desirable.

Digital Signal Levels

The LTC2415/LTC2415-1 digital interface is easy to use.

Its digital inputs (FO, CS and SCK in External SCK mode

of operation) accept standard TTL/CMOS logic levels and

the internal hysteresis receivers can tolerate edge rates

as slow as 100µs. However, some considerations are

required to take advantage of the exceptional accuracy

and low supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during conversion.

While a digital input signal is in the range 0.5V to

(VCC–0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (FO, CS and SCK

in External SCK mode of operation) is within this range, the

LTC2415/LTC2415-1 power supply current may increase

even if the signal in question is at a valid logic level. For

micropower operation, it is recommended to drive all

digital input signals to full CMOS levels [VIL < 0.4V and

VOH > (VCC – 0.4V)].

During the conversion period, the undershoot and/or over-

shoot of a fast digital signal connected to the LTC2415/

Timing Compatibility with the LTC2410/LTC2413

All timing modes described above are identical with respect

to the LTC2410/LTC2413 and LTC2415/LTC2415-1, with

one exception. The conversion time of the LTC2410 is

133ms while the conversion time of the LTC2415 is 66.6ms

LTC2415/LTC2415-1

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APPLICATIONS INFORMATION

LTC2415-1 pins may severely disturb the analog to digital

conversion process. Undershoot and overshoot can occur

because of the impedance mismatch at the converter pin

when the transition time of an external control signal is

less than twice the propagation delay from the driver to

LTC2415/LTC2415-1. For reference, on a regular FR-4

board, signal propagation velocity is approximately 183ps/

inch for internal traces and 170ps/inch for surface traces.

Thus, a driver generating a control signal with a minimum

transition time of 1ns must be connected to the converter

pin through a trace shorter than 2.5 inches. This problem

becomes particularly difficult when shared control lines are

used and multiple reflections may occur. The solution is

to carefully terminate all transmission lines close to their

characteristic impedance.

Parallel termination near the LTC2415/LTC2415-1 pins will

eliminate this problem but will increase the driver power

dissipation. A series resistor between 27Ω and 56Ω placed

near the driver or near the LTC2415/LTC2415-1 pins will

also eliminate this problem without additional power dis-

sipation. The actual resistor value depends upon the trace

impedance and connection topology.

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The multiple ground pins used

in this package configuration, as well as the differential

input and reference architecture, reduce substantially the

converter’s sensitivity to ground currents.

Particular attention must be given to the connection of

the FO signal when the LTC2415/LTC2415-1 are used

with an external conversion clock. This clock is active

during the conversion time and the normal mode rejection

provided by the internal digital filter is not very high at

this frequency. A normal mode signal of this frequency at

the converter reference terminals may result into DC gain

and INL errors. A normal mode signal of this frequency at

the converter input terminals may result into a DC offset

error. Such perturbations may occur due to asymmetric

capacitive coupling between the FO signal trace and the

converter input and/or reference connection traces. An

immediate solution is to maintain maximum possible

separation between the FO signal trace and the input/ref-

erence signals. When the FO signal is parallel terminated

near the converter, substantial AC current is flowing in the

loop formed by the FO connection trace, the termination

and the ground return path. Thus, perturbation signals

may be inductively coupled into the converter input and/

or reference. In this situation, the user must reduce to a

minimum the loop area for the FO signal as well as the loop

area for the differential input and reference connections.

Driving the Input and Reference

The input and reference pins of the LTC2415/LTC2415-1

converters are directly connected to a network of sam-

pling capacitors. Depending upon the relation between

the differential input voltage and the differential refer-

ence voltage, these capacitors are switching between

these four pins transferring small amounts of charge in

the process. A simplified equivalent circuit is shown in

Figure18.

For a simple approximation, the source impedance RS

driving an analog input pin (IN+, IN–, REF+ or REF–) can

be considered to form, together with R

SW and CEQ (see

Figure 18), a first order passive network with a time

constant τ = (RS + RSW) • CEQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant τ. The sampling process on

the four input analog pins is quasi-independent so each

time constant should be considered by itself and, under

worst-case circumstances, the errors may add.

When using the internal oscillator (FO = LOW or HIGH), the

LTC2415’s front-end switched-capacitor network is clocked

at 76800Hz corresponding to a 13µs sampling period and the

LTC2415-1’s front end is clocked at 69900Hz correspond-

ing to 14.2µs. Thus, for settling errors of less than 1ppm,

the driving source impedance should be chosen such that

τ≤13µs/14 = 920ns (LTC2415) and τ <14.2µs/14 = 1.01µs

(LTC2415-1). When an external oscillator of frequency fEOSC

is used, the sampling period is 2/fEOSC and, for a settling

error of less than 1ppm, τ ≤ 0.14/fEOSC.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

LTC2415/LTC2415-1

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Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit

Figure 19. An RC Network at IN+ and IN–Figure 21. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)

Figure 20. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)

I IN

( )

AVG

INCM

−V

REFCM

0.5•R

I IN

−

( )

AVG

=−V

INCM

−V

REFCM

0.5•R

I REF

( )

AVG

=1.5•V

REF

−V

INCM

REFCM

0.5•R

−V

REF

•R

I REF

−

( )

AVG

=−1.5•V

REF

−V

INCM

REFCM

0.5•R

REF

•R

where:

REF

=REF

−REF

−

REFCM

=REF

+REF

−











=IN

−IN

−

INCM

=IN

−IN

−











=3.61MΩINTERNAL OSCILLATOR 60Hz Notch F

=LOW

( )

LTC2415

=4.32MΩINTERNAL OSCILLATOR 50Hz Notch F

=HIGH

( )

LTC2415

=0.555•10

( )

/ f

EOSC

EXTERNAL OSCILLATOR

=3.97MΩINTERNAL OSCILLATOR 50Hz / 60Hz Notch F

=LOW

( )

LTC2415-1

CIN

2415 F19

INCM + 0.5VIN

SOURCE

IN+

LTC2415/

LTC2415-1

CPAR

≅20pF

CIN

INCM – 0.5VIN

RSOURCE

IN–

CPAR

≅20pF

RSOURCE (Ω)

1 10 100 1k 10k

100k

+FS ERROR (ppm OF V

REF

)

2415 F20

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 5V

IN– = 2.5V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.001µF

CIN = 100pF

CIN = 0pF

RSOURCE (Ω)

1 10 100 1k 10k

100k

–FS ERROR (ppm OF V

REF

)

2415 F21

–10

–20

–30

–40

–50

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = GND

IN– = 2.5V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.001µF

CIN = 100pF

CIN = 0pF

VREF+

VIN+

RSW (TYP)

20k

ILEAK

VCC

ILEAK

VCC

RSW (TYP)

20k

CEQ

18pF

(TYP)

RSW (TYP)

20k

ILEAK

IIN+

VIN–

IIN–

IREF+

IREF–

2415 F18

ILEAK

VCC

ILEAK

SWITCHING FREQUENCY

fSW = 76800Hz INTERNAL

OSCILLATOR (LTC2415)

(FO = LOW OR HIGH)

fSW = 69900Hz INTERNAL

OSCILLATOR (LTC2415-1)

(FO = LOW)

fSW = 0.5 • fEOSC

EXTERNAL OSCILLATOR

VREF–

RSW (TYP)

20k

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

the INL performance of the converter. Figure 18 shows the

mathematical expressions for the average bias currents

flowing through the IN+ and IN– pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 19. The CPAR capacitor

includes the LTC2415/LTC2415-1 pin capacitance (5pF

typical) plus the capacitance of the test fixture used to

obtain the results shown in Figures 20 and 21. A careful

implementation can bring the total input capacitance (CIN

+ CPAR) closer to 5pF thus achieving better performance

than the one predicted by Figures 20 and 21. For simplicity,

two distinct situations can be considered.

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APPLICATIONS INFORMATION

For relatively small values of input capacitance (CIN <

0.01µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the source

impedance result in only small errors. Such values for CIN

will deteriorate the converter offset and gain performance

without significant benefits of signal filtering and the user

is advised to avoid them. Nevertheless, when small val-

ues of CIN are unavoidably present as parasitics of input

multiplexers, wires, connectors or sensors, the LTC2415/

LTC2415-1 can maintain their exceptional accuracy while

operating with relative large values of source resistance

as shown in Figures 20 and 21. These measured results

may be slightly different from the first order approxima-

tion suggested earlier because they include the effect of

the actual second order input network together with the

nonlinear settling process of the input amplifiers. For

small CIN values, the settling on IN+ and IN– occurs almost

independently and there is little benefit in trying to match

the source impedance for the two pins.

Larger values of input capacitors (CIN > 0.01µF) may

be required in certain configurations for anti-aliasing or

general input signal filtering. Such capacitors will aver-

age the input sampling charge and the external source

resistance will see a quasi constant input differential

impedance. When FO = LOW (internal oscillator and 60Hz

notch), the typical differential input resistance is 1.8MΩ

(LTC2415), 1.97MΩ (LTC2415-1) which will generate

a gain error of approximately 0.28ppm for each ohm of

source resistance driving IN+ or IN–. For the LTC2415,

when FO = HIGH (internal oscillator and 50Hz notch), the

typical differential input resistance is 2.16MΩ which will

generate a gain error of approximately 0.23ppm for each

ohm of source resistance driving IN+ or IN–. When FO is

driven by an external oscillator with a frequency fEOSC (ex-

ternal conversion clock operation), the typical differential

input resistance is 0.28 • 1012/fEOSCΩ and each ohm of

source resistance driving IN+ or IN– will result in

1.78 • 10–6 • fEOSCppm gain error. The effect of the source

resistance on the two input pins is additive with respect to

this gain error. The typical +FS and –FS errors as a func-

tion of the sum of the source resistance seen by IN+ and

IN– for large values of CIN are shown in Figures 22 and 23.

In addition to this gain error, an offset error term may also

appear. The offset error is proportional to the mismatch

between the source impedance driving the two input

pins IN+ and IN– and with the difference between the

input and reference common mode voltages. While the

input drive circuit nonzero source impedance combined

with the converter average input current will not degrade

the INL performance, indirect distortion may result from

the modulation of the offset error by the common mode

component of the input signal. Thus, when using large

CIN capacitor values, it is advisable to carefully match the

source impedance seen by the IN+ and IN– pins. When

FO = LOW (internal oscillator and 60Hz notch), every 1Ω

mismatch in source impedance transforms a full-scale

common mode input signal into a differential mode input

signal of 0.28ppm. When FO = HIGH (internal oscillator

and 50Hz notch), every 1Ω mismatch in source imped-

ance transforms a full-scale common mode input signal

into a differential mode input signal of 0.23ppm. When FO

is driven by an external oscillator with a frequency fEOSC,

every 1Ω mismatch in source impedance transforms a full-

scale common mode input signal into a differential mode

input signal of 1.78 • 10–6 • fEOSCppm. Figure 24 shows

the typical offset error due to input common mode voltage

for various values of source resistance imbalance between

the IN+ and IN– pins when large CIN values are used.

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

The magnitude of the dynamic input current depends upon

the size of the very stable internal sampling capacitors and

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are used

for the external source impedance seen by IN+ and IN–,

the expected drift of the dynamic current, offset and gain

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Figure 22. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)Figure 23. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)

Figure 24. Offset Error vs Common Mode Voltage

(VINCM = IN+ = IN–) and Input Source Resistance Imbalance

(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)

RSOURCE (Ω)

0100 200 300 400 500 600 700 800 900

1000

+FS ERROR (ppm OF V

REF

)

2415 F22

300

240

180

120

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 3.75V

IN– = 1.25V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

RSOURCE (Ω)

0100 200 300 400 500 600 700 800 900

1000

–FS ERROR (ppm OF V

REF

)

2415 F23

–60

–120

–180

–240

–300

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 1.25V

IN– = 3.75V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

VINCM (V)

00.5 1 1.5 2 2.5 3 3.5 4 4.5 5

OFFSET ERROR (ppm OF V

REF

)

2415 F24

120

100

–20

–40

–60

–80

–100

–120

FO = GND

TA = 25°C

RSOURCEIN– = 500Ω

CIN = 10µF

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = IN– = VINCM

A: ∆RIN = +400Ω

B: ∆RIN = +200Ω

C: ∆RIN = +100Ω

D: ∆RIN = 0

E: ∆RIN = –100Ω

F: ∆RIN = –200Ω

G: ∆RIN = –400Ω

errors will be insignificant (about 1% of their respective

values over the entire temperature and voltage range). Even

for the most stringent applications, a one-time calibration

operation may be sufficient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

in a small offset shift. A 100Ω source resistance will create

a 0.1µV typical and 1µV maximum offset voltage.

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Figure 25. +FS Error vs RSOURCE at REF+ or REF– (Small CIN) Figure 26. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)

Figure 27. +FS Error vs RSOURCE at REF+ and REF– (Large CREF) Figure 28. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)

RSOURCE (Ω)

1 10 100 1k 10k

100k

+FS ERROR (ppm OF V

REF

)

2415 F25

–10

–20

–30

–40

–50

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 5V

IN– = 2.5V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

RSOURCE (Ω)

1 10 100 1k 10k

100k

–FS ERROR (ppm OF V

REF

)

2415 F26

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = GND

IN– = 2.5V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

RSOURCE (Ω)

0100 200 300 400 500 600 700 800 900

1000

+FS ERROR (ppm OF V

REF

)

2415 F27

–90

–180

–270

–360

–450

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 3.75V

IN– = 1.25V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.1µF

CREF = 1µF, 10µF

RSOURCE (Ω)

0100 200 300 400 500 600 700 800 900

1000

–FS ERROR (ppm OF V

REF

)

2415 F28

450

360

270

180

VCC = 5V

REF+ = 5V

REF– = GND

IN+ = 1.25V

IN– = 3.75V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0.1µF

CREF = 1µF, 10µF

Reference Current

In a similar fashion, the LTC2415/LTC2415-1 sample the

differential reference pins REF+ and REF– transferring small

amount of charge to and from the external driving circuits

thus producing a dynamic reference current. This current

does not change the converter offset, but it may degrade

the gain and INL performance. The effect of this current

can be analyzed in the same two distinct situations.

For relatively small values of the external reference capaci-

tors (CREF < 0.01µF), the voltage on the sampling capacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for CREF will deteriorate the converter offset and

gain performance without significant benefits of reference

filtering and the user is advised to avoid them.

Larger values of reference capacitors (CREF > 0.01µF) may

be required as reference filters in certain configurations.

Such capacitors will average the reference sampling charge

and the external source resistance will see a quasi constant

reference differential impedance. For the LTC2415, when

FO = LOW (internal oscillator and 60Hz notch), the typical

differential reference resistance is 1.3MΩ which will gener-

ate a gain error of approximately 0.38ppm for each ohm of

source resistance driving REF+ or REF–. When FO = HIGH

(internal oscillator and 50Hz notch), the typical differential

reference resistance is 1.56MΩ which will generate a gain

error of approximately 0.32ppm for each ohm of source

resistance driving REF+ or REF–. For the LTC2415-1, the

typical differential reference resistance is 1.43MΩ. When

FO is driven by an external oscillator with a frequency fEOSC

(external conversion clock operation), the typical differen-

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Figure 29. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference

Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF)

VINDIF/VREFDIF

–0.5–0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5

INL (ppm OF V

REF

)

–3

–6

–9

–12

–15

VCC = 5V

REF+ = 5V

REF– = GND

VINCM = 0.5 • (IN+ + IN–

) = 2.5V

FO = GND

CREF = 10µF

TA = 25°C

RSOURCE = 1000Ω

RSOURCE = 500Ω

RSOURCE = 100Ω

2415 F29

tial reference resistance is 0.20 • 1012/fEOSCΩ and each

ohm of source resistance driving REF+ or REF– will result in

2.47 • 10–6 • fEOSCppm gain error. The effect of the source

resistance on the two reference pins is additive with re-

spect to this gain error. The typical +FS and –FS errors

for various combinations of source resistance seen by

the REF+ and REF– pins and external capacitance CREF

connected to these pins are shown in Figures 25, 26, 27

and28.

In addition to this gain error, the converter INL performance

is degraded by the reference source impedance. When FO

= LOW (internal oscillator and 60Hz notch), every 100Ω of

source resistance driving REF+ or REF– translates into about

1.34ppm additional INL error. For the LTC2415, when FO

= HIGH (internal oscillator and 50Hz notch), every 100Ω

of source resistance driving REF+ or REF– translates into

about 1.1ppm additional INL error; and for the LTC2415-1

operating with simultaneous 50Hz/60Hz rejection, every

100Ω of source resistance leads to an additional 1.22ppm

of additional INL error. When FO is driven by an external

oscillator with a frequency fEOSC, every 100Ω of source

resistance driving REF+ or REF– translates into about 8.73•

10–6 • fEOSCppm additional INL error. Figure26 shows the

typical INL error due to the source resistance driving the

REF+ or REF– pins when large CREF values are used. The

effect of the source resistance on the two reference pins is

additive with respect to this INL error. In general, matching

of source impedance for the REF+ and REF– pins does not

help the gain or the INL error. The user is thus advised

to minimize the combined source impedance driving the

REF+ and REF– pins rather than to try to match it.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capacitors

and upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by REF+

and REF–, the expected drift of the dynamic current gain

error will be insignificant (about 1% of its value over the

entire temperature and voltage range). Even for the most

stringent applications a one-time calibration operation

may be sufficient.

In addition to the reference sampling charge, the refer-

ence pins ESD protection diodes have a temperature de-

pendent leakage current. This leakage current, nominally

1nA (±10nA max), results in a small gain error. A 100Ω

source resistance will create a 0.05µV typical and 0.5µV

maximum full-scale error.

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

APPLICATIONS INFORMATION

FREQUENCY AT VIN (Hz)

–120

REJECTION (dB)

–100

–80

–60

–40

–20

50 100 150 200

2415 F30

250

VCC = 5V

VREF = 5V

VIN = 2.5V

FO = 0

INPUT FREQUENCY

–60

–40

2415 F31

–80

–100

fS/2 fS

–120

–140

–20

REJECTION (dB)

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

–12 –8 –4 0 4 8 12

REJECTION (dB)

2415 F32

–60

–70

–80

–90

–100

–110

–120

–130

–140

48 50 52 54 56 58 60 62

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

NORMAL MODE REJECTION RATIO (dB)

2415 F33

–80

–90

–100

–120

–130

–140

INPUT FREQUENCY (Hz)

020 40 60 80 100 120 140 160 180 200

220

NORMAL MODE REJECTION (dB)

2415 F34

–20

–40

–60

–80

–100

–120

VCC = 5V

REF+ = 5V

REF– = GND

VINCM = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

Figure 34. Input Normal Mode Rejection vs Input

Frequency with Input Perturbation of 100% of Full Scale

Figure 30. Rejection vs Frequency at VIN Figure 31. Rejection vs Frequency at VIN Figure 32. Rejection vs Frequency at VIN

Figure 33. Normal Mode Rejection

when Using an Internal Oscillator

Normal Mode Rejection, Output Rate and Running

Averages

The LTC2415/LTC2415-1 both contain an identical Sinc4

digital filter (see Figures 30 and 31) which offers excellent

line frequency noise rejection. For the LTC2415, a notch

frequency of either 50Hz or 60Hz (see Figure 32) is user

selectable by tying pin FO high or low, respectively. On the

other hand, the LTC2415-1 offers simultaneous rejection

of 50Hz and 60Hz by tying FO low. This sets the notch

frequency to approximately 55Hz (see Figure 32).

At a notch frequency of 55Hz, the LTC2415-1 rejects 50Hz

±2% and 60Hz ±2% better than 72dB. In order to achieve

better than 87dB rejection of both 50Hz and 60Hz ±2%,

a running average can be performed. By averaging two

consecutive ADC readings, a Sinc1 notch is combined with

the Sinc4 digital filter yielding the frequency response

shown in Figures 33 and 34. In order to preserve the 2×

output rate, adjacent results are averaged with the fol-

lowing algorithm:

Result 1 = average (sample 0, sample 1)

Result 2 = average (sample 1, sample 2)

Result 3 = average (sample 2, sample 3)

…

Result N = average (sample n-1, sample n)

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

APPLICATIONS INFORMATION

Figure 36. Connecting the LTC2415/LTC2415-1 to a 68HC11 MCU Using the SPI Serial Interface

2415 F35

REF+

REF–

IN+

IN–

1, 7, 8, 9,

10, 15, 16

LTC2415/

LTC2415-1

VCC

GND

12 47µF

TO OTHER

DEVICES 4

74HC4052

Figure 35. Use a Differential Multiplexer to Expand Channel Capability

LTC2415/

LTC2415-1

SCK

SDO

SCK (PD4)

MISO (PD2)

SS (PD5)

68HC11

2415 F36

Sample Driver for LTC2415/LTC2415-1 SPI Interface

Figure 35 shows the use of an LTC2415/LTC2415-1 with a

differential multiplexer. This is an inexpensive multiplexer

that will contribute some error due to leakage if used directly

with the output from the bridge, or if resistors are inserted

as a protection mechanism from overvoltage. Although the

bridge output may be within the input range of the A/D and

multiplexer in normal operation, some thought should be

given to fault conditions that could result in full excitation

voltage at the inputs to the multiplexer or ADC. The use of

amplification prior to the multiplexer will largely eliminate

errors associated with channel leakage developing error

voltages in the source impedance.

The LTC2415/LTC2415-1 have a very simple serial in-

terface that makes interfacing to microprocessors and

microcontrollers very easy.

The listing in Figure 38 is a simple assembler routine for

the 68HC11 microcontroller. It uses PORT D, configur-

ing it for SPI data transfer between the controller and the

LTC2415/LTC2415-1. Figure 36 shows the simple 3-wire

SPI connection.

The code begins by declaring variables and allocating four

memory locations to store the 32-bit conversion result.

This is followed by initializing PORT D’s SPI configuration.

The program then enters the main sequence. It activates

the LTC2415/LTC2415-1 serial interface by setting the

SS output low, sending a logic low to CS. It next waits in

a loop for a logic low on the data line, signifying end-of-

conversion. After the loop is satisfied, four SPI transfers

are completed, retrieving the conversion. The main se-

quence ends by setting SS high. This places the LTC2415/

LTC2415-1 serial interface in a high impedance state and

initiates another conversion.

The performance of the LTC2415/LTC2415-1 can be verified

using the demonstration board DC291A, see Figure 40 for

the schematic. This circuit uses the computer’s serial port

to generate power and the SPI digital signals necessary

for starting a conversion and reading the result. It includes

a Labview application software program (see Figure 39)

which graphically captures the conversion results. It can

be used to determine noise performance, stability and

with an external source, linearity. As exemplified in the

schematic, the LTC2415/LTC2415-1 are extremely easy

to use. This demonstration board and associated software

is available by contacting Linear Technology.

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

APPLICATIONS INFORMATION

Correlated Double Sampling with the

LTC2415/LTC2415-1

Figure 37 shows the LTC2415/LTC2415-1 in a correlated

double sampling circuit that achieves a noise floor of

under 100nV. In this scheme, the polarity of the bridge is

alternated every other sample and the result is the average

of a pair of samples of opposite sign. This technique has

the benefit of canceling any fixed DC error components

in the bridge, amplifiers and the converter, as these will

alternate in polarity relative to the signal. Offset voltages

and currents, thermocouple voltages at junctions of dis-

similar metals and the lower frequency components of 1/f

noise are virtually eliminated.

The LTC2415/LTC2415-1 have the virtue of being able to

digitize an input voltage that is outside the range defined

by the reference, thereby providing a simple means to

implement a ratiometric example of correlated double

sampling.

This circuit uses a bipolar amplifier (LT1219—U1 and

U2) that has neither the lowest noise nor the highest gain.

It does, however, have an output stage that can effec-

tively suppress the conversion spikes from the LTC2415/

LTC2415-1. The LT1219 is a C-Load

stable amplifier

that, by design, needs at least 0.1µF output capacitance to

remain stable. The 0.1µF ceramic capacitors at the outputs

(C1 and C2) should be placed and routed to minimize lead

inductance or their effectiveness in preventing envelope

detection in the input stage will be reduced. Alternatively,

several smaller capacitors could be placed so that lead

inductance is further reduced. This is a consideration

because the frequency content of the conversion spikes

extends to 50MHz or more. The output impedance of most

op amps increases dramatically with frequency but the

effective output impedance of the LT1219 remains low,

determined by the ESR and inductance of the capacitors

above 10MHz. The conversion spikes that remain at the

output of other bipolar amplifiers pass through the feedback

network and often overdrive the input of the amplifier,

producing envelope detection. RFI may also be present

on the signal lines from the bridge; C3 and C4 provide RFI

suppression at the signal input, as well as suppressing

transient voltages during bridge commutation.

The wideband noise density of the LT1219 is 33nV√Hz,

seemingly much noisier than the lowest noise amplifiers.

However, in the region just below the 1/f corner that is

not well suppressed by the correlated double sampling,

the average noise density is similar to the noise density

of many low noise amplifiers. If the amplifier is rolled off

below about 1500Hz, the total noise bandwidth is deter-

mined by the converter’s Sinc4 filter at about 12Hz. The

use of correlated double sampling involves averaging even

numbers of samples; hence, in this situation, two samples

would be averaged to give an input-referred noise level of

about 100nVRMS.

Level shift transistors Q4 and Q5 are included to allow

excitation voltages up to the maximum recommended

for the bridge. In the case shown, if a 10V supply is

used, the excitation voltage to the bridge is 8.5V and

the outputs of the bridge are above the supply rail of the

ADC. U1 and U2 are also used to produce a level shift to

bring the outputs within the input range of the converter.

This instrumentation amplifier topology does not require

well-matched resistors in order to produce good CMRR.

However, the use of R2 requires that R3 and R6 match

well, as the common mode gain is approximately –12dB.

If the bridge is composed of four equal 350Ω resistors,

the differential component associated with mismatch of R3

and R6 is nearly constant with either polarity of excitation

and, as with offset, its contribution is canceled.

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

APPLICATIONS INFORMATION

–

LT1219

0.1µF

R3 10k

R6 10k

C4 2.2nF

C3 2.2nF

499Ω

10V

1000pF

27k

10V

DIFFERENCE

AMP

33Ω

100Ω

61.9Ω

0.1%

22Ω

74HC04

350Ω

×4

5V 5V

2.7k 2.7k

100Ω

1.5k 1.5k

ELIMINATE FOR 5V

OPERATION (CONNECT 2.7k

RESISTORS TO 100Ω

RESISTORS)

Q4 Q5

Q2 Q3

POL

Q1:

Q2, Q3:

Q4, Q5:

SILICONIX Si9802DY (800) 554-5565

MMBD2907

MMBD3904

0.1µf

SHDN

30pF

2415 F37

30pF

–

REF

–

GND

LTC2415/

LTC2415-1

Figure 37. Correlated Double Sampling Resolves 100nV

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TYPICAL APPLICATIONS

************************************************************

* This example program transfers the LTC2415/LTC2415-1 32-bit output *

* conversion result into four consecutive 8-bit memory locations. *

************************************************************

*68HC11 register definition

PORTD EQU $1008 Port D data register

* “ – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD”

DDRD EQU $1009 Port D data direction register

SPSR EQU $1028 SPI control register

* “SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”

SPSR EQU $1029 SPI status register

* “SPIF,WCOL, – ,MODF; – , – , – , – “

SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter

* RAM variables to hold the LTC2415/LTC2415-1’s 32 conversion result

DIN1 EQU $00 This memory location holds the LTC2415/LTC2415-1’s bits 31 - 24

DIN2 EQU $01 This memory location holds the LTC2415/LTC2415-1’s bits 23 - 16

DIN3 EQU $02 This memory location holds the LTC2415/LTC2415-1’s bits 15 - 08

DIN4 EQU $03 This memory location holds the LTC2415/LTC2415-1’s bits 07 - 00

**********************

* Start GETDATA Routine *

**********************

ORG $C000 Program start location

INIT1 LDS #$CFFF Top of C page RAM, beginning location of stack

LDAA #$2F –,–,1,0;1,1,1,1

* –, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X

STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set

LDAA #$38 –,–,1,1;1,0,0,0

STAA DDRD SS*, SCK, MOSI are configured as Outputs

* MISO, TxD, RxD are configured as Inputs

*DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output

LDAA #$50

STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0

* and the clock rate is E/2

* (This assumes an E-Clock frequency of 4MHz. For higher E-

* Clock frequencies, change the above value of $50 to a value

* that ensures the SCK frequency is 2MHz or less.)

GETDATA PSHX

PSHY

PSHA

LDX #$0 The X register is used as a pointer to the memory locations

* that hold the conversion data

LDY #$1000

BCLR PORTD, Y %00100000 This sets the SS* output bit to a logic

* low, selecting the LTC2415/LTC2415-1

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TYPICAL APPLICATIONS

********************************************

* The next short loop waits for the *

* LTC2415/LTC2415-1’s conversion to finish before *

* starting the SPI data transfer *

********************************************

CONVEND LDAA PORTD Retrieve the contents of port D

ANDA #%00000100 Look at bit 2

* Bit 2 = Hi; the LTC2415/LTC2415-1’s conversion is not

* complete

* Bit 2 = Lo; the LTC2415/LTC2415-1’s conversion is complete

BNE CONVEND Branch to the loop’s beginning while bit 2 remains

high

********************

* The SPI data transfer *

********************

TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer

STAA SPDR This writes the byte in the SPI data register and starts

* the transfer

WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial

transfer/exchange by reading the SPI Status Register

BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s MSB

* and is set to one at the end of an SPI transfer. The branch

* will occur while SPIF is a zero.

LDAA SPDR Load accumulator A with the current byte of LTC2415/LTC2415-1 data

that was just received

STAA 0,X Transfer the LTC2415/LTC2415-1’s data to memory

INX Increment the pointer

CPX #DIN4+1 Has the last byte been transferred/exchanged?

BNE TRFLP1 If the last byte has not been reached, then proceed to the

* next byte for transfer/exchange

BSET PORTD,Y %00100000 This sets the SS* output bit to a logic high,

* de-selecting the LTC2415/LTC2415-1

PULA Restore the A register

PULY Restore the Y register

PULX Restore the X register

RTS

Figure 38. This is an Example of 68HC11 Code That Captures the LTC2415/LTC2415-1

Conversion Results Over the SPI Serial Interface Shown in Figure 40

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

TYPICAL APPLICATIONS

PCB LAYOUT AND FILM

Silkscreen Top Top Layer

Differential Input 24-Bit ADC

with 2¥ Output Rate

Demo Circuit DC382

www.linear-tech.com

LTC Confidential For Customer Use Only

LTC2415CGN

Figure 39. Display Graphic

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

PCB LAYOUT AND FILM

Bottom Layer

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN16 REV B 0212

1 2 345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ±.004

(0.38 ±0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 08/15 Reduced external oscillator maximum frequency to 500kHz.

Removed noise histogram plots for 105Hz output rate.

Adjusted output data rate on G27 to maximum of 50 readings/second.

6, 7

LTC2415/LTC2415-1

2415fa

For more information www.linear.com/LTC2415

 LINEAR TECHNOLOGY CORPORATION 2001

LT 0815 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2415

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max Initial Accuracy

LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy

LTC1043 Dual Precision Instrumentation Switched Capacitor Building Block Precise Charge, Balanced Switching, Low Power

LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µVP-P Noise

LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift

LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift,

LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADCs in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2414/LTC2418 4-/8-Channel, 24-Bit, No Latency ∆Σ ADCs with Differential Inputs 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2410 24-Bit, No Latency ∆Σ ADC with Differential Inputs 800nVRMS Noise, Pin Compatible with LTC2415

LTC2411 24-Bit, No Latency ∆Σ ADC with Differential Inputs in MSOP 1.45µVRMS Noise, 4ppm INL

LTC2413 24-Bit, No Latency ∆Σ ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise

LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

JP4

JUMPER

DB9

2415 F40

10Ω

VEXT

BAV74LT1

100µF

16V

VOUT VIN

GND

LT1236ACN8-5

U3E

74HC14

6 2

1110

143

134

125

166

9871

112

2 1

U3F

74HC14

1312

U3B

74HC14

U3A

74HC14

U3C

74HC14

U3D

74HC14

+C3

10µF

35V

VOUT VIN

GND

LT1460ACN8-2.5

6 2

+C1

10µF

35V

+C2

22µF

25V

0.1µF

+C5

10µF

35V

VCC

GND

VCC

GND

REF–

BANANA JACK

REF+

BANANA JACK

VEXT

BANANA JACK

VIN+

BANANA JACK

VIN–

BANANA JACK

J10

GND

BANANA JACK

51k

MMBT3904LT1

49.9Ω

22k

51k

REF+FO

REF–SCK

VIN+ SDO

VIN– GND

GND

CSVCC

GNDGND GND GND

JP3

JUMPER

0.1µF

BYPASS CAP

FOR U3

NOTES:

INSTALL JUMBER JP1 AT PIN 1 AND PIN 2

INSTALL JUMBER JP2 AT PIN 1 AND PIN 2

INSTALL JUMBER JP3 AT PIN 1 AND PIN 2

VCC

JP5

JUMPER

JP1

JUMPER

JP2

JUMPER

3Ω

LTC2415/

LTC2415-1

Figure 40. 24-Bit A/D Demo Board Schematic