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H8/300L Series
Software Manual
16
User’s Manual
Rev.2.00 2004.12
Renesas 16-Bit Single-Chip
Microcomputer
H8 Family/H8/300L Series
Rev. 2.00 Dec 27, 2004 page ii of xii
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 2.00 Dec 27, 2004 page iii of xii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 2.00 Dec 27, 2004 page iv of xii
Rev. 2.00 Dec 27, 2004 page v of xii
Preface
The H8/300L Series of single-chip microcomputers is built around the high-speed H8/300L CPU,
with an architecture featuring eight 16-bit (or sixteen 8-bit) general registers and a concise,
optimized instruction set.
This manual gives detailed descriptions of the H8/300L instructions. The descriptions apply to all
chips in the H8/300L Series. Assembly-language programmers should also read the separate
H8/300 Series Cross Assembler User's Manual.
For hardware details, refer to the hardware manual of the specific chip.
Rev. 2.00 Dec 27, 2004 page vi of xii
Rev. 2.00 Dec 27, 2004 page vii of xii
Main Revisions for this Edition
Item Page Revision (See Manual for Details)
All All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and
other Hitachi brand names changed to Renesas Technology Corp.
Designation for categories changed from “series” to “group”
Rev. 2.00 Dec 27, 2004 page viii of xii
Rev. 2.00 Dec 27, 2004 page ix of xii
Contents
Section 1 CPU.................................................................................................................... 1
1.1 Overview........................................................................................................................... 1
1.1.1 Features............................................................................................................. 1
1.1.2 Data Structure ................................................................................................... 2
1.1.3 Address Space................................................................................................... 5
1.1.4 Register Configuration...................................................................................... 5
1.2 Registers............................................................................................................................ 6
1.2.1 General Registers.............................................................................................. 6
1.2.2 Control Registers .............................................................................................. 6
1.2.3 Initial Register Values....................................................................................... 7
1.3 Instructions........................................................................................................................ 8
1.3.1 Types of Instructions......................................................................................... 8
1.3.2 Instruction Functions......................................................................................... 9
1.3.3 Basic Instruction Formats ................................................................................. 20
1.3.4 Addressing Modes and Effective Address Calculation ..................................... 26
Section 2 Instruction Set ................................................................................................. 31
2.1 Explanation Format...........................................................................................................31
2.2 Instructions........................................................................................................................ 36
2.2.1 (1) ADD (add binary) (byte)................................................................................. 36
2.2.1 (2) ADD (add binary) (word)................................................................................ 37
2.2.2 ADDS (add with sign extension)..................................................................... 38
2.2.3 ADDX (add with extend carry) ....................................................................... 39
2.2.4 AND (AND logical)........................................................................................ 40
2.2.5 ANDC (AND control register)........................................................................ 41
2.2.6 BAND (bit AND)............................................................................................ 42
2.2.7 Bcc (branch conditionally) .............................................................................. 43
2.2.8 BCLR (bit clear).............................................................................................. 46
2.2.9 BIAND (bit invert AND) ................................................................................ 47
2.2.10 BILD (bit invert load) ..................................................................................... 48
2.2.11 BIOR (bit invert inclusive OR) ....................................................................... 49
2.2.12 BIST (bit invert store) ..................................................................................... 50
2.2.13 BIXOR (bit invert exclusive OR).................................................................... 51
2.2.14 BLD (bit load)................................................................................................. 52
2.2.15 BNOT (bit NOT)............................................................................................. 53
2.2.16 BOR (bit inclusive OR)................................................................................... 54
2.2.17 BSET (bit set).................................................................................................. 55
Rev. 2.00 Dec 27, 2004 page x of xii
2.2.18 BSR (branch to subroutine) ............................................................................. 56
2.2.19 BST (bit store) ................................................................................................. 57
2.2.20 BTST (bit test)................................................................................................. 58
2.2.21 BXOR (bit exclusive OR)................................................................................ 59
2.2.22 (1) CMP (compare) (byte)CMP ............................................................................ 60
2.2.22 (2) CMP (compare) (word)CMP........................................................................... 61
2.2.23 DAA (decimal adjust add)............................................................................... 62
2.2.24 DAS (decimal adjust subtract)......................................................................... 64
2.2.25 DEC (decrement)............................................................................................. 65
2.2.26 DIVXU (divide extend as unsigned) ............................................................... 66
2.2.27 EEPMOV (move data to EEPROM) ............................................................... 68
2.2.28 INC (increment)............................................................................................... 69
2.2.29 JMP (jump)...................................................................................................... 70
2.2.30 JSR (Jump to subroutine)................................................................................. 71
2.2.31 LDC (load to control register) LDC ................................................................ 72
2.2.32 (1) MOV (move data) (byte)MOV........................................................................ 73
2.2.32 (2) MOV (move data) (word)MOV ...................................................................... 74
2.2.32 (3) MOV (move data) (byte)MOV........................................................................ 75
2.2.32 (4) MOV (move data) (word)MOV ...................................................................... 76
2.2.32 (5) MOV (move data) (byte)MOV........................................................................ 77
2.2.32 (6) MOV (move data) (word)MOV ...................................................................... 78
2.2.33 MULXU (multiply extend as unsigned) .......................................................... 79
2.2.34 NEG (negate)................................................................................................... 80
2.2.35 NOP (no operation) ......................................................................................... 81
2.2.36 NOT (NOT = logical complement) ................................................................. 82
2.2.37 OR (inclusive OR logical) ............................................................................... 83
2.2.38 ORC (inclusive OR control register) ............................................................... 84
2.2.39 POP (pop data) ................................................................................................ 85
2.2.40 PUSH (push data) ............................................................................................ 86
2.2.41 ROTL (rotate left)............................................................................................ 87
2.2.42 ROTR (rotate right) ......................................................................................... 88
2.2.43 ROTXL (rotate with extend carry left) ............................................................ 89
2.2.44 ROTXR (rotate with extend carry right).......................................................... 90
2.2.45 RTE (return from exception) ........................................................................... 91
2.2.46 RTS (return from subroutine) .......................................................................... 92
2.2.47 SHAL (shift arithmetic left)............................................................................. 93
2.2.48 SHAR (shift arithmetic right) .......................................................................... 94
2.2.49 SHLL (shift logical left) .................................................................................. 95
2.2.50 SHLR (shift logical right)................................................................................ 96
2.2.51 SLEEP (sleep) ................................................................................................. 97
2.2.52 STC (store from control register)..................................................................... 98
Rev. 2.00 Dec 27, 2004 page xi of xii
2.2.53 (1) SUB (subtract binary) (byte)SUB ................................................................... 99
2.2.53 (2) SUB (subtract binary) (word)SUB.................................................................. 100
2.2.54 SUBS (subtract with sign extension)............................................................... 101
2.2.55 SUBX (subtract with extend carry) ................................................................. 102
2.2.56 XOR (exclusive OR logical) ........................................................................... 103
2.2.57 XORC (exclusive OR control register) ........................................................... 104
2.3 Operation Code Map......................................................................................................... 105
2.4 List of Instructions ............................................................................................................ 107
2.5 Number of Execution States.............................................................................................. 114
Section 3 CPU Operation States ................................................................................... 121
3.1 Program Execution State................................................................................................... 122
3.2 Exception Handling States ................................................................................................ 122
3.2.1 Types and Priorities of Exception Handling ..................................................... 122
3.2.2 Exception Sources and Vector Table ................................................................ 123
3.2.3 Outline of Exception Handling Operation......................................................... 124
3.3 Reset State......................................................................................................................... 125
3.4 Power-Down State ............................................................................................................ 125
Section 4 Basic Operation Timing ............................................................................... 127
4.1 On-chip Memory (RAM, ROM) ....................................................................................... 127
4.2 On-chip Peripheral Modules and External Devices .......................................................... 128
Rev. 2.00 Dec 27, 2004 page xii of xii
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 1 of 128
REJ09B0214-0200
Section 1 CPU
1.1 Overview
The H8/300L CPU at the heart of the H8/300L Series features 16 general registers of 8 bits each
(or 8 registers of 16-bits each), and a concise, optimized instruction set geared to high-speed
operation.
1.1.1 Features
The H8/300L CPU has the following features.
General register configuration
16 8-bit registers (can be used as 8 16-bit registers)
55 basic instructions
• Multiply and divide instructions
• Powerful bit manipulation instructions
8 addressing modes
• Register direct (Rn)
• Register indirect (@Rn)
• Register indirect with displacement (@(d:16, Rn))
• Register indirect with post-increment/pre-decrement (@Rn+/@–Rn)
• Absolute address (@aa:8/@aa:16)
• Immediate (#xx:8/#xx:16)
• Program-counter relative (@(d:8, PC))
• Memory indirect (@@aa:8)
64-kbyte address space
High-speed operation
• All frequently used instructions are executed in 2 to 4 states
• High-speed operating frequency: 5 MHz
Add/subtract between 8/16-bit registers: 0.4 µs
8 × 8-bit multiply: 2.8 µs
16 ÷ 8-bit divide: 2.8 µs
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 2 of 128
REJ09B0214-0200
Low-power operation
• Transition to power-down state using SLEEP instruction
1.1.2 Data Structure
The H8/300L CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit
(word) data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte
operand.
• All operational instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed
BCD form. Each 4-bit of the byte is treated as a decimal digit.
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 3 of 128
REJ09B0214-0200
Data Structure in General Registers: Data of all the sizes above can be stored in general
registers as shown in figure 1-1.
1-Bit data
1-Bit data
Byte data
Byte data
Word data
4-Bit BCD data
Data type
Don't-care
4
3
7
0
Data format
7
0
7
6
5
4
3
2
1
0
Don't-care
Don't-care
7
6
5
4
3
2
1
0
Don't-care
7
0
Don't-care
7
0
0
15
Don't-care
4
3
7
0
RnL
RnH
RnL
RnH
RnL
Rn
RnH
Register No.
7
0
4-Bit BCD data
M
S
B
M
S
B
M
S
B
L
S
B
L
S
B
L
S
B
Upper
Lower
Upper
Lower
RnH: Upper 8 bits of General Register
RnL: Lower 8 bits of General Register
MSB: Most Significant Bit
LSB: Least Significant Bit
Figure 1-1 Register Data Structure
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 4 of 128
REJ09B0214-0200
Data Structure in Memory: Figure 1-2 shows the structure of data in memory. The H8/300L
CPU is able to access word data in memory (MOV.W instruction), but only if the word data starts
from an even-numbered address. If an odd address is designated, no address error occurs, but the
access is performed starting from the previous even address, with the least significant bit of the
address regarded as 0.* The same applies to instruction codes.
* Note that the LSIs in the H8/300L Series also contain on-chip peripheral modules for
which access in word size is not possible. Details are given in the applicable hardware
manual.
L
S
B
Upper 8 bits
7
0
7
6
5
4
3
2
1
0
1-Bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Data type
Data format
Address
Address n
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
Lower 8 bits
M
S
B
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
Upper 8 bits
Lower 8 bits
CCR
CCR
*
CCR: Condition code register.
Note: Word data must begin at an even address.
*
: Ignored when returned.
Figure 1-2 Memory Data Formats
The stack is always accessed a word at a time. When the CCR is pushed on the stack, two identical
copies of the CCR are pushed to make a complete word. When they are returned, the lower byte is
ignored.
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 5 of 128
REJ09B0214-0200
1.1.3 Address Space
The H8/300L CPU supports a 64-kbyte address space (program code + data). The memory map
differs depending on the particular chip in the H8/300L Series and its operating mode. See the
applicable hardware manual for details.
1.1.4 Register Configuration
Figure 1-3 shows the register configuration of the H8/300L CPU. There are 16 8-bit general
registers (R0H, R0L, ..., R7H, R7L), which can also be accessed as eight 16-bit registers (R0 to
R7). There are two control registers: the 16-bit program counter (PC) and the 8-bit condition code
register (CCR).
0
7
R0H
R0L
R1H
R1L
R2H
R2L
R3L
R3H
R4L
R4H
R5H
R5L
R6H
R6L
R7H
R7L
(SP)
0
15
PC
0
2
3
5
C
V
Z
H
0
7
CCR
N
I
1
7
SP: Stack Pointer
Program Counter
Condition Code Register
Carry flag
Overflow flag
Zero flag
Half-carry flag
Interrupt mask bit
User bit
Negative flag
U
U
6
4
General Registers (Rn)
Control Registers (CR)
Figure 1-3 CPU Registers
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 6 of 128
REJ09B0214-0200
1.2 Registers
1.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers (R0 to R7), or the high (R0H to R7H) and
low (R0L to R7L) bytes can be accessed separately as 8-bit registers. The register length is
determined by the instruction.
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly language, the letters SP can be coded as a synonym for R7. As
indicated in figure 1-4, R7 (SP) points to the top of the stack.
Unused area
Stack area
SP (R7)
Figure 1-4 Stack Pointer
1.2.2 Control Registers
The CPU has a 16-bit program counter (PC) and an 8-bit condition code register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Instructions are fetched by 16-bit (word) access, so the least significant bit of
the PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register indicates the internal status of the CPU
with an interrupt mask (I) bit and five flag bits: half-carry (H), negative (N), zero (Z), overflow
(V), and carry (C) flags. The two unused bits are available to the user. The bit configuration of the
condition code register is shown below.
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 7 of 128
REJ09B0214-0200
Bit 76543210
I UHUNZVC
Initial value ********
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
*Not fixed
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked.
This bit is set to 1 automatically at the start of interrupt handling.
Bits 6 and 4—User Bits (U): These bits can be written and read by software for its own purposes
using LDC, STC, ANDC, ORC, and XORC instructions.
Bit 5—Half-Carry (H): This bit is used by add, subtract, and compare instructions to indicate a
borrow or carry out of bit 3 or bit 11. It is referenced by the decimal adjust instructions.
Bit 3—Negative (N): This bit indicates the value of the most significant bit (sign bit) of the result
of an instruction.
Bit 2—Zero (Z): This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero
result.
Bit 1—Overflow (V): This bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at
other times.
Bit 0—Carry (C): This bit is used by:
• Add, subtract, and compare instructions, to indicate a carry or borrow at the most significant
bit
• Shift and rotate instructions, to store the value shifted out of the most or least significant bit
• Bit manipulation instructions, as a bit accumulator
Note that some instructions involve no flag changes. The flag operations with each instruction are
indicated in the individual instruction descriptions that follow in section 2, Instruction Set. CCR is
used by LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by
the conditional branch instruction (Bcc).
1.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt
mask bit (I) in CCR is set to 1. The other CCR bits and the general registers are not initialized.
Section 1 CPU
Rev. 2.00 Dec 27, 2004 page 8 of 128
REJ09B0214-0200
The initial value of the stack pointer (R7) is not fixed. To prevent program crashes the stack
pointer should be initialized by software, by the first instruction executed after a reset.
1.3 Instructions
Features:
• The H8/300L CPU has a concise set of 55 instructions.
• A general-register architecture is adopted.
• All instructions are 2 or 4 bytes long.
• Fast multiply/divide instructions and extensive bit manipulation instructions are supported.
• Eight addressing modes are supported.
1.3.1 Types of Instructions
Table 1-1 classifies the H8/300L instructions by type. Section 2, Instruction Set, gives detailed
descriptions.
Table 1-1 Instruction Classification
Function Instructions Types
Data transfer MOV, POP*, PUSH*1
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG 14
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, ROTXR 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14
Branch Bcc**, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP 8
Block data transfer EEPMOV 1
Total 55
*POP Rn is equivalent to MOV.W @SP+, Rn.
PUSH Rn is equivalent to MOV.W Rn, @-SP.
** Bcc is a conditional branch instruction in which cc represents a condition.
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1.3.2 Instruction Functions
Tables 1-2 to 1-9 give brief descriptions of the instructions in each functional group.
The following notation is used.
Notation
Rd General register (destination)
Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) bit of CCR
Z Z (zero) bit of CCR
V V (overflow) bit of CCR
C C (carry) bit of CCR
PC Program counter
SP Stack pointer (R7)
#Imm Immediate data
op Operation field
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷ Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Move
¬Not
:3, :8, :16 3-bit, 8-bit, or 16-bit length
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Table 1-2 Data Transfer Instructions
Instruction Size*Function
MOV B/W (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general
register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn,
and @Rn+ addressing modes are available for byte or word
data. The @aa:8 addressing mode is available for byte data
only.
The @–R7 and @R7+ modes require word operands. Do not
specify byte size for these two modes.
POP W @SP+ → Rn
Pops a 16-bit general register from the stack.
Equivalent to MOV.W @SP+, Rn.
PUSH WRn → @–SP
Pushes a 16-bit general register onto the stack.
Equivalent to MOV.W Rn, @-SP.
*Size: Operand size
B: Byte
W: Word
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Table 1-3 Arithmetic Instructions
Instruction Size*Function
ADD
SUB
B/W Rd ± Rs → Rd, Rd + #Imm → Rd
Performs addition or subtraction on data in two general registers,
or addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general
register.
Word data can be added or subtracted only when both words are
in general registers.
ADDX
SUBX
B Rd ± Rs ± C → Rd, Rd ± #Imm ± C → Rd
Performs addition or subtraction with carry or borrow on byte data
in two general registers, or addition or subtraction on immediate
data and data in a general register.
INC
DEC
B Rd ± 1 → Rd
Increments or decrements a general register.
ADDS
SUBS
W Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts immediate data to or from data in a general
register. The immediate data must be 1 or 2.
DAA
DAS
B Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or
subtraction result in a general register by referring to the condition
code register.
MULXU BRd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two
general registers, providing a 16-bit result.
DIVXU B Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
CMP B/W Rd – Rs, Rd – #Imm
Compares data in a general register with data in another general
register or with immediate data. Word data can be compared only
between two general registers.
NEG B0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in
a general register.
*Size: Operand size
B: Byte
W: Word
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Table 1-4 Logic Operation Instructions
Instruction Size*Function
AND BRd ∧ Rs → Rd, Rd ∧ #Imm → Rd
Performs a logical AND operation on a general register and
another general register or immediate data.
OR BRd ∨ Rs → Rd, Rd ∨ #Imm → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR BRd ⊕ Rs → Rd, Rd ⊕ #Imm → Rd
Performs a logical exclusive OR operation on a general register
and another general register or immediate data.
NOT B¬ Rd → Rd
Obtains the one’s complement (logical complement) of general
register contents.
*Size: Operand size
B: Byte
Table 1-5 Shift Instructions
Instruction Size*Function
SHAL
SHAR
B Rd shift → Rd
Performs an arithmetic shift operation on general register
contents.
SHLL
SHLR
B Rd shift → Rd
Performs a logical shift operation on general register contents.
ROTL
ROTR
B Rd rotate → Rd
Rotates general register contents.
ROTXL
ROTXR
B Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit.
*Size: Operand size
B: Byte
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Table 1-6 Bit Manipulation Instructions
Instruction Size*Function
BSET B1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit is
specified by a bit number, given in 3-bit immediate data or the
lower three bits of a general register.
BCLR B0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
is specified by a bit number, given in 3-bit immediate data or the
lower three bits of a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is
specified by a bit number, given in 3-bit immediate data or the
lower three bits of a general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit is specified by a bit number,
given in 3-bit immediate data or the lower three bits of a general
register.
BAND BC ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or
memory.
BIAND BC ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
BOR BC ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or
memory.
BIOR BC ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
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Table 1-6 Bit Manipulation Instructions (Cont.)
Instruction Size*Function
BXOR BC ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the C flag with a specified bit in a general register
or memory.
BIXOR BC ⊕ [¬ (<bit-No.> of <EAd>)] →
Exclusive-ORs the C flag with the inverse of a specified bit in a
general register or memory.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C
flag.
BILD B ¬ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or
memory to the C flag.
The bit number is specified by 3-bit immediate data.
BST BC → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or
memory.
BIST B¬ C → (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
*Size: Operand size
B: Byte
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Table 1-7 Branching Instructions
Instruction Size*Function
Bcc Branches if condition cc is true. The branching conditions are as
follows.
Mnemonic Description Condition
BRA (BT) Always (True) Always
BRN (BF) Never (False) Never
BHI High C ∨ Z = 0
BLS Low or Same C ∨ Z = 1
BCC (BHS) Carry Clear
(High or Same)
C = 0
BCS (BLO) Carry Set (Low) C = 1
BNE Not Equal Z = 0
BEQ Equal Z = 1
BVC Overflow Clear V = 0
BVS Overflow Set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or Equal N ⊕ V = 0
BLT Less Than N ⊕ V = 1
BGT Greater Than Z ∨ (N ⊕ V) = 0
BLE Less or Equal Z ∨ (N ⊕ V) = 1
JMP Branches unconditionally to a specified address.
BSR Branches to a subroutine at a specified displacement from the
current address.
JSR Branches to a subroutine at a specified address.
RTS Returns from a subroutine.
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Table 1-8 System Control Instructions
Instruction Size*Function
RTE Returns from an exception handling routine.
SLEEP Causes a transition to power-down state.
LDC BRs → CCR, #Imm → CCR
Moves immediate data or general register contents to the
condition code register.
STC B CCR → Rd
Copies the condition code register to a specified general register.
ANDC B CCR ∧ #Imm → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #Imm → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #Imm → CCR
Logically exclusive-ORs the condition code register with
immediate data.
NOP PC + 2 → PC
Only increments the program counter.
*Size: Operand size
B: Byte
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Table 1-9 Block Data Transfer Instruction
Instruction Size*Function
EEPMOV if R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until R4L = 0
else next;
Moves a data block according to parameters set in general
registers
R4L, R5, and R6.
R4L: size of block (bytes)
R5: starting source address
R6: starting destination address
Execution of the next instruction starts as soon as the block
transfer is completed.
This instruction is for writing to the large-capacity EEPROM
provided on chip with some models in the H8/300L Series. For
details see the applicable hardware manual.
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-
modify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte
back. Care is required when these instructions are applied to registers with write-only bits and to
the I/O port registers.
Sequence Operation
1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in port control register 4 (PCR4) under the following
conditions.
P47 : Input pin, Low
P46 : Input pin, High
P45 – P40 : Output pins, Low
The intended purpose of this BCLR instruction is to switch P40 from output to input.
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Before Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
PCR4 00111111
PDR4 10000000
Execution of BCLR Instruction
BCLR #0 @PCR4 ;clear bit 0 in PCR4
After Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High
PCR4 11111110
PDR4 10000000
Explanation: To execute the BCLR instruction, the CPU begins by reading PCR4. Since PCR4 is
a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to PCR4 to complete the BCLR instruction.
As a result, bit 0 in PCR4 is cleared to 0, making P40 an input pin. In addition, bits 7 and 6 in
PCR4 are set to 1, making P47 and P46 output pins.
Example 2: BSET is executed to set bit 0 in the port 4 port data register (PDR4) under the
following conditions.
P47 : Input pin, Low
P46 : Input pin, High
P45 – P40 : Output pins, Low
The intended purpose of this BSET instruction is to switch the output level at P40 from Low to
High.
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Before Execution of BSET Instruction
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
PCR4 00111111
PDR4 10000000
Execution of BSET Instruction
BSET #0 @PDR4 ;set bit 0 in port 4 port data register
After Execution of BSET Instruction
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low High
PCR4 00111111
PDR4 01000001
Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P47 and
P46 are input pins, the CPU reads the level of these pins directly, not the value in the port data
register. It reads P47 as Low (0) and P46 as High (1).
Since P45 to P40 are output pins, for these pins the CPU reads the value in PDR4. The CPU
therefore reads the value of port 4 as H'40, although the actual value in PDR4 is H'80.
Next the CPU sets bit 0 of the read data to 1, changing the value to H'41.
Finally, the CPU writes this value (H'41) back to PDR4 to complete the BSET instruction.
As a result, bit 0 in PDR4 is set to 0, switching pin P40 to High output. However, bits 7 and 6 in
PDR4 change their values.
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1.3.3 Basic Instruction Formats
(1) Format of Data Transfer Instructions
Figure 1-5 shows the format used for data transfer instructions.
15 8 7 0 MOV
op rrRm
→ Rn
rr Rn
→ @Rm, or @Rm→ Rn
r r @(d:16, Rm) → Rn, or
disp. Rn → @(d:16, Rm)
r @Rm+ → Rn, or Rn → @–Rm
abs. @aa:8 → Rn, or Rn → @aa:8
r@aa:16 → Rn, or
abs. Rn → @aa:16
IMM #xx:8 → Rn
#xx:16 → Rn
IMM
r
m
n
m
m
r
n
n
n
n
n
r
n
r
n
m
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
0
op
r
n
POP, PUSH
8
7
Notation
op: Operation field
rm, rn: Register field
disp: Displacement
abs.: Absolute address
IMM: Immediate data
Figure 1-5 Instruction Format of Data Transfer Instructions
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(2) Format of Arithmetic, Logic Operation, and Shift Instructions
Figure 1-6 shows the format used for arithmetic, logic operation, and shift instructions.
r
ADD, SUB, CMP (Rm)
ADDX, SUBX (Rm)
r
m
n
15
8
7
0
op
r
ADDS, SUBS, INC, DEC, DAA,
DAS, NEG, NOT
n
15
8
7
0
op
r
IMM
ADD, ADDX, SUBX, CMP
(#xx:8)
r
IMM
AND, OR, XOR (#xx:8)
n
n
15
8
7
0
op
r
r
AND, OR, XOR (Rm)
m
n
15
8
7
0
op
15
8
7
0
op
r
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
n
15
8
7
0
op
r
MULXU, DIVXU
n
15
0
op
r
m
8
7
Notation
op: Operation field
rm, rn: Register field
IMM: Immediate data
Figure 1-6 Instruction Format of Arithmetic, Logic, and Shift Instructions
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(3) Format of Bit Manipulation Instructions
Figure 1-7 shows the format used for bit manipulation instructions.
BSET, BCLR, BNOT, BTST
IMM
r
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
r
Operand: register direct (Rn)
r
Operand: register indirect (@Rn)
r
Bit No.: register direct (Rm)
abs.
Operand: absolute (@aa:8)
IMM
Bit No.: immediate (#xx:3)
abs.
Operand: absolute (@aa:8)
r
Bit No.: register direct (Rm)
BAND, BOR, BXOR, BLD, BST
IMM
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
Operand: register indirect (@Rn)
IMM
Bit No.: immediate (#xx:3)
abs.
Operand: absolute (@aa:8)
IMM
Bit No.: immediate (#xx:3)
m
n
m
n
n
m
r
n
n
15
8
7
0
op
15
8
7
0
op
Bit No.: register direct (Rm)
r
Operand: register indirect (@Rn)
IMM
Bit No.: immediate (#xx:3)
n
15
8
7
0
op
op
15
8
7
0
op
15
8
7
0
op
op
15
8
7
0
op
op
15
8
7
0
op
15
8
7
0
op
op
15
8
7
0
op
op
op
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
Notation
op: Operation field
rm, rn: Register field
abs.: Absolute address
IMM: Immediate data
Figure 1-7 Instruction Format of Bit Manipulation Instructions
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BIAND, BIOR, BIXOR, BILD, BIST
IMM
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
Operand: register indirect (@Rn)
IMM
Bit No.: immediate (#xx:3)
abs.
Operand: absolute (@aa:8)
IMM
Bit No.: immediate (#xx:3)
r
n
n
15
8
7
0
op
op
15
8
7
0
op
op
15
8
7
0
op
0 0 0 0
0 0 0 0
0 0 0 0
Notation
op: Operation field
rm, rn: Register field
abs.: Absolute address
IMM: Immediate data
Figure 1-7 Instruction Format of Bit Manipulation Instructions (Cont.)
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(4) Format of Branching Instructions
Figure 1-8 shows the format used for branching instructions.
cc disp. Bcc
rJMP (@Rm)
JMP (@aa:16)
abs.
abs. JMP (@@aa:8)
disp. BSR
JSR (@Rm)
JSR (@aa:16)
abs.
abs. JSR (@@aa:8)
RTS
r
m
m
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
15
8
7
0
op
0
0
0
0
0 0 0 0
Notation
op: Operation field
cc: Condition field
rm: Register field
disp.: Displacement
abs.: Absolute address
Figure 1-8 Instruction Format of Branching Instructions
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(5) Format of System Control Instructions
Figure 1-9 shows the format used for system control instructions.
15 8 7 0
RTE, SLEEP, NOP
rLDC, STC (Rn)
IMM ANDC, ORC, XORC, LDC
(#xx:8)
n
op
15
8
7
0
op
15
8
7
0
op
Notation
op: Operation field
rn: Register field
IMM: Immediate data
Figure 1-9 Instruction Format of System Control Instructions
(6) Format of Block Data Transfer Instruction
Figure 1-10 shows the format used for the block data transfer instruction.
15 8 7 0
EEPMOV
op
op
Figure 1-10 Instruction Format of Block Data Transfer Instruction
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1.3.4 Addressing Modes and Effective Address Calculation
Table 1-10 lists the eight addressing modes and their assembly-language notation. Each instruction
can use a specific subset of these addressing modes.
Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX,
SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
The MOV instruction uses all the addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or absolute (5) addressing
to identify a byte operand and 3-bit immediate addressing to identify a bit within the byte. The
BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to identify
the bit.
Table 1-10 Addressing Modes
No. Mode Notation
(1) Register direct Rn
(2) Register indirect @Rn
(3) Register indirect with 16-bit displacement @(d:16, Rn)
(4) Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
(5) Absolute address (8 or 16 bits) @aa:8, @aa:16
(6) Immediate (3-, 8-, or 16-bit data) #xx:3, #xx:8, #xx:16
(7) PC-relative (8-bit displacement) @(d:8, PC)
(8) Memory indirect @@aa:8
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
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(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment
is 1 or 2 depending on the size of the operand: 1 for a byte operand; 2 for a word operand. For
a word operand, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is decremented before the operand is accessed. The size of the
decrement is 1 or 2 depending on the size of the operand: 1 for a byte operand; 2 for a word
operand. For a word operand, the original contents of the 16-bit general register must be even.
(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The @aa:8 mode uses an 8-bit absolute address of the form H'FFxx. The
upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to
65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or
a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit
immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as
immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the
second or fourth byte of the instruction, specifying a bit number.
(7) PC-Relative—@(d:8, PC): This mode is used to generate branch addresses in the Bcc and
BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-extended
value to the program counter contents. The result must be an even number. The possible branching
range is –126 to +128 bytes (–63 to +64 words) from the current address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0
to 255). Note that the initial part of the area from H'0000 to H'00FF contains the exception vector
table. See the applicable hardware manual for details. The word located at this address contains
the branch address.
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If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See the memory data structure description in section
1.1.2, Data Structure.
Effective Address Calculation
Table 1-11 explains how the effective address is calculated in each addressing mode.
Table 1-11 Effective Address Calculation (1)
Addressing mode, Effective address Effective
No. instruction format calculation address
1 Register direct Rn None
2 Register indirect @Rn
Operand is at address
indicated by register
15
0
7 6
4 3
OP
reg
16-bit register contents
15
0
15
0
15 8 7 0
OP
reg m
reg n
4 3
3
0
3
0
reg m
reg n
Operands are contained in
registers m and n
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Table 1-11 Effective Address Calculation (2)
Addressing mode, Effective address Effective
No. instruction format calculation address
3 Register indirect with displacement
@(d:16, Rn)
4 Register indirect with pre-decrement
@-Rn
Register indirect with post-increment
@Rn+
5 Absolute address None
@aa:8
Absolute address
@aa:16
16-bit register contents
15 0
15 0
16-bit displacement
+
15
0
disp
Operand address is sum
of register contents an d
displacement
OP
reg
7 6
4 3
15
0
7 6
4 3
OP
reg
16-bit register contents
15
0
-
1 or 2*
15
0
Register is decremented
before operand access
15
0
7 6
4 3
OP
reg
16-bit register contents
15
0
+
1 or 2*
15
0
Register is incremente
after operand access
Register is incremented
after operand access
OP
15
8 7
0
abs
H'FF
15
8 7
0
Operand address is in rang e
from H'FF00 to H'FFFF
15
0
OP
15
0
Any address
abs
*1 for a byte operand,
2 for a word operand
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Table 1-11 Effective Address Calculation (3)
Addressing mode, Effective address Effective
No. instruction format calculation address
6 Immediate #xx:8. None
Immediate #xx:16 None
7 PC-relative @(d:8, PC)
8 Memory indirect @@aa:8
reg, regm, regn: General register
op: Operation field
disp: Displacement
abs: Absolute address
IMM: Immediate data
PC contents
15
0
15
0
Destinationaddress
+
OP
15
8 7
0
disp
disp
Sign extension
OP
15
8 7
0
abs
H'00
15
8 7
0
16-bit memory contents
15
0
15
0
Destination address
OP
15
8 7
0
IMM
Operand is 1-byte
immediate data
15
0
OP
IMM
Operand is 2-byte
immediate dat a
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Section 2 Instruction Set
2.1 Explanation Format
Section 2 gives full descriptions of all the H8/300L Series instructions, presenting them in
alphabetic order. Each instruction is explained in a table like the following:
ADD (add binary) (byte) ADD
Operation
Rd + (EAs) → Rd
Assembly-Language Format
ADD.B <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a carry from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a carry from bit 7;
otherwise cleared to 0.
Description
This instruction adds the source operand to the contents of an 8-bit general register and places
the result in the general register.
Instruction Formats and Number of Execution States
Immediate ADD.B #xx:8, Rd 8 rd IMM 2
Register direct ADD.B Rs, Rd 0 8 rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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The parts of the table are explained below.
Name: The full and mnemonic names of the instruction are given at the top of the page.
Operation: The instruction is described in symbolic notation. The following symbols are used.
Symbol Meaning
Rd General register (destination)*
Rs General register (source)*
Rn General register*
<EAd> Destination operand
<EAs> Source operand
PC Program counter
SP Stack pointer
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
disp Displacement
→ Transfer from left operand to right operand; or state transition
from left state to right state.
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
¬ Inverse logic (logical complement)
( ) < > Contents of operand effective address
* General registers are either 8 bits (R0H/R0L - R7H/R7L) or 16 bits (R0 - R7).
Assembly-Language Format:
The assembly-language coding
of the instruction is given. An
example is:
ADD. B <EAs>, Rd
Mnemonic Size Source Destinatio
n
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The operand size is indicated by the letter B (byte) or W (word). Some instructions have
restrictions on the size of operands they handle.
The abbreviation EAs or EAd (effective address of source or destination) is used for operands that
permit more than one addressing mode. The H8/300L CPU supports the following eight
addressing modes. The method of calculating effective addresses is explained in section 1.3.4,
Addressing Modes and Effective Address Calculation, above.
Notation Addressing Mode
Rn Register direct
@Rn Register indirect
@(d:16, Rn) Register indirect with displacement
@Rn+/@–Rn Register indirect with post-increment/pre-decrement
@aa:8/@aa:16 Absolute address
#xx:8/#xx:16 Immediate
@(d:8, PC) Program-counter relative
@@aa:8 Memory indirect
Operand size: Word or byte. Byte size is indicated for bit-manipulation instructions because these
instructions access a full byte in order to read or write one bit.
Condition code: The effect of instruction execution on the flag bits in CCR is indicated. The
following notation is used:
Symbol Meaning
The flag is altered according to the result of the instruction.
0 The flag is cleared to "0."
The flag is not changed.
*Not fixed; the flag is left in an unpredictable state.
Description: The action of the instruction is described in detail.
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Instruction Formats: Each possible format of the instruction is shown explicitly, indicating the
addressing mode, the object code, and the number of states required for execution when the
instruction and its operands are located in on-chip memory. The following symbols are used:
Symbol Meaning
Imm. Immediate data (3, 8, or 16 bits)
abs. An absolute address (8 bits or 16 bits)
disp. Displacement (8 bits or 16 bits)
rs ,rd ,rnGeneral register number (3 bits or 4 bits) The s, d, and n correspond to the
letters in the operand notation.
Register Designation: 16-bit general registers are indicated by a 3-bit rs ,rd , or rn value. 8-bit
registers are indicated by a 4-bit rs ,rd , or rn value. Address registers used in the @Rn, @(disp:16,
Rn), @Rn+, and @–Rn addressing modes are always 16-bit registers. Data registers are 8-bit or
16-bit registers depending on the size of the operand. For 8-bit registers, the lower three bits of r s
,r d , or r n give the register number. The most significant bit is 1 if the lower byte of the register is
used, or 0 if the upper byte is used. Registers are thus indicated as follows:
16-Bit register 16-Bit registers
rs ,rd , or rnRegister rs ,rd , or rnRegister
0 0 0
0 0 1
:
1 1 1
R0
R1
:
R7
0 0 0 0
0 0 0 1
:
0 1 1 1
1 0 0 0
1 0 0 1
:
1 1 1 1
R0H
R1H
:
R7H
R0L
R1L
:
R7L
Bit Data Access: Bit data are accessed as the n-th bit of a byte operand in a general register or
memory. The bit number is given by 3-bit immediate data, or by a value in a general register.
When a bit number is specified in a general register, only the lower three bits of the register are
significant. Two examples are shown below.
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BSET R1L, R2H
BLD #5, @H'FF02:8
1 0 1 0 0 1 1 0
H'FF02
Loaded to C (carry)
flag in CCR C
Bit No. 5
R1L don't care 011
R2H 01100101
Bit number = 3
Bit 3 is set to 1
The addressing mode and operand size apply to the register or memory byte containing the bit.
Number of States Required for Execution: The number of states indicated is the number
required when the instruction and any memory operands are located in on-chip ROM or RAM. If
the instruction or an operand is located in external memory or the on-chip register field, additional
states are required for each access. See section 2.5, Number of Execution States.
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2.2 Instructions
2.2.1 (1) ADD (add binary) (byte) ADD ADD
Operation
Rd + (EAs) → Rd
Assembly-Language Format
ADD.B <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a carry from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a carry from bit 7;
otherwise cleared to 0.
Description
This instruction adds the source operand to the contents of an 8-bit general register and places
the result in the general register.
Instruction Formats and Number of Execution States
Immediate ADD.B #xx:8, Rd 8 rd IMM 2
Register direct ADD.B Rs, Rd 0 8 rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.1 (2) ADD (add binary) (word) ADD
Operation
Rd + Rs → Rd
Assembly-Language Format
ADD.W Rs, Rd
Operand Size
Word
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a carry from bit 11;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a carry from bit 15;
otherwise cleared to 0.
Description
This instruction adds word data in two general registers and places the result in the second
general register.
Instruction Formats and Number of Execution States
Register direct ADD.W Rs, Rd 0 9 0 rs 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.2 ADDS (add with sign extension) ADDS
Operation
Rd + 1 → Rd
Rd + 2 → Rd
Assembly-Language Format
ADDS #1, Rd
ADDS #2, Rd
Operand Size
Word
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction adds the immediate value 1 or 2 to word data in a general register. Unlike the
ADD instruction, it does not affect the condition code flags.
Instruction Formats and Number of Execution States
Register direct ADDS #1, Rd 0 B 0 0 rd 2
Register direct ADDS #2, Rd 0 B 8 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Note: This instruction cannot access byte-size data.
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2.2.3 ADDX (add with extend carry) ADDX
Operation
Rd + (EAs) + C → Rd
Assembly-Language Format
ADDX <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 if there is a carry from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a carry from bit 7;
otherwise cleared to 0.
Description
This instruction adds the source operand and carry flag to the contents of an 8-bit general
register and places the result in the general register.
Instruction Formats and Number of Execution States
Immediate ADDX #xx:8, Rd 9 rd IMM 2
Register direct ADDX Rs, Rd 0 E rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.4 AND (AND logical) AND
Operation
Rd ∧ (EAs) → Rd
Assembly-Language Format
AND <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction ANDs the source operand with the contents of an 8-bit general register and
places the result in the general register.
Instruction Formats and Number of Execution States
Immediate AND #xx:8, Rd E rd IMM 2
Register direct AND Rs, Rd 1 6 rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.5 ANDC (AND control register) ANDC
Operation
CCR ∧ #IMΜ→ CCR
Assembly-Language Format
ANDC #xx:8, CCR
Operand Size
Byte
Condition Code
IHNZVC
I: ANDed with bit 7 of the immediate data.
H: ANDed with bit 5 of the immediate data.
N: ANDed with bit 3 of the immediate data.
Z: ANDed with bit 2 of the immediate data.
V: ANDed with bit 1 of the immediate data.
C: ANDed with bit 0 of the immediate data.
Description
This instruction ANDs the condition code register (CCR) with immediate data and places the
result in the condition code register. Bits 6 and 4 are ANDed as well as the flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts, including the
nonmaskable interrupt (NMI), are deferred until after the next instruction.
Instruction Formats and Number of Execution States
Immediate ANDC #xx:8, CCR 0 6 IMM 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.6 BAND (bit AND) BAND
Operation
C ∧ (<Bit No.> of <EAd>) → C
Assembly-Language Format
BAND #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: ANDed with the specified bit.
Description
This instruction ANDs a specified bit with the carry flag and places the result in the carry flag.
The specified bit can be located in a general register or memory. The bit number is specified by
3-bit immediate data. The operation is shown schematically below.
C
∧
C
Bit No.
7
0
#xx:3
Byte data in register or memory
<EAd>*
→
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BAND #xx:3, Rd 7 6 0 IMM rd 2
Register indirect BAND #xx:3,@Rd 7 C 0 rd 0 76
0 IMM 0 6
Absolute address BAND #xx:3,@aa:8 7 E abs 7 6 0 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.7 Bcc (branch conditionally) Bcc
Operation
If cc then
PC + d:8 → PC
else next;
Assembly-Language Format
Bcc
Condition code field
d:8
(For mnemonics, see the table on
the next page.)
Operand Size
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
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Bcc (branch conditionally) Bcc
Description
If the specified condition is false, this instruction does nothing; the next instruction is executed.
If the specified condition is true, a signed displacement is added to the address of the next
instruction and execution branches to the resulting address.
The displacement is a signed 8-bit value which must be even. The branch destination address
can be located in the range –126 to +128 bytes from the address of the Bcc instruction.
The applicable conditions and their mnemonics are given below.
Mnemonic cc Field Description Condition Meaning
BRA (BT) 0 0 0 0 Always (True) Always true
BRN (BF) 0 0 0 1 Never (False) Never
BHI 0 0 1 0 High C ∨ Z = 0 X > Y (Unsigned)
BLS 0 0 1 1 Low or Same C ∨ Z = 1 X ≤ Y (Unsigned)
BCC (BHS) 0 1 0 0 Carry Clear
(High or Same)
C = 0 X ≥ Y (Unsigned)
BCS (BLO) 0 1 0 1 Carry Set (Low) C = 1 X < Y (Unsigned)
BNE 0 1 1 0 Not Equal Z = 0 X ≠ Y (Signed or
unsigned)
BEQ 0 1 1 1 Equal Z = 1 X = Y (Signed or
unsigned)
BVC 1 0 0 0 Overflow Clear V = 0
BVS 1 0 0 1 Overflow Set V = 1
BPL 1 0 1 0 Plus N = 0
BMI 1 0 1 1 Minus N = 1
BGE 1 1 0 0 Greater or Equal N ⊕ V = 0 X ≥ Y (Signed)
BLT 1 1 0 1 Less Than N ⊕ V = 1 X < Y (Signed)
BGT 1 1 1 0 Greater Than Z ∨ (N ⊕ V) = 0 X > Y (Signed)
BLE 1 1 1 1 Less or Equal Z ∨ (N ⊕ V) = 1 X ≤ Y (Signed)
BT, BF, BHS, and BLO are synonyms for BRA, BRN, BCC, and BCS, respectively.
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Bcc (branch conditionally) Bcc
Instruction Formats and Number of Execution States
Instruction code
Adressing
mode Mnem. Operands
1st
byte
2nd
byte
3rd
byte
4th
byte
No. of
states
PC relative BRA (BT) d:8 4 0 disp. 4
PC relative BRN (BF) d:8 4 1 disp. 4
PC relative BHI d:8 4 2 disp. 4
PC relative BLS d:8 4 3 disp. 4
PC relative BCC (BHS) d:8 4 4 disp. 4
PC relative BCS (BLO) d:8 4 5 disp. 4
PC relative BNE d:8 4 6 disp. 4
PC relative BEQ d:8 4 7 disp. 4
PC relative BVC d:8 4 8 disp. 4
PC relative BVS d:8 4 9 disp. 4
PC relative BPL d:8 4 A disp. 4
PC relative BMI d:8 4 B disp. 4
PC relative BGE d:8 4 C disp. 4
PC relative BLT d:8 4 D disp. 4
PC relative BGT d:8 4 E disp. 4
PC relative BLE d:8 4 F disp. 4
* The branch address must be even.
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2.2.8 BCLR (bit clear) BCLR
Operation
0 → (<Bit No.> of <EAd>)
Assembly-Language Format
BCLR #xx:3, <EAd>
BCLR Rn, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction clears a specified bit in the destination operand to 0. The bit number can be
specified by 3-bit immediate data, or by the lower three bits of an 8-bit general register. The
destination operand can be located in a general register or memory.
The specified bit is not tested before being cleared. The condition code flags are not altered.
#xx:3 or Rn
Bit No. 70
0
Byte data in register or memory
<EAd>*
→
Instruction Formats and Number of Execution States
Register direct BCLR #xx:3, Rd 7 2 0 IMM rd 2
Register indirect BCLR #xx:3,@Rd 7 D 0 rd 0 720 IMM 0 8
Absolute address BCLR #xx:3,@aa:8 7 F abs 7 2 0 IMM 0 8
Register direct BCLR Rn, Rd 6 2 rn rd 2
Register indirect BCLR Rn, @Rd 7 D 0 rd 0 62 rn 0 8
Absolute address BCLR Rn, @aa:8 7 F abs 6 2 rn 0 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.9 BIAND (bit invert AND) BIAND
Operation
C ∧[ ¬ (<Bit No.> of <EAd>)] → C
Assembly-Language Format
BIAND #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: ANDed with the inverse of the specified bit.
Description
This instruction ANDs the inverse of a specified bit with the carry flag and places the result in the
carry flag. The specified bit can be located in a general register or memory. The bit number is
specified by 3-bit immediate data. The operation is shown schematically below.
Bit No.
Byte data in register or memory
<EAd>*
→
7
0
C
∧
C
#xx:3
Invert
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BIAND #xx:3, Rd 7 6 1 IMM rd 2
Register indirect BIAND #xx:3,@Rd 7 C 0 rd 0 76
1 IMM 0 6
Absolute address BIAND #xx:3,@aa:8 7 E abs 7 6 1 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.10 BILD (bit invert load) BILD
Operation
¬ (<Bit No.> of <EAd>) → C
Assembly-Language Format
BILD #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Loaded with the inverse of the specified bit.
Description
This instruction loads the inverse of a specified bit into the carry flag. The specified bit can be
located in a general register or memory. The bit number is specified by 3-bit immediate data.
The operation is shown schematically below.
Bit No 70
C
#xx:3
Inver
t
Byte data in register or memory<EAd>*→
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BILD #xx:3, Rd 7 7 1 IMM rd 2
Register indirect BILD #xx:3,@Rd 7 C 0 rd 0 77
1 IMM 0 6
Absolute address BILD #xx:3,@aa:8 7 E abs 7 7 1 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.11 BIOR (bit invert inclusive OR) BIOR
Operation
C ∨ [¬ (<Bit No.> of <EAd>)] → C
Assembly-Language Format
BIOR #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: ORed with the inverse of the specified bit.
Description
This instruction ORs the inverse of a specified bit with the carry flag and places the result in the
carry flag. The specified bit can be located in a general register or memory. The bit number is
specified by 3-bit immediate data. The operation is shown schematically below.
#xx:3
Bit No.
Byte data in register or memory<EAd>*→
70
C
C
Invert
∧
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BIOR #xx:3, Rd 7 4 1 IMM rd 2
Register indirect BIOR #xx:3,@Rd 7 C 0 rd 0 74
1 IMM 0 6
Absolute address BIOR #xx:3,@aa:8 7 E abs 7 4 1 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
Section 2 Instruction Set
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2.2.12 BIST (bit invert store) BIST
Operation
¬ C → (<Bit No.> of <EAd>)
Assembly-Language Format
BIST #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction stores the inverse of the carry flag to a specified bit location in a general register
or memory. The bit number is specified by 3-bit immediate data. The operation is shown
schematically below.
Bit No. 70
C
#xx:3
Invert
Byte data in register or memory
<EAd>*
→
The values of the unspecified bits are not changed.
Instruction Formats and Number of Execution States
Register direct BIST #xx:3, Rd 6 7 1 IMM rd 2
Register indirect BIST #xx:3,@Rd 7 D 0 rd 0 67
1 IMM 0 8
Absolute address BIST #xx:3,@aa:8 7 F abs 6 7 1 IMM 0 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.13 BIXOR (bit invert exclusive OR) BIXOR
Operation
C ⊕ [¬ (<Bit No.> of <EAd>)] → C
Assembly-Language Format
BIXOR #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Exclusive-ORed with the inverse of the specified bit.
Description
This instruction exclusive-ORs the inverse of a specified bit with the carry flag and places the
result in the carry flag. The specified bit can be located in a general register or memory. The bit
number is specified by 3-bit immediate data. The operation is shown schematically below.
⊕
Bit No.
Byte data in register or memory<EAd>*→
70
C
C
#xx:3
Invert
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BIXOR #xx:3, Rd 7 5 1 IMM rd 2
Register indirect BIXOR #xx:3,@Rd 7 C 0 rd 0 75
1 IMM 0 6
Absolute address BIXOR #xx:3,@aa:8 7 E abs 7 5 1 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.14 BLD (bit load) BLD
Operation
(<Bit No.> of <EAd>) → C
Assembly-Language Format
BLD #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Loaded with the specified bit.
Description
This instruction loads a specified bit into the carry flag. The specified bit can be located in a
general register or memory. The bit number is specified by 3-bit immediate data. The operation
is shown schematically below.
Bit No. 70
C
#xx:3
Byte data in register or memory
<EAd>*
→
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BLD #xx:3, Rd 7 7 0 IMM rd 2
Register indirect BLD #xx:3,@Rd 7 C 0 rd 0 77
0 IMM 0 6
Absolute address BLD #xx:3,@aa:8 7 E abs 7 7 0 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.15 BNOT (bit NOT) BNOT
Operation
¬ (<Bit No.> of <EAd>)
→ (<Bit No.> of <EAd>)
Assembly-Language Format
BNOT #xx:3, <EAd>
BNOT Rn, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction inverts a specified bit in a general register or memory location. The bit number is
specified by 3-bit immediate data, or by the lower three-bits of a general register.
The operation is shown schematically below.
#xx:3 or Rn
Bit No. 70
Invert
Byte data in register or memory
<EAd>*
→
The bit is not tested before being inverted. The condition code flags are not altered.
Instruction Formats and Number of Execution States
Register direct BNOT #xx:3, Rd 7 1 0 IMM rd 2
Register indirect BNOT #xx:3,@Rd 7 D 0 rd 0 710 IMM 0 8
Absolute address BNOT #xx:3,@aa:8 7 F abs 7 1 0 IMM 0 8
Register direct BNOT Rn, Rd 6 1 rn rd 2
Register indirect BNOT Rn, @Rd 7 D 0 rd 0 61 rn 0 8
Absolute address BNOT Rn, @aa:8 7 F abs 6 1 rn 0 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.16 BOR (bit inclusive OR) BOR
Operation
C ∨ (<Bit No.> of <EAd>) → C
Assembly-Language Format
BOR #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: ORed with the specified bit.
Description
This instruction ORs a specified bit with the carry flag and places the result in the carry flag.
The specified bit can be located in a general register or memory. The bit number is specified by
3-bit immediate data. The operation is shown schematically below.
CC
Bit No. 70
#xx:3
Byte data in register or memory
<EAd>*
→
∨
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BOR #xx:3, Rd 7 4 0 IMM rd 2
Register indirect BOR #xx:3,@Rd 7 C 0 rd 0 74
0 IMM 0 6
Absolute address BOR #xx:3,@aa:8 7 E abs 7 4 0 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.17 BSET (bit set) BSET
Operation
1 → (<Bit No.> of <EAd>)
Assembly-Language Format
BSET #xx:3,<EAd>
BSET Rn,<EAd>
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction sets a specified bit in the destination operand to 1. The bit number can be
specified by 3-bit immediate data, or by the lower three-bits of an 8-bit general register. The
destination operand can be located in a general register or memory.
The specified bit is not tested before being cleared. The condition code flags are not altered.
1
#xx:3 or Rn
Bit No. 70
Byte data in register or memory
<EAd>*
→
Instruction Formats and Number of Execution States
Register direct BSET #xx:3, Rd 7 0 0 IMM rd 2
Register indirect BSET #xx:3,@Rd 7 D 0 rd 0 700 IMM 0 8
Absolute address BSET #xx:3,@aa:8 7 F abs 7 0 0 IMM 0 8
Register direct BSET Rn, Rd 6 0
rn
rd 2
Register indirect BSET Rn, @Rd 7 D 0 rd 0 60 rn 0 8
Absolute address BSET Rn, @aa:8 7 F abs 6 0 rn 0 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.18 BSR (branch to subroutine) BSR
Operation
PC → @–SP
PC + d:8 → PC
Assembly-Language Format
BSR d:8
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction pushes the program counter (PC) value onto the stack, then adds a specified
displacement to the program counter value and branches to the resulting address. The program
counter value used is the address of the instruction following the BSR instruction.
The displacement is a signed 8-bit value which must be even. The possible branching range is –
126 to +128 bytes from the address of the BSR instruction.
Instruction Formats and Number of Execution States
PC-relative BSR d:8 5 5 disp 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.19 BST (bit store) BST
Operation
C → (<Bit No.> of <EAd>)
Assembly-Language Format
BST #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction stores the carry flag to a specified flag location in a general register or memory.
The bit number is specified by 3-bit immediate data. The operation is shown schematically
below.
Bit No. 70
C
#xx:3
Byte data in register or memory
<EAd>*
→
Instruction Formats and Number of Execution States
Register direct BST #xx:3, Rd 6 7 0 IMM rd 2
Register indirect BST #xx:3,@Rd 7 D 0 rd 0 67
0 IMM 0 8
Absolute address BST #xx:3,@aa:8 7 F abs 6 7 0 IMM 0 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
Section 2 Instruction Set
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2.2.20 BTST (bit test) BTST
Operation
¬ (<Bit No.> of <EAd>) → Z
Assembly-Language Format
BTST #xx:3, <EAd>
BTST Rn, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
————— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Set to 1 when the specified bit is zero;
otherwise cleared to 0.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction tests a specified bit in a general register or memory location and sets or clears
the Zero flag accordingly. The bit number can be specified by 3-bit immediate data, or by the
lower three bits of an 8-bit general register. The operation is shown schematically below.
#xx:3 or Rn
Bit No. 70
Test
Byte data in register or memory
<EAd>*
→
The value of the specified bit is not altered.
Instruction Formats and Number of Execution States
Register direct BTST #xx:3, Rd 7 3 0 IMM rd 2
Register indirect BTST #xx:3,@Rd 7 C 0 rd 0 730 IMM 0 6
Absolute address BTST #xx:3,@aa:8 7 E abs 7 3 0 IMM 0 6
Register direct BTST Rn, Rd 6 3 rn rd 2
Register indirect BTST Rn, @Rd 7 C 0 rd 0 63 rn 0 6
Absolute address BTST Rn, @aa:8 7 E abs 6 3 rn 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.21 BXOR (bit exclusive OR) BXOR
Operation
C ⊕ (<Bit No.> of <EAd>) → C
Assembly-Language Format
BXOR #xx:3, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Exclusive-ORed with the specified bit.
Description
This instruction exclusive-ORs a specified bit with the carry flag and places the result in the carry
flag. The specified bit can be located in a general register or memory. The bit number is
specified by 3-bit immediate data. The operation is shown schematically below.
Bit No.
Byte data in register or memory<EAd>*→
70
⊕
C
C
#xx:3
The value of the specified bit is not changed.
Instruction Formats and Number of Execution States
Register direct BXOR #xx:3, Rd 7 5 0 IMM rd 2
Register indirect BXOR #xx:3,@Rd 7 C 0 rd 0 75
0 IMM 0 6
Absolute address BXOR #xx:3,@aa:8 7 E abs 7 5 0 IMM 0 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
* Register direct, register indirect, or absolute addressing.
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2.2.22 (1) CMP (compare) (byte) CMP
Operation
Rd – (EAs); set condition code
Assembly-Language Format
CMP.B <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a borrow from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a borrow from bit 7;
otherwise cleared to 0.
Description
This instruction subtracts an 8-bit source register or immediate data from an 8-bit destination
register and sets the condition code flags according to the result. The destination register is not
altered.
Instruction Formats and Number of Execution States
Immediate CMP.B #xx:8,Rd A rd IMM 2
Register direct CMP.B Rs, Rd 1 C rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.22 (2) CMP (compare) (word) CMP
Operation
Rd – Rs; set condition code
Assembly-Language Format
CMP.W Rs, Rd
Operand Size
Word
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a borrow from bit 11;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a borrow from bit 15;
otherwise cleared to 0.
Description
This instruction subtracts a source register from a destination register and sets the condition
code flags according to the result. The destination register is not altered.
Instruction Formats and Number of Execution States
Register direct CMP.W Rs, Rd 1 D 0 rs 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.23 DAA (decimal adjust add) DAA
Operation
Rd (decimal adjust) → Rd
Assembly-Language Format
DAA Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
**
I: Previous value remains unchanged.
H: Unpredictable.
N: Set to 1 when the adjusted result is negative;
otherwise cleared to 0.
Z: Set to 1 when the adjusted result is zero;
otherwise cleared to 0.
V: Unpredictable.
C: Set to 1 when there is a carry from bit 7;
otherwise left unchanged.
Description
When the result of an addition operation performed by the ADD.B or ADDX instruction on 4-bit
BCD data is contained in an 8-bit general register and the carry and half-carry flags, the DAA
instruction adjusts the result by adding H'00, H'06, H'60, or H'66 to the general register
according to the table below.
Valid results are not assured if this instruction is executed under conditions other than those
stated above.
Status before adjustment
C flag Upper nibble H flag Lower nibble
Value
added
Resulting
C flag
0
0
0
0
0
0
1
1
1
0 – 9
0 – 8
0 – 9
A – F
9 – F
A – F
0 – 2
0 – 2
0 – 3
0
0
1
0
0
1
0
0
1
0 – 9
A – F
0 – 3
0 – 9
A – F
0 – 3
0 – 9
A – F
0 – 3
H'00
H'06
H'06
H'60
H'66
H'66
H'60
H'66
H'66
0
0
0
1
1
1
1
1
1
Section 2 Instruction Set
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DAA (decimal adjust add) DAA
Instruction Formats and Number of Execution States
Register direct DAA Rd 0 F 0 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.24 DAS (decimal adjust subtract) DAS
Operation
Rd (decimal adjust) → Rd
Assembly-Language Format
DAS Rd
Operand Size
Byte
Condition Code
IHNZVC
* *
—— — —
I: Previous value remains unchanged.
H: Unpredictable.
N: Set to 1 when the adjusted result is negative;
otherwise cleared to 0.
Z: Set to 1 when the adjusted result is zero;
otherwise cleared to 0.
V: Unpredictable.
C: Previous value remains unchanged.
Description
When the result of a subtraction operation performed by the SUB.B, SUBX, or NEG instruction
on 4-bit BCD data is contained in an 8-bit general register and the carry and half-carry flags, the
DAA instruction adjusts the result by adding H'00, H'FA, H'A0, or H'9A to the general register
according to the table below.
Valid results are not assured if this instruction is executed under conditions other than those
stated above.
Status before adjustment
C flag Upper nibble H flag Lower nibble
Value
added
Resulting
C flag
0
0
1
1
0 – 9
0 – 8
7 – F
6 – F
0
1
0
1
0 – 9
6 – F
0 – 9
6 – F
H'00
H'FA
H'A0
H'9A
0
0
1
1
Instruction Formats and Number of Execution States
Register direct DAS Rd 1 F 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.25 DEC (decrement) DEC
Operation
Rd – 1 → Rd
Assembly-Language Format
DEC Rd
Operand Size
Byte
Condition Code
IHNZVC
—— ———
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs (the previous value in
Rd was H'80); otherwise cleared to 0.
C: Previous value remains unchanged.
Description
This instruction decrements an 8-bit general register and places the result in the general
register.
Instruction Formats and Number of Execution States
Register direct DEC Rd 1 A 0
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
rd 2
Section 2 Instruction Set
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2.2.26 DIVXU (divide extend as unsigned) DIVXU
Operation
Rd ÷ Rs → Rd
Assembly-Language Format
DIVXU Rs, Rd
Operand Size
Byte
Condition Code
IHNZVC
——— ———
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the divisor is negative;
otherwise cleared to 0.
Z: Cleared to 0 when divisor ≠ 0;
otherwise not guaranteed.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction divides a 16-bit general register by an 8-bit general register and places the result
in the 16-bit general register. The quotient is placed in the lower byte. The remainder is placed in
the upper byte. The operation is shown schematically below.
Rd Rs (RdH)
Dividend ÷Divisor →Remainder Quotient
16 bits 8 bits 8 bits 8 bits
(RdL)
Rd
Valid results (Rd, N, Z) are not assured if division by zero is attempted or an overflow occurs.
Division by zero is indicated in the Zero flag. Overflow can be avoided by the coding shown on
the next page.
Instruction Formats and Number of Execution States
Register direct DIVXU Rs, Rd 5 1 rs 0 rd 14
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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DIVXU (divide extend as unsigned) DIVXU
Note: DIVXU Overflow
Since the DIVXU instruction performs 16-bit ÷ 8-bit → 8-bit division, an overflow will occur if the
divisor byte is equal to or less than the upper byte of the dividend. For example, H'FFFF ÷ H'01
→ H'FFFF causes an overflow. (The quotient has more than 8 bits.)
Overflows can be avoided by using a subprogram like the following. A work register is required.
R0L Divisor
R1 Dividend
R1 Remainder Quotient (*1)
R1
R2 H'00 Dividend (High) (*2)
R1 Dividend (Low)
R2
R1
R2 (*4)
Dividend
P
artial remainder Quotient
(
High)
Remainder Quotient (Low)
Quotient
(*3)
DIVXU R0L, R1:
MOV.B #H'00, R2H
CMP.B R0L, R1H
BCC L1
DIVXU R0L, R1
(*1)
MOV.B R1L, R2L
BRA L2
L1
MOV.B R1H, R2L
(*2)
DIVXU R0L, R2
MOV.B R2H, R1H
(*3)
DIVXU R0L, R1
MOV.B R2L, R2H
MOV.B R1L, R2L
L2
RTS
(*4)
To perform
Partial remainder
Section 2 Instruction Set
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2.2.27 EEPMOV (move data to EEPROM) EEPMOV
Operation
if R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until R4L = 0
else next;
Assembly-Language Format
EEPMOV
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction moves a block of data from the memory location specified in general register R5
to the memory location specified in general register R6. General register R4L gives the byte
length of the block.
Data are transferred a byte at a time. After each byte transfer, R5 and R6 are incremented and
R4L is decremented. When R4L reaches 0, the transfer ends and the next instruction is
executed. No interrupt requests are accepted during the data transfer.
At the end of this instruction, R4L contains H'00. R5 and R6 contain the last transfer address +1.
The memory locations specified by general registers R5 and R6 are read before the block
transfer is performed.
Instruction Formats and Number of Execution States
EEPMOV 7 B 5 C 5 9 8 F 9+4n*
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
*n is the initial value in R4L (0 ≤ n ≤ 255). Although n bytes of data are transferred, memory is
accessed 2 (n +1) times, requiring 4 (n + 1) states.
Section 2 Instruction Set
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2.2.28 INC (increment) INC
Operation
Rd + 1 → Rd
Assembly-Language Format
INC Rd
Operand Size
Byte
Condition Code
IHNZVC
—— ———
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs (the previous value in
Rd was H'7F); otherwise cleared to 0.
C: Previous value remains unchanged.
Description
This instruction increments an 8-bit general register and places the result in the general register.
Instruction Formats and Number of Execution States
Register direct INC Rd 0 A 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.29 JMP (jump) JMP
Operation
(EAd) → PC
Assembly-Language Format
JMP <EA>
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction branches unconditionally to a specified destination address.
The destination address must be even.
Instruction Formats and Number of Execution States
Register indirect JMP @Rn 5 9 0 rn 0 4
Absolute address JMP @aa:16 5 A 0 0 abs. 6
Memory indirect JMP @@aa:8 5 B abs. 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.30 JSR (Jump to subroutine) JSR
Operation
PC → @-SP
(EAd) → PC
Assembly-Language Format
JSR <EA>
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction pushes the program counter onto the stack, then branches to a specified
destination address. The program counter value pushed on the stack is the address of the
instruction following the JSR instruction. The destination address must be even.
Instruction Formats and Number of Execution States
Register indirect JSR @Rn 5 D 0 rn 0
Absolute address JSR @aa:16 5 E 0 0 abs. 8
Memory indirect JSR @@aa:8 5 F abs. 8
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
6
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2.2.31 LDC (load to control register) LDC
Operation
(EAs) → CCR
Assembly-Language Format
LDC <EAs>, CCR
Operand Size
Byte
Condition Code
IHNZVC
I: Loaded from the source operand.
H: Loaded from the source operand.
N: Loaded from the source operand.
Z: Loaded from the source operand.
V: Loaded from the source operand.
C: Loaded from the source operand.
Description
This instruction loads the source operand contents into the condition code register (CCR). Bits 4
and 6 are loaded as well as the flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts are deferred
until after the next instruction.
Instruction Formats and Number of Execution States
Immediate LDC #xx:8, CCR 0 7 IMM
Register direct LDC Rs, CCR 0 3 0 rs
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
2
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2.2.32 (1) MOV (move data) (byte) MOV
Operation
Rs → Rd
Assembly-Language Format
MOV.B Rs, Rd
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction moves one byte of data from a source register to a destination register and sets
condition code flags according to the data value.
Instruction Formats and Number of Execution States
Register direct MOV.B Rs, Rd 0 C rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.32 (2) MOV (move data) (word) MOV
Operation
Rs → Rd
Assembly-Language Format
MOV.W Rs, Rd
Operand Size
Word
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction moves one word of data from a source register to a destination register and sets
condition code flags according to the data value.
Instruction Formats and Number of Execution States
Register direct MOV.W Rs, Rd 0 D 0 rs 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.32 (3) MOV (move data) (byte) MOV
Operation
(EAs) → Rd
Assembly-Language Format
MOV.B <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction moves one byte of data from a source operand to a destination register and sets
condition code flags according to the data value.
The MOV.B @R7+, Rd instruction should never be used, because it leaves an odd value in the
stack pointer. See section 3.2.3 for details.
Instruction Formats and Number of Execution States
Immediate MOV.B #xx:8, Rd F rd IMM 2
Register indirect MOV.B @RS, Rd 6 8 0 rs rd 4
Register indirect
with displacement MOV.B @(d:16,Rs),Rd 6 E 0 rs rd disp. 6
Register indirect
with post-increment MOV.B @Rs+, Rd 6 C 0 rs rd 6
Absolute address MOV.B @aa:8, Rd 2 rd abs 4
Absolute address MOV.B @aa:16, Rd 6 A 0 rd abs. 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.32 (4) MOV (move data) (word) MOV
Operation
(EAs) → Rd
Assembly-Language Format
MOV.W <EAs>, Rd
Operand Size
Word
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction moves one word of data from a source operand to a destination register and sets
condition code flags according to the data value.
If the source operand is in memory, it must be located at an even address.
MOV.W @R7+, Rd is identical in machine language to POP.W Rd.
Note that the LSIs in the H8/300L Series contain on-chip peripheral modules for which access in
word size is not possible. Details are given in the applicable hardware manual.
Instruction Formats and Number of Execution States
Immediate MOV.W #xx:16, Rd 7 9 0 0 rd IMM
Register indirect MOV.W @RS, Rd 6 9 0 rs 0 rd 4
4
Register indirect
with displacement MOV.W @(d:16,Rs),Rd 6 F 0 rs 0 rd disp. 6
Register indirect
with post-increment MOV.W @Rs+, Rd 6 D 0 rs 0 rd 6
Absolute address MOV.W @aa:16, Rd 6 B 0 0 rd abs. 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
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2.2.32 (5) MOV (move data) (byte) MOV
Operation
Rs → (EAd)
Assembly-Language Format
MOV.B Rs, <EAd>
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction moves one byte of data from a source register to memory and sets condition
code flags according to the data value.
The MOV.B Rs, @–R7 instruction should never be used, because it leaves an odd value in the
stack pointer. See section 3.2.3, Outline of Exception Handling Operation, for details.
The instruction MOV.B RnH, @–Rn or MOV.B RnL, @–Rn decrements register Rn, then moves
the upper or lower byte of the decremented result to memory.
Instruction Formats and Number of Execution States
Register indirect MOV.B Rs, @Rd 6 8 1 rd rs 4
Register indirect Rs,
with displacement MOV.B @(d:16,Rd) 6 E 1 rd rs disp. 6
Register indirect
with pre-decrement MOV.B Rs, @-Rd 6 C 1 rd rs 6
Absolute address MOV.B Rs,@aa:8 3 rs abs 4
Absolute address MOV.B Rs,@aa:16 6 A 8 rs abs. 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.32 (6) MOV (move data) (word) MOV
Operation
Rs → (EAd)
Assembly-Language Format
MOV.W Rs, <EAd>
Operand Size
Word
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction moves one word of data from a general register to memory and sets condition
code flags according to the data value.
The destination address in memory must be even.
MOV.W Rs, @–R7 is identical in machine language to PUSH.W Rs.
The instruction MOV.W Rn, @–Rn decrements register Rn by 2, then moves the decremented
result to memory.
Note that the LSIs in the H8/300L Series contain on-chip peripheral modules for which access in
word size is not possible. Details are given in the applicable hardware manual.
Instruction Formats and Number of Execution States
Register indirect MOV.W Rs, @Rd 6 9 1 rd 0 rs 4
Register indirect Rs,
with displacement MOV.W @(d:16, Rd) 6 F 1 rd 0 rs disp. 6
Register indirect
with pre-decrement MOV.W Rs, @-Rd 6 D 1 rd 0 rs 6
Absolute address MOV.W Rs, @aa:16 6 B 8 0 rs abs. 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.33 MULXU (multiply extend as unsigned) MULXU
Operation
Rd × Rs → Rd
Assembly-Language Format
MULXU Rs, Rd
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction performs 8-bit × 8-bit → 16-bit multiplication. It multiplies a destination register by
a source register and places the result in the destination register. The source register is an 8-bit
register. The destination register is a 16-bit register containing the data to be multiplied in the
lower byte. (The upper byte is ignored.) The result is placed in both bytes of the destination
register. The operation is shown schematically below.
Rd Rs Rd
Don't-care ×Multiplier → Product
8 bits 8 bits 16 bits
Multiplicand
The multiplier can occupy either the upper or lower byte of the source register.
Instruction Formats and Number of Execution States
Register direct MULXU Rs, Rd 5 0 rs 0 rd 14
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.34 NEG (negate) NEG
Operation
0 – Rd → Rd
Assembly-Language Format
NEG Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a borrow from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs (the previous contents
of the destination register was H'80);
otherwise cleared to 0.
C: Set to 1 when there is a borrow from bit 7 (the previous
contents of the destination register was not H'00);
otherwise cleared to 0.
Description
This instruction replaces the contents of an 8-bit general register with its two's complement
(subtracts the register contents from H'00).
If the original contents of the destination register was H'80, the register value remains H'80 and
the overflow flag is set.
Instruction Formats and Number of Execution States
Register direct NEG Rd 1 7 8 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
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2.2.35 NOP (no operation) NOP
Operation
PC + 2 → PC
Assembly-Language Format
NOP
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction only increments the program counter, causing the next instruction to be
executed. The internal state of the CPU does not change.
Instruction Formats and Number of Execution States
NOP 0 0 0 0 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.36 NOT (NOT = logical complement) NOT
Operation
¬ Rd → Rd
Assembly-Language Format
NOT Rd
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction replaces the contents of an 8-bit general register with its one’s complement
(subtracts the register contents from H'FF).
Instruction Formats and Number of Execution States
Register direct NOT Rd 1 7 0 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
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2.2.37 OR (inclusive OR logical) OR
Operation
Rd ∨ (EAs) → Rd
Assembly-Language Format
OR <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction ORs the source operand with the contents of an 8-bit general register and places
the result in the general register.
Instruction Formats and Number of Execution States
Immediate OR #xx:8, Rd C rd IMM 2
Register direct OR Rs, Rd 1 4 rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.38 ORC (inclusive OR control register) ORC
Operation
CCR ∨ #IMM → CCR
Assembly-Language Format
ORC #xx:8, CCR
Operand Size
Byte
Condition Code
IHNZVC
I: ORed with bit 7 of the immediate data.
H: ORed with bit 5 of the immediate data.
N: ORed with bit 3 of the immediate data.
Z: ORed with bit 2 of the immediate data.
V: ORed with bit 1 of the immediate data.
C: ORed with bit 0 of the immediate data.
Description
This instruction ORs the condition code register (CCR) with immediate data and places the result
in the condition code register. Bits 6 and 4 are ORed as well as the flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts are deferred
until after the next instruction.
Instruction Formats and Number of Execution States
Immediate ORC #xx:8, CCR 0 4 IMM
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.39 POP (pop data) POP
Operation
@SP+ → Rn
Assembly-Language Format
POP Rn
Operand Size
Word
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction pops data from the stack to a 16-bit general register and sets condition code
flags according to the data value.
POP.W Rn is identical in machine language to MOV.W @SP+, Rn.
Instruction Formats and Number of Execution States
POP Rd 6 D 7 0 rn 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.40 PUSH (push data) PUSH
Operation
Rn → @–SP
Assembly-Language Format
PUSH Rn
Operand Size
Word
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the data value is negative;
otherwise cleared to 0.
Z: Set to 1 when the data value is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction pushes data from a 16-bit general register onto the stack and sets condition
code flags according to the data value.
PUSH.W Rn is identical in machine language to MOV.W Rn, @–SP.
Instruction Formats and Number of Execution States
PUSH Rs 6 D F 0 rn 6
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.41 ROTL (rotate left) ROTL
Operation
Rd (rotated left) → Rd
Assembly-Language Format
ROTL Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 7.
Description
This instruction rotates an 8-bit general register one bit to the left. The most significant bit is
rotated to the least significant bit, and also copied to the carry flag.
The operation is shown schematically below.
C Bit 7 Bit 0
MSB LSB
Instruction Formats and Number of Execution States
Register direct ROTL Rd 1 2 8 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.42 ROTR (rotate right) ROTR
Operation
Rd (rotated right) → Rd
Assembly-Language Format
ROTR Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 0.
Description
This instruction rotates an 8-bit general register one bit to the right. The least significant bit is
rotated to the most significant bit, and also copied to the carry flag.
The operation is shown schematically below.
CBit 7 Bit 0
MSB LSB
Instruction Formats and Number of Execution States
Register direct ROTR Rd 1 3 8 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.43 ROTXL (rotate with extend carry left) ROTXL
Operation
Rd (rotated with carry left) → Rd
Assembly-Language Format
ROTXL Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 7.
Description
This instruction rotates an 8-bit general register one bit to the left through the carry flag. The
carry flag is rotated into the least significant bit of the register. The most significant bit rotates
into the carry flag.
The operation is shown schematically below.
C Bit 7 Bit 0
MSB
LSB
Instruction Formats and Number of Execution States
Register direct ROTXL Rd 1 2 0 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.44 ROTXR (rotate with extend carry right) ROTXR
Operation
Rd (rotated with carry right) → Rd
Assembly-Language Format
ROTXR Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 0.
Description
This instruction rotates an 8-bit general register one bit to the right through the carry flag. The
least significant bit is rotated into the carry flag. The carry flag rotates into the most significant
bit.
The operation is shown schematically below.
CBit 7 Bit 0
MSB LSB
Instruction Formats and Number of Execution States
Register direct ROTXR Rd 1 3 0 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.45 RTE (return from exception) RTE
Operation
@SP+ → CCR
@SP+ → PC
Assembly-Language Format
RTE
Operand Size
—
Condition Code
IHNZVC
I: Restored from stack.
H: Restored from stack.
N: Restored from stack.
Z: Restored from stack.
V: Restored from stack.
C: Restored from stack.
Description
This instruction returns from an exception-handling routine. It pops the condition code register
(CCR) and program counter (PC) from the stack. Program execution continues from the address
restored to the program counter.
The CCR and PC contents at the time of execution of this instruction are lost.
The CCR is one byte in size, but it is popped from the stack as a word (in which the lower 8 bits
are ignored). This instruction therefore adds 4 to the value of the stack pointer (R7).
Instruction Formats and Number of Execution States
RTE 5 6 7 0 10
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.46 RTS (return from subroutine) RTS
Operation
@SP+ → PC
Assembly-Language Format
RTS
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction returns from a subroutine. It pops the program counter (PC) from the stack.
Program execution continues from the address restored to the program counter.
The PC contents at the time of execution of this instruction are lost.
Instruction Formats and Number of Execution States
RTS 5 4 7 0
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
8
Section 2 Instruction Set
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2.2.47 SHAL (shift arithmetic left) SHAL
Operation
Rd (shifted arithmetic left ) → Rd
Assembly-Language Format
SHAL Rd
Operand Size
Byte
Condition Code
IHNZVC
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Receives the previous value in bit 7.
Description
This instruction shifts an 8-bit general register one bit to the left. The most significant bit shifts
into the carry flag, and the least significant bit is cleared to 0.
The operation is shown schematically below.
C Bit 7 Bit 0
0
MSB LSB
The SHAL instruction is identical to the SHLL instruction except for its effect on the overflow
(V) flag.
Instruction Formats and Number of Execution States
Register direct SHAL Rd 1 0 8 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.48 SHAR (shift arithmetic right) SHAR
Operation
Rd (shifted arithmetic right ) → Rd
Assembly-Language Format
SHAR Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 0.
Description
This instruction shifts an 8-bit general register one bit to the right. The most significant bit
remains unchanged. The sign of the result does not change. The least significant bit shifts into
the carry flag.
CBit 7 Bit 0
MSB LSB
The operation is shown schematically below.
Instruction Formats and Number of Execution States
Register direct SHAR Rd 1 1 8 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
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2.2.49 SHLL (shift logical left) SHLL
Operation
Rd (shifted logical left ) → Rd
Assembly-Language Format
SHLL Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 0.
Description
This instruction shifts an 8-bit general register one bit to the left. The least significant bit is
cleared to 0. The most significant bit shifts into the carry flag.
The operation is shown schematically below.
C Bit 7 Bit 0
0
MSB LSB
The SHLL instruction is identical to the SHAL instruction except for its effect on the overflow
(V) flag.
Instruction Formats and Number of Execution States
Register direct SHLL Rd 1 0 0 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 96 of 128
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2.2.50 SHLR (shift logical right) SHLR
Operation
Rd (shifted logical right ) → Rd
Assembly-Language Format
SHLR Rd
Operand Size
Byte
Condition Code
IHNZVC
0
—— ——
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 0.
Description
This instruction shifts an 8-bit general register one bit to the right. The most significant bit is
cleared to 0. The least significant bit shifts into the carry flag.
The operation is shown schematically below.
CBit 7 Bit 0
0
MSB LSB
Instruction Formats and Number of Execution States
Register direct SHLR Rd 1 1 0 rd
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 97 of 128
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2.2.51 SLEEP (sleep) SLEEP
Operation
Program execution state
→ power-down mode
Assembly-Language Format
SLEEP
Operand Size
—
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
When the SLEEP instruction is executed, the CPU enters a power-down mode. Its internal state
remains unchanged, but the CPU stops executing instructions and waits for an exception-
handling request (interrupt or reset). When it receives an exception-handling request, the CPU
exits the power-down mode and begins the exception-handling sequence.
If the interrupt mask (I) bit is set to 1, the power-down mode can be released only by a
nonmaskable interrupt (NMI) or reset.
For information about the power-down modes, see the applicable hardware manual.
Instruction Formats and Number of Execution States
SLEEP 0 1 8 0 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
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2.2.52 STC (store from control register) STC
Operation
CCR → Rd
Assembly-Language Format
STC CCR, Rd
Operand Size
Byte
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction copies the condition code register (CCR) to a specified general register. Bits 6
and 4 are copied as well as the flag bits.
Instruction Formats and Number of Execution States
Register direct STC CCR, Rd 0 2 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 99 of 128
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2.2.53 (1) SUB (subtract binary) (byte) SUB
Operation
Rd – Rs → Rd
Assembly-Language Format
SUB.B Rs, Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a borrow from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a borrow from bit 7;
otherwise cleared to 0.
Description
This instruction subtracts an 8-bit source register from an 8-bit destination register and places
the result in the destination register.
Only register direct addressing is supported. To subtract immediate data it is necessary to use
the SUBX.B instruction, first setting the zero flag to 1 and clearing the carry flag to 0.
The following codings can also be used to subtract nonzero immediate data.
(1) ORC #H'05, CCR (2) ADD #(0 – Imm), Rd
SUBX #(Imm – 1), Rd XORC #H'01, CCR
Instruction Formats and Number of Execution States
Register direct SUB.B Rs, Rd 1 8 rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 100 of 128
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2.2.53 (2) SUB (subtract binary) (word) SUB
Operation
Rd - Rs → Rd
Assembly-Language Format
SUB.W Rs, Rd
Operand Size
Word
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 when there is a borrow from bit 11;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
C: Set to 1 when there is a borrow from bit 15;
otherwise cleared to 0.
Description
This instruction subtracts a 16-bit source register from a 16-bit destination register and places
the result in the destination register.
Instruction Formats and Number of Execution States
Register direct SUB.W Rs, Rd 1 9 0 rs 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 101 of 128
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2.2.54 SUBS (subtract with sign extension) SUBS
Operation
Rd – 1 → Rd
Rd – 2 → Rd
Assembly-Language Format
SUBS #1, Rd
SUBS #2, Rd
Operand Size
Word
Condition Code
IHNZVC
————————
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Description
This instruction subtracts the immediate value 1 or 2 from word data in a general register.
Unlike the SUB instruction, it does not affect the condition code flags.
The SUBS instruction does not permit byte operands.
Instruction Formats and Number of Execution States
Register direct SUBS #1, Rd 1 B 0 0 rd 2
Register direct SUBS #2, Rd 1 B 8 0 rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 102 of 128
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2.2.55 SUBX (subtract with extend carry) SUBX
Operation
Rd – (EAs) – C → Rd
Assembly-Language Format
SUBX <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
—— —
I: Previous value remains unchanged.
H: Set to 1 if there is a borrow from bit 3;
otherwise cleared to 0.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Previous value remains unchanged when the result is
zero; otherwise cleared to 0.
V: Set to 1 when an overflow occurs;
otherwise cleared to 0.
Description
This instruction subtracts the source operand and carry flag from the contents of an 8-bit general
register and places the result in the general register.
Instruction Formats and Number of Execution States
Immediate SUBX #xx:8, Rd B rd IMM 2
Register direct SUBX Rs, Rd 1 E rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 103 of 128
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2.2.56 XOR (exclusive OR logical) XOR
Operation
Rd ⊕ (EAs) → Rd
Assembly-Language Format
XOR <EAs>, Rd
Operand Size
Byte
Condition Code
IHNZVC
———— 0 —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative;
otherwise cleared to 0.
Z: Set to 1 when the result is zero;
otherwise cleared to 0.
V: Cleared to 0.
C: Previous value remains unchanged.
Description
This instruction exclusive-ORs the source operand with the contents of an 8-bit general register
and places the result in the general register.
Instruction Formats and Number of Execution States
Immediate XOR #xx:8, Rd D rd IMM 2
Register direct XOR Rs, Rd 1 5 rs rd 2
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 104 of 128
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2.2.57 XORC (exclusive OR control register) XORC
Operation
CCR ⊕ #IMM → CCR
Assembly-Language Format
XORC #xx:8, CCR
Operand Size
Byte
Condition Code
IHNZVC
I: Exclusive-ORed with bit 7 of the immediate data.
H: Exclusive-ORed with bit 5 of the immediate data.
N: Exclusive-ORed with bit 3 of the immediate data.
Z: Exclusive-ORed with bit 2 of the immediate data.
V: Exclusive-ORed with bit 1 of the immediate data.
C: Exclusive-ORed with bit 0 of the immediate data.
Description
This instruction exclusive-ORs the condition code register (CCR) with immediate data and
places the result in the condition code register. Bits 6 and 4 are exclusive-ORed as well as the
flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts, including the
nonmaskable interrupt (NMI), are deferred until after the next instruction.
Instruction Formats and Number of Execution States
Immediate XORC #xx:8, CCR 0 5 IMM
Addressing
mode Mnem. Operands 1st byte
Instruction code No. of
states
2nd byte 3rd byte 4th byte
2
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 105 of 128
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2.3 Operation Code Map
Table 2-1 shows the operation code map for instructions of the H8/300L CPU. Only the first byte
(bits 15 to 8 of the first word) of the instruction code is indicated here.
Indicates that the most significant bit of the 2nd byte
(bit 7 of 1st word of instruction code) is 0.
Indicates that the most significant bit of the 2nd byte
(bit 7 of 1st word of instruction code) is 1.
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 106 of 128
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Table 2-1 Operation Code Map
HI LO 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
MULXU
BSET
SHLL
SHAL
SLEEP
BRN
DIVXU
BNOT
SHLR
SHAR
STC
BHI
BCLR
ROTXL
ROTL
LDC
BLS
BTST
ROTXR
ROTR
ORC
OR
BCC
RTS
XORC
XOR
BCS
BSR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND
BNE
RTE
LDC
BEQ
NOT
NEG
BLD
BILD
BST
BIST
ADD
SUB
BVC BVS
MOV
INC
DEC
BPL
JMP
ADDS
SUBS
BMI
EEPMOV
MOV
CMP
BGE BLT
ADDX
SUBX
BGT
JSR
DAA
DAS
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
MOV*
The PUSH and POP instructions are equivalent in machine language to the MOV instruction. See the descriptions of individual instructions in section 2.2, Instructions, for details.Note:
Bit manipulation instructions
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 107 of 128
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2.4 List of Instructions
Table 2-2 List of Instructions (1)
Mnemonic Operation HNIZVC
MOV.B #xx:8, Rd B #xx:8 →Rd8 2 — 2
MOV.B Rs, Rd B Rs8 →Rd8 2 — 2
MOV.B @Rs, Rd B @Rs16 →Rd8 2 — 4
MOV.B @(d:16, Rs), Rd B @(d:16, Rs16) →Rd8 4 — 6
MOV.B @Rs+, Rd B @Rs16 →Rd8 2 — 6
Rs16+1 →Rs16
MOV.B @aa:8, Rd B @aa:8 →Rd8 2 — 4
MOV.B @aa:16, Rd B @aa:16 →Rd8 4 — 6
MOV.B Rs, @Rd B Rs8 →@Rd16 2 — 4
MOV.B Rs, @(d:16, Rd) B Rs8 →@(d:16, Rd16) 4 — 6
MOV.B Rs, @–Rd B Rd16–1 →Rd16 2 — 6
Rs8 →@Rd16
MOV.B Rs, @aa:8 B Rs8 →@aa:8 2 4
MOV.B Rs, @aa:16 B Rs8 →@aa:16 4 — 6
MOV.W #xx:16, Rd W #xx:16 →Rd 4 — 4
MOV.W Rs, Rd W Rs16 →Rd16 2 — 2
MOV.W @Rs, Rd W @Rs16 →Rd16 2 — 4
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) →Rd16 4 — 6
MOV.W @Rs+, Rd W @Rs16 →Rd16 2 — 6
Rs16+2 →Rs16
MOV.W @aa:16, Rd W @aa:16 →Rd16 4 — 6
MOV.W Rs, @Rd W Rs16 →@Rd16 2 — 4
MOV.W Rs, @(d:16, Rd) W Rs16 →@(d:16, Rd16) 4 — 6
MOV.W Rs, @–Rd W Rd16–2 →Rd16 2 — 6
Rs16 →@Rd16
MOV.W Rs, @aa:16 W Rs16 →@aa:16 4 — 6
POP Rd W @SP →Rd16 2 — 6
SP+2 →SP
PUSH Rs W SP–2 →SP 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——6
Rs16 →@SP
Size
#
xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
0——
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 108 of 128
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Table 2-2 List of Instructions (2)
Mnemonic Operation HNIZVC
ADD.B #xx:8, Rd B Rd8+#xx:8 →Rd8 2 2
ADD.B Rs, Rd B Rd8+Rs8 →Rd8 2 2
ADD.W Rs, Rd W Rd16+Rs16 →Rd16 2 2
ADDX.B #xx:8, Rd B Rd8+#xx:8+C →Rd8 2 2
ADDX.B Rs, Rd B Rd8+Rs8+C →Rd8 2 2
ADDS.W #1, Rd W Rd16+1 →Rd16 2 2
ADDS.W #2, Rd W Rd16+2 →Rd16 2 2
INC.B Rd B Rd8+1 →Rd8 2 2
DAA.B Rd B
Rd8 decimal-adjust →Rd8
22
SUB.B Rs, Rd B Rd8–Rs8 →Rd8 2 2
SUB.W Rs, Rd W Rd16–Rs16 →Rd16 2 2
SUBX.B #xx:8, Rd B Rd8–#xx:8–C →Rd8 2 2
SUBX.B Rs, Rd B Rd8–Rs8–C →Rd8 2 2
SUBS.W #1, Rd W Rd16–1 →Rd16 2 2
2
2
2
2
2
2
2
SUBS.W #2, Rd W Rd16–2 →Rd16 2 2
DEC.B Rd B Rd8–1 →Rd8 2 2
2
2
DAS.B Rd B
Rd8 decimal-adjust →Rd8
2
NEG.B Rd B 0–Rd →Rd 2
2
2
CMP.B #xx:8, Rd B Rd8–#xx:8
CMP.B Rs, Rd B Rd8–Rs8 2 2
CMP.W Rs, Rd W Rd16–Rs16 2 2
MULXU.B Rs, Rd B Rd8×Rs8 →Rd16 2 14
DIVXU.B Rs, Rd B Rd16÷Rs8 →Rd16 2 14
(RdH: remainder,
RdL: quotient)
AND.B #xx:8, Rd B Rd8∧#xx:8 →Rd8 2
AND.B Rs, Rd B Rd8∧Rs8 →Rd8 2
OR.B #xx:8, Rd B Rd8∨#xx:8 →Rd8 2
OR.B Rs, Rd B Rd8∨Rs8 →Rd8 2
XOR.B #xx:8, Rd B Rd8⊕#xx:8 →Rd8 2
XOR.B Rs, Rd B Rd8⊕Rs8 →Rd8 2
NOT.B Rd B Rd →Rd 2
Size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
**
**
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—— —
—
—
—
—
—
—
—
—
—
—————
———
——
——
——
——
——
——
——
—
——
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(2)
(2)
(1)
(1)
(2)
(2)
(6)(5)
(3)
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 109 of 128
REJ09B0214-0200
Table 2-2 List of Instructions (3)
Mnemonic Operation HNIZVC
SHAL.B Rd B —— 22
2
2
2
2
2
2
2
2
2
4
4
4
4
SHAR.B Rd B —— 0
SHLL.B Rd B —— 0
SHLR.B Rd B —— 002
ROTXL.B Rd B —— 0
ROTXR.B Rd B —— 0
ROTL.B Rd B —— 0
ROTR.B Rd B —— 0
2
2
2
2
2
2
BSET #xx:3, Rd B (#xx:3 of Rd8) ←1—————— 2
BSET #xx:3, @Rd B (#xx:3 of @Rd16) ←1—————— 8
BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) ←1—————— 8
BSET Rn, Rd B (Rn8 of Rd8) ←1—————— 2
BSET Rn, @Rd B (Rn8 of @Rd16) ←1—————— 8
BSET Rn, @aa:8 B (Rn8 of @aa:8) ←1—————— 8
Size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
b
7
b
0
0C
C
b
7
b
0
b
7
b
0
0C
b
7
b
0
0
C
b
7
b
0
C
b
7
b
0
C
b
7
b
0
C
b
7
b
0
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 110 of 128
REJ09B0214-0200
Table 2-2 List of Instructions (4)
Mnemonic Operation H NIZVC
BCLR #xx:3, Rd B (#xx:3 of Rd8) ←0—————— 2
BCLR #xx:3, @Rd B (#xx:3 of @Rd16) ←0—————— 8
BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) ←0—————— 8
BCLR Rn, Rd B (Rn8 of Rd8) ←0—————— 2
BCLR Rn, @Rd B (Rn8 of @Rd16) ←0—————— 8
BCLR Rn, @aa:8 B (Rn8 of @aa:8) ←0—————— 8
BNOT #xx:3, Rd B (#xx:3 of Rd8) ←2
2
—————— 2
(#xx:3 of Rd8)
BNOT #xx:3, @Rd B (#xx:3 of @Rd16) ←4
4
—————— 8
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) ←4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
—————— 8
(#xx:3 of @aa:8)
BNOT Rn, Rd B (Rn8 of Rd8) ←2—————— 2
(Rn8 of Rd8)
BNOT Rn, @Rd B (Rn8 of @Rd16) ←4—————— 8
(Rn8 of @Rd16)
BNOT Rn, @aa:8 B (Rn8 of @aa:8) ←4—————— 8
(Rn8 of @aa:8)
BTST #xx:3, Rd B (#xx:3 of Rd8) →Z——— —— 2
BTST #xx:3, @Rd B (#xx:3 of @Rd16) →Z——— —— 6
BTST #xx:3, @aa:8 B (#xx:3 of @aa:8) →Z——— —— 6
BTST Rn, Rd B (Rn8 of Rd8) →Z——— —— 2
BTST Rn, @Rd B (Rn8 of @Rd16) →Z——— —— 6
BTST Rn, @aa:8 B (Rn8 of @aa:8) →Z——— —— 6
BLD #xx:3, Rd B (#xx:3 of Rd8) →C————— 2
BLD #xx:3, @Rd B (#xx:3 of @Rd16) →C————— 6
BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) →C————— 6
BILD #xx:3, Rd B (#xx:3 of Rd8) →C————— 2
BILD #xx:3, @Rd B (#xx:3 of @Rd16) →C————— 6
BILD #xx:3, @aa:8 B (#xx:3 of @aa:8) →C————— 6
BST #xx:3, Rd B C →(#xx:3 of Rd8) 2 —————— 2
BST #xx:3, @Rd B C →(#xx:3 of @Rd16) 4 —————— 8
BST #xx:3, @aa:8 B C →(#xx:3 of @aa:8) 4 —————— 8
Size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 111 of 128
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Table 2-2 List of Instructions (5)
Mnemonic Operation H NIZVC
BIST #xx:3, Rd B C →(#xx:3 of Rd8) 2 —————— 2
BIST #xx:3, @Rd B C →(#xx:3 of @Rd16) 4 —————— 8
BIST #xx:3, @aa:8 B C →(#xx:3 of @aa:8) 4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
—————— 8
BAND #xx:3, Rd B C∧(#xx:3 of Rd8) →C————— 2
BAND #xx:3, @Rd B C∧(#xx:3 of @Rd16) →C————— 6
BAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) →C————— 6
BIAND #xx:3, Rd B C∧(#xx:3 of Rd8) →C————— 2
BIAND #xx:3, @Rd B C∧(#xx:3 of @Rd16) →C————— 6
BIAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) →C————— 6
BOR #xx:3, Rd B C∨(#xx:3 of Rd8) →C————— 2
BOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) →C————— 6
BOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) →C————— 6
BIOR #xx:3, Rd B C∨(#xx:3 of Rd8) →C————— 2
BIOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) →C————— 6
BIOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) →C————— 6
BXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) →C————— 2
BXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) →C————— 6
BXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) →C————— 6
BIXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) →C————— 2
BIXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) →C————— 6
BIXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) →C————— 6
BRA d:8 (BT d:8) —PC ←PC+d:82 —————— 4
BRN d:8 (BF d:8) —PC ←PC+2 2
2
2
2
2
2
2
2
2
2
—————— 4
BHI d:8 — C∨Z = 0 —————— 4
BLS d:8 — C∨Z = 1 —————— 4
BCC d:8 (BHS d:8) — 0 —————— 4
BCS d:8 (BLO d:8) — 1 —————— 4
BNE d:8 —Z =
C =
C =
0—————— 4
BEQ d:8 —Z = 1 —————— 4
BVC d:8 —V = 0 —————— 4
BVS d:8 —V = 1 —————— 4
Size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
Branching
Condition
if condition
is true then
PC ←
PC+d:8
else next;
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 112 of 128
REJ09B0214-0200
Table 2-2 List of Instructions (6)
Mnemonic Operation H NIZVC
BPL d:8 —N = 0 —————— 4
BMI d:8 — N = 1 —————— 4
BGE d:8 — N⊕V = 0 —————— 4
BLT d:8 — N⊕V = 1 —————— 4
BGT d:8 —
Z∨(N⊕V) = 0
2—————— 4
BLE d:8 —
Z∨(N⊕V) = 1
2
2
2
2
2
—————— 4
JMP @Rn — PC ←Rn16 2 —————— 4
JMP @aa:16 — PC ←aa:16 4 —————— 6
JMP @@aa:8 — PC ←@aa:8 —————— 8
BSR d:8 — SP–2 →SP 2
2
—————— 6
PC →@SP
PC ←PC+d:8
JSR @Rn — SP–2 →SP 2 —————— 6
PC →@SP
PC ←Rn16
JSR @aa:16 — SP–2 →SP 4 —————— 8
PC →@SP
PC ←aa:16
JSR @@aa:8 SP–2 →SP 2 —————— 8
PC →@SP
PC ←@aa:8
RTS — PC ←@SP —————— 8
SP+2 →SP
RTE — CCR ←@SP 10
SP+2 →SP
PC ←@SP
SP+2 →SP
SLEEP — Transit to sleep mode. 2
2
2
—————— 2
2
2
2
2
LDC #xx:8, CCR B #xx:8 →CCR 2
LDC Rs, CCR B Rs8 →CCR 2
STC CCR, Rd B CCR →Rd8 2 —————— 2
ANDC #xx:8, CCR B CCR∧#xx:8 →CCR 2
ORC #xx:8, CCR B CCR∨#xx:8 →CCR 2
if condition
is true then
PC ←
PC+d:8
else next;
Size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
Branching
Condition
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 113 of 128
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Table 2-2 List of Instructions (7)
Mnemonic Operation H NIZVC
XORC #xx:8, CCR B CCR⊕#xx:8 →CCR 2
NOP —PC ←PC+2 2
4
—————— 2
(4)
2
EEPMOV —if R4L ≠0——————
Repeat @R5 →@R6
R5+1 →R5
R6+1 →R6
R4L–1 →R4L
Until R4L = 0
else next;
Notes: *The number of execution states indicated here assumes that the operation code and operand data are
in on-chip memory. For other cases, refer to section 2.5, Number of Execution States.
Set to 1 when there is a carry or borrow at bit 11; otherwise cleared to 0.
When the result is 0, the previous value remains unchanged; otherwise cleared to 0.
Set to 1 when there is a carry in the adjusted result; otherwise the previous value remains unchanged.
The number of execution states is 4n + 9, with n being the value set in R4L.
Set to 1 when the divisor is negative; otherwise cleared to 0.
Set to 1 when the divisor is 0; otherwise cleared to 0.
Size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of States*
Addressing Mode and
Instruction Length (Bytes)
Condition Code
(1)
(2)
(3)
(4)
(5)
(6)
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 114 of 128
REJ09B0214-0200
2.5 Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table 2-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation).
Table 2-4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables as
follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
1. BSET #0, @FF00
From table 2-4:
I = L = 2, J = K = M = N= 0
From table 2-3:
S I = 2, S L = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM,
and on-chip RAM is used for stack area.
2. JSR @@ 30
From table 2-4:
I = 2, J = K = 1, L = M = N = 0
From table 2-3:
S I = S J = S K = 2
Number of states required for execution = 2 × 2 + 1 × 2 + 1 × 2 = 8
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 115 of 128
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Table 2-3 Number of States Taken by Each Cycle in Instruction Execution
*Depends on which on-chip module is accessed. See the applicable hardware manual for
details.
Execution Status Access Location
(instruction cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch SI
Branch address read S
S
S
J
Stack operation K2
Byte data access SL2 or 3*
Word data access SM
Internal operation N1
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 116 of 128
REJ09B0214-0200
Table 2-4 Number of Cycles in Each Instruction
Instruction
Fetch
Branch
Addr.
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic IJKLMN
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
1
1
1
ADDS ADDS.W #1/2, Rd 1
ADDX ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
1
1
AND AND.B #xx:8, Rd
AND.B Rs, Rd
1
1
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
1
2
2
1
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 117 of 128
REJ09B0214-0200
Instruction
Fetch
Branch
Addr.
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic IJKLMN
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BIAND BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD BILD #xx:3, Rd
BILD #xx:3, @Rd
BILD #xx:3, @aa:8
1
2
2
1
1
BIOR BIOR #xx:3, Rd
BIOR #xx:3, @Rd
BIOR #xx:3, @aa:8
1
2
2
1
1
BIST BIST #xx:3, Rd
BIST #xx:3, @Rd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD BLD #xx:3, Rd
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
1
2
2
1
1
BNOT BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @Rd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 118 of 128
REJ09B0214-0200
Instruction
Fetch
Branch
Addr.
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic IJKLMN
BOR BOR #xx:3, Rd
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
1
2
2
1
1
BSET BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @Rd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BSR BSR d:8 2 1
BST BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
1
2
2
2
2
BTST BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
1
2
2
1
1
CMP CMP. B #xx:8, Rd
CMP. B Rs, Rd
CMP.W Rs, Rd
1
1
1
DAA DAA.B Rd 1
DAS DAS.B Rd 1
DEC DEC.B Rd 1
DIVXU DIVXU.B Rs, Rd 1 12
EEPMOV EEPMOV 2 2n + 2*1
INC INC.B Rd 1
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 119 of 128
REJ09B0214-0200
Instruction
Fetch
Branch
Addr.
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic IJKLMN
JMP JMP @Rn
JMP @aa:16
JMP @@aa:8
2
2
21
2
2
JSR JSR @Rn
JSR @aa:16
JSR @@aa:8
2
2
21
1
1
1
2
LDC LDC #xx:8, CCR
LDC Rs, CCR
1
1
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
1
1
11
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @-Rd
MOV.W Rs, @aa:16
2
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
MULXU MULXU.B Rs, Rd 1 12
Section 2 Instruction Set
Rev. 2.00 Dec 27, 2004 page 120 of 128
REJ09B0214-0200
Instruction
Fetch
Branch
Addr.
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic IJKLMN
NEG NEG.B Rd 1
NOP NOP 1
NOT NOT.B Rd 1
OR OR.B #xx:8, Rd
OR.B Rs, Rd
1
1
ORC ORC #xx:8, CCR 1
POP POP Rd 1 1 2
PUSH PUSH Rs 1 1 2
ROTL ROTL.B Rd 1
ROTR ROTR.B Rd 1
ROTXL ROTXL.B Rd 1
ROTXR ROTXR.B Rd 1
RTE RTE 2 2 2
RTS RTS 2 1 2
SHLL SHLL.B Rd 1
SHAL SHAL.B Rd 1
SHAR SHAR.B Rd 1
SHLR SHLR.B Rd 1
SLEEP SLEEP 1
STC STC CCR, Rd 1
SUB SUB.B Rs, Rd
SUB.W Rs, Rd
1
1
SUBS SUBS.W #1/2, Rd 1
SUBX SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
1
1
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd
1
1
XORC XORC #xx:8, CCR 1
* n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
Section 3 CPU Operation States
Rev. 2.00 Dec 27, 2004 page 121 of 128
REJ09B0214-0200
Section 3 CPU Operation States
There are three CPU operation states, namely, program execution state, power-down state, and
exception-handling state. In power-down state there are sleep mode, standby mode, and watch
mode. These operation states are shown in figure 3-1. Figure 3-2 shows the state transitions.
For further details please refer to the applicable hardware manual.
State Program execution state Active mode
The CPU executes successive program instructions,
synchronized by the system clock.
Subactive mode
The CPU executes
successive program
instructions in low-
speed operations,
synchronized by the
subclock.
Power-down state
Low-power modes
A state in which some or all
of the chip functions are
stopped to conserve power.
Sleep mode
Standby mode
Watch mode
Exception-handling state
A transient state in which the CPU changes
the
p
rocessin
g
flow due to a reset or an interru
p
t.
Figure 3-1 CPU Operation States
Section 3 CPU Operation States
Rev. 2.00 Dec 27, 2004 page 122 of 128
REJ09B0214-0200
Reset state
Power-down state
Exception-
handling state
Program
execution state
Reset cleared
SLEEP instruction executed
Reset occurs
Interrupt
raised
Interrupt
raised Interrupt handling
complete
Reset
occurs
Note: On the transitions between modes, see the applicable hardware manual.
Figure 3-2 State Transitions
3.1 Program Execution State
In program execution state the CPU executes program instructions in sequence.
3.2 Exception Handling States
Exception-handling states are transient states occurring when exception handling is raised by a
reset or interrupt, and the CPU changes its normal processing flow, branching to a start address
acquired from a vector table. In exception handling caused by an interrupt, PC and CCR values are
saved to the stack, with reference made to a stack pointer (R7).
3.2.1 Types and Priorities of Exception Handling
Exception handling includes processing of reset exceptions and of interrupts. Table 3-1
summarizes the factors causing each kind of exception, and their priorities. Reset exception
handling has the highest priority.
Section 3 CPU Operation States
Rev. 2.00 Dec 27, 2004 page 123 of 128
REJ09B0214-0200
Table 3-1 Types of Exception Handling and Priorities
Priority Exception source Detection timing Timing for start of exception
handling
High Reset Clock-synchronous Reset exception handling starts as
soon as RES pin changes from low to
high.
Low
Interrupt End of instruction*When an interrupt request is made,
execution* interrupt exception
handling starts after execution of the
present instruction is completed.
Note: *Interrupt detection is not made upon completion of ANDC, ORC, XORC, and LDC
instruction execution, nor upon completion of reset exception handling.
3.2.2 Exception Sources and Vector Table
The factors causing exception handling can be classified as in figure 3-3
For details of exception handling, the vector numbers of each source, and the vector addresses, see
the applicable hardware manual.
Exception source
Reset
Interrupt
External interrupt
Internal interrupt
(interrupt raised by on-chip peripheral module)
Figure 3-3 Classification of Exception Sources
Section 3 CPU Operation States
Rev. 2.00 Dec 27, 2004 page 124 of 128
REJ09B0214-0200
3.2.3 Outline of Exception Handling Operation
A reset has the highest priority of all exception handling. After the RES pin goes to low level
putting the CPU in reset state, the RES pin is then put at high level, and reset exception handling is
started at the point when the reset conditions are met. For details on reset conditions refer to the
applicable hardware manual. When reset exception handling is started, the CPU gets a start
address from the exception handling vector table, and starts executing the exception handling
routine from that address. During execution of this routine and immediately after, all interrupts
including NMI are masked.
When interrupt exception handling is started, the CPU refers to the stack pointer (R7) and pushes
the PC and CCR contents to the stack. The CCR I bit is then set to 1, a start address is acquired
from the exception handling vector table, and the interrupt exception handling routine is executed
from this address. The stack state in this case is as shown in figure 3-4.
Contents
saved to stack
SP (R7)
SP – 1
SP – 2
SP – 3
SP – 4
Stack SP + 4
SP + 3
SP + 2
SP + 1
SP (R7)
Even-numbered
address
Prior to start of interrupt
exception handling After completion of interrupt
exception handling
Notation
PC
H
:
PC
L
:
CCR:
SP:
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
* Ignored on return from interrupt
Notes:
CCR
CCR*
PC
H
PC
L
1.
2.
PC shows the address of the first instruction to be executed upon
return from the interrupt.
Saving and restoring of register contents must always be done
in word size, and must start from an even-numbered address.
Figure 3-4 Stack State after Completion of Interrupt Exception Handling
Section 3 CPU Operation States
Rev. 2.00 Dec 27, 2004 page 125 of 128
REJ09B0214-0200
3.3 Reset State
When the RES pin goes to low level, all processing stops and the system goes to reset state.
The I bit of the condition code register (CCR) is set, masking all interrupts.
After the RES pin is changed externally from low to high level, reset exception handling starts at
the point when the reset conditions are met. For details on reset conditions refer to the applicable
hardware manual.
3.4 Power-Down State
In power-down state the CPU operation is stopped, reducing power consumption. For details see
the applicable hardware manual.
Section 3 CPU Operation States
Rev. 2.00 Dec 27, 2004 page 126 of 128
REJ09B0214-0200
Section 4 Basic Operation Timing
Rev. 2.00 Dec 27, 2004 page 127 of 128
REJ09B0214-0200
Section 4 Basic Operation Timing
CPU operation is synchronized by a clock (f). The period from the rising edge of φ to the next
rising edge is called one state. A memory cycle or bus cycle consists of two or three states.
For details on access to on-chip memory and to on-chip peripheral modules see the applicable
hardware manual.
4.1 On-chip Memory (RAM, ROM)
Two-state access is employed for high-speed access to on-chip memory. The data bus width is 16
bits, allowing access in byte or word size. Figure 4-1 shows the on-chip memory access cycle.
φ
Internal address bus
Internal read signal
Internal data bus*
(read access)
Internal write signal
Internal data bus*
(write access)
Note:
Bus cycle
T
1
state T
2
state
Address
Read data
Write data
A 16-bit data bus is used making possible access to word-size
data in 2 states.
Figure 4-1 On-Chip Memory Access Cycle
Section 4 Basic Operation Timing
Rev. 2.00 Dec 27, 2004 page 128 of 128
REJ09B0214-0200
4.2 On-chip Peripheral Modules and External Devices
On-chip peripheral modules are accessed in two or three states. The data bus width is 8 bits, so
access is made in byte size only. Access to word data or instruction codes is not possible.
Figure 4-2 shows the on-chip peripheral module access cycle.
φ
Internal address bus
Internal read signal
Internal data bus*
(read access)
Internal write signal
Internal data bus*
(write access)
Note: An 8-bit data bus is used.
Bus cycle
T
1
state T
2
state
Address
Read data
Write data
(a) Two-state access
φ
Internal address bus
Internal read signal
Internal data bus*
(read access)
Internal write signal
Internal data bus*
(write access)
Bus cycle
T
1
state T
2
state
Address
Read data
Write data
(b) Three-state access
T
3
state
Figure 4-2 On-Chip Peripheral Module Access Cycle
Renesas 16-Bit Single-Chip Microcomputer
Software Manual
H8/300L Series
Publication Date: 1st Edition, December 1991
Rev.2.00, December 27, 2004
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Technical Documentation & Information Department
Renesas Kodaira Semiconductor Co., Ltd.
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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H8/300L Series
REJ09B0214-0200
Software Manual
