M25P05-AVMN6TP - Numonyx, B.V. - Datasheet.Directory

April 2008 Rev 11 1/52

M25P05-A

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Features

■512 Kbits of flash memory

■Page program (up to 256 bytes) in 1.4 ms

(typical)

■Sector erase (256 Kbits) in 0.65 s (typical)

■Bulk erase (512 Kbits) in 0.85 s (typical)

■2.3 to 3.6 V single supply voltage

■SPI bus compatible serial interface

■50 MHz clock ra te (maximum)

■Deep power-down mode 1 µA (typical)

■Electronic signatures

– JEDEC standard two-byte signature

(2010h)

– RES instruction, one-byte, signature (05h),

for backward compatibility

■More than 100,000 erase/program cycles per

sector

■More than 20 years data retention

■ECOPACK® packages available

SO8 (MN)

150 mil width

VFQFPN8 (MP)

(MLP8)

TSSOP8 (DW)

UFDFPN8 (MB)

2x3mm

www.numonyx.com

Contents M25P05-A

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Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12

4.4 Active power, standby power and deep power-down modes . . . . . . . . . . 12

4.5 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

M25P05-A Contents

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6.4 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.5 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.6 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.7 Read data by tes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 27

6.8 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.9 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.10 Bulk erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.11 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.12 Release from deep power-down and read electronic signature (RES) . . 33

7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

List of tables M25P05-A

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List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 14. Instruction times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 15. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 16. AC characteristics (40 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 17. AC characteristics (50 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 45

Table 19. VFQFPN8 (MLP8) - 8 lead very th in fine pitch quad flat package no lead,

6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 47

Table 21. UFDFPN8 (MLP8) – 8 lead ultra thin fi ne pitch dual flat package no lead,

2 x 3 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

M25P05-A List of figures

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List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SO, VFQFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21

Figure 10. Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 23

Figure 11. Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12. Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26

Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. Release from deep power-down and read electronic signature (RES)

instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 19. Release from deep power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23. Write protect setup and hold timing during WRSR when SRWD =1. . . . . . . . . . . . . . . . . . 43

Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 26. SO8N – 8 lead plastic small out line , 15 0 mils bod y wi dt h, pa ck ag e ou tlin e . . . . . . . . . . . . 45

Figure 27. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,

6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 29. UFDFPN8 (MLP8) – 8 lead ultra t hin fine pitch dual flat package no lead,

2 x 3 mm package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Description M25P05-A

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1 Description

The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write

protection mechanisms, accessed by a high speed SPI-compa tible bus.

The memory can be progra mmed 1 to 256 bytes at a time, using the page program

instruction.

The memory is organized as 2 sectors , each contain ing 128 page s . Each pag e is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.

The whole memory can be erased using the bulk erase instruction, or a sector at a time,

using the sector erase instruction.

Figure 1. Logic diagram

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data input Input

Q Serial Data output Output

SChip Select Input

W Write Protect Input

HOLD Hold Input

VCC Supply voltage Supply

VSS Ground Supply

AI05757

VCC

M25P05-A

HOLD

VSS

M25P05-A Description

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Figure 2. SO, VFQFPN and TSSOP connections

1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to

VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Package mechanical section for package dimensions, and how to identify pin-1.

AI05758B

5DVSS C

HOLDQ

M25P05-A

Signal descriptions M25P05-A

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2 Signal descriptions

2.1 Serial Data output (Q)

This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the device is desel ected and Serial Data outpu t (Q) is at high

impedance. Unless an internal program, erase or write status register cycle is in progress,

the de vice will be in the standby mode (this is not the deep pow er-down mode). Driving Chip

Select (S) Low enables the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any se rial communications with the de vice without

deselecting the device.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are don’t care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

2.6 Write Protect (W)

The main purpose of th is input sig na l is to free ze the size of the area of memory that is

protected against program or erase instructions (as specified by the values in the BP1 and

BP0 bits of the status register).

M25P05-A Signal descriptions

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2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

SPI modes M25P05-A

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3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two follo wing modes:

●CPOL=0, CPHA=0

●CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes , a s shown in Figure 4, is the clock polarity when the

bus mast er is in standb y mode and not transferring data:

●C remains at 0 for (CPOL=0, CPHA=0)

●C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus master and memory devices on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 3 shows a n examp le of three de vices connected t o an MCU , on an SPI bus . Only one

device is selected at a time, so only one device drives the Serial Data output (Q) line at a

time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure

that the M25P05 -A is no t selecte d if the bus master lea ves the S line in th e hi gh im pedan ce

state . As the bus master ma y enter a state wher e all inputs/outputs are in high impedance at

the same time (for example, when the bus master is reset), the clock line (C) must be

connected to an external pull-down resistor so that, when all inputs/outputs become high

impedance, the S line is pulled High while the C line is pulled Lo w ( thus ensuring that S a nd

C do not become High at the same time , and so, that the tSHCH requirement is met). The

typical v alue of R is 100 kΩ, assuming th at the tim e co nst an t R*Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the bus master leaves the

SPI bus in high impe dance.

AI12836b

SPI bus master

SPI memory

device

SDO

SDI

SCK

CQD

SPI memory

device

CQD

SPI memory

device

CQD

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

RR R

M25P05-A SPI modes

11/52

Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the b us

master never leaves the SPI bus in the high impedance state for a time period shorter than

5µs.

Figure 4. SPI modes supported

AI01438B

MSB

CPHA

CPOL

MSB

Operating features M25P05-A

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4 Operating features

4.1 Page programming

To progr am one data by te, two instructions are req uired: Write Enable (WREN), which is one

byte, and a page program (PP) sequence, which consists of four bytes plus data. This is

followed by the internal program cycle (of duration tPP).

To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

F or optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Section 6.8: Page

program (PP) and Table 14: Instruction times).

4.2 Sector erase and bulk erase

The page program (PP) instruction allows bits to be reset fro m 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achieved eit her a sector a t a time, using the sector er as e (SE) inst ruction, or thr ougho ut the

entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of

duration tSE or tBE).

The erase instruction must be preceded by a write enable (WREN) instruction.

4.3 Polling during a write, program or erase cycle

A further improvement in the time to write status register (WRSR), program (PP) or erase

(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP

, tSE, or tBE). The

write in progress (WIP) bit is provided in the status register so that the application program

can monitor its value, polling it to establish when the previous write cycle, program cycle or

erase cycle is comple te.

4.4 Active power, standby power and deep power-down modes

When Chip Select (S) is Low, the de vice is selected, and in the act ive power mode.

When Chip Select (S) is High, the d e vice is deselecte d, b ut could remain in the act iv e powe r

mode until all internal cycles have completed (program, erase, write status register). The

device then goes in to the standby power mode. The device consumption drops to ICC1.

The deep power-down mo de is en tere d when th e specific in struction (the de ep power-down

(DP) instruction) is executed. The device consumption drops further to ICC2. The device

remains in this mode until another specific instruction (the release from deep power-down

and read electronic signature (RES) instruction) is executed.

While in the deep power-down mode, the device ignores all write, program and erase

instructions (see Section 6.11: Deep power-down (DP)). This can be used as an extra

software protection mechanism, when the device is not in active use, to protect the device

from inadvertent write, program or erase instructions.

M25P05-A Operating features

13/52

4.5 Status register

The status register contains a number of status and control bits, as shown in Table 6, that

can be read or set (as appropriate) by specific instructions.

4.5.1 WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write status

4.5.2 WEL bit

The write enable latch (WEL) bit indicates the status of the inter nal wr ite enable latch.

4.5.3 BP1, BP0 bits

The bloc k protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against program and erase instructions.

4.5.4 SRWD bit

The status register write disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. Th e status register write disab le (SR WD) bit and Write Prot ect (W) signal

allow t he de vice to be put in the hardw are protected mode . In this mode, the non-vola tile bits

of the status register (SRWD, BP1, BP0) become read-only bits.

Operating features M25P05-A

14/52

4.6 Protection modes

The environments where non-volatile memory de vices are used can be very noisy. No SPI

device can operate correctly in the presence of e xcessive noise. To help combat this, the

M25P05-A features the following data protection mechanisms:

●Power on reset and an internal timer (tPUW) can provid e protection against inadve rtent

changes while the power supply is outside the operating specification

●Progr am, era se and write status registe r instructions are chec k ed tha t the y consist of a

number of clock pulses that is a multiple of eigh t, before they are accepted for

execution

●All instructions that modify data must be preceded by a write enable (WREN)

instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

– Write disable (WRDI) instruction completion

– Write status register (WRSR) instruction completion

– Page program (PP) instruction completion

– Sector erase (SE) instruction completion

– Bulk erase (BE) instruction completion

●The block protect (BP1, BP0) bits allow part of the memory to be configur ed as read-

only. This is the software protected mode (SPM)

●The Write Protect (W) signal, in co-operation with the status register write disable

(SRWD) bit, allows the block protect (BP1, BP0) bits and status register write disable

(SRWD) bit to be write-protected. This is the hardware protected mode (HPM)

●In addition to the low power consumption feature, the deep power-down mode offers

extra software protection, as all write, program and erase instructions are ignored.

1. The device is ready to accept a bulk erase instruction if, and only if, both block protect (BP1, BP0) are 0.

Table 2. Prote cted area sizes

Status Register

content Memory content

BP1 bit BP0 bit Protected area Unprotected area

0 0 none All sectors (sectors 0 and 1)

0 1 No protection against page program (PP) and sector erase (SE)

All sectors (sectors 0 and 1) protected against bulk erase (BE)

1 0

1 1 All sectors (sectors 0 and 1) none

M25P05-A Operating features

15/52

4.7 Hold condition

The Hold (HOLD) signal is used to pause any se rial communications with the de vice without

resetting the clocking sequence. However, taking this signal Low does not terminate any

write status register, program or erase cycle that is currently in progress.

To enter the hold condition, the device must be selected, with Chip Select (S) Low.

The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 5).

The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes

Low (this is shown in Figure 5).

During the hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are don’t care.

Normally, the de vice is k ept selected, with Chip Select (S) driv en Lo w, f or the whol e duratio n

of the hold condition. Th is is to ensure that the state of th e internal logic remains unchanged

from the moment of entering the hold condition.

If Chip Select (S) goes High while the device is in the hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the hold condition.

Figure 5. Hold condition activation

AI02029D

HOLD

Hold

condition

(standard use)

Hold

condition

(non-standard use)

Memory organization M25P05-A

16/52

5 Memory organization

The memory is organized as:

●65,536 bytes (8 bits each)

●2 sectors (256 Kbits, 32768 bytes each)

●256 pages (256 bytes each).

Each page can be individually pro grammed (bits are prog rammed from 1 to 0). The de vice is

sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.

Table 3. Memory organization

Sector Address range

1 08000h 0FFFFh

0 00000h 07FFFh

M25P05-A Memory organization

17/52

Figure 6. Block diagram

AI05759

HOLD

WControl logic High voltage

generator

I/O shift register

Address register

and counter 256 byte

data buffer

256 bytes (page size)

X decoder

Y decoder

Status

00000h

08000h

0FFFFh

000FFh

Size of the

read-only

memory area

Instructions M25P05-A

18/52

6 Instructions

All instruct ion s, addresses and dat a are shifted in and out of the device, most significant bit

first.

Serial Data input (D) is sampled on the first rising edge of Serial Cloc k (C ) afte r Ch ip Se lect

(S) is drive n L ow. Then, the one-byte instruction code must be shifte d in to the device, most

significant bit first, on Serial Data input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 4.

Every instruction sequence starts with a one-byte inst ruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

Chip Select (S) must be driven High after the last bit of the instruction sequence has been

shifted in.

In the case of a read data b yte s (READ), read data b ytes at higher speed (Fast_Read), read

identification (RDID), read status register (RDSR) or release from deep power-down, and

read electronic signature (RES) inst ruction, the shifted-in instruction sequence is followed

by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a page p rogr am (PP), sector er ase (SE), b ulk er ase (BE), write status regist er

(WRSR), write enable (WREN), write disable (WRDI) or deep power-down ( DP) instruction,

Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is

rejected, and is not exe cuted. That is , Chip Select (S) m ust d riv en High when t he n umber of

clock pulses after Chip Select (S) being driven Low is an exact multiple of eight.

All attempts to acce ss the memory array during a write status register cycle, program cycle

or erase cycle are ignored, and the internal write status register cycle, program cycle or

erase cycle continues unaffected.

M25P05-A Instructions

19/52

6.1 Write enable (WREN)

The write enable (WREN) instru ction (Figure 7) sets the write enable latch (WEL) bit.

The write enab le latch (WEL) b it must be set prior to e v ery page prog ram (PP), sect or era se

(SE), bulk erase (BE) and write status register (WRSR) instruction.

The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, an d then driving Chip Select (S) High.

Figure 7. Write enable (WREN) instruction sequence

Table 4. Instruction set

Instruction Description One-byte instruction

code Address

bytes Dummy

bytes Data

bytes

WREN Write enable 0000 0110 06h 0 0 0

WRDI Write disable 0000 0100 04h 0 0 0

RDID(1)

1. The read identification (RDID) instruction is available only in products with process technology code X and

Y (see application note AN1995).

Read identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read status register 0000 0101 05h 0 0 1 to ∞

WRSR Write status register 0000 0001 01h 0 0 1

READ Read data bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read data bytes at higher

speed 0000 1011 0Bh 3 1 1 to ∞

PP Pa ge program 0000 0010 02h 3 0 1 to 256

SE Sector erase 1101 1000 D8h 3 0 0

BE Bulk erase 1100 0111 C7h 0 0 0

DP Deep power-down 1011 1001 B9h 0 0 0

RES

Release from deep power-

down, and read electronic

signature 1010 1011 ABh 0 3 1 to ∞

Release from deep power-

down 0 0 0

AI02281E

21 34567

High Impedance

Instruction

Instructions M25P05-A

20/52

6.2 Write disable (WRDI)

The write disable (WRDI) instruction (Figure 8) resets the write enable latch (WEL) bit.

The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, an d then driving Chip Select (S) High.

The write enable latch (WEL) bit is reset under the following conditions:

●Power-up

●Write disable (WRDI) instruction completion

●Write status register (WRSR) instruction completion

●Page program (PP) instruction completion

●Sector erase (SE) instruction completion

●Bulk erase (BE) instruction completion.

Figure 8. Write disable (WRDI) instruction sequence

AI03750D

21 34567

High Impedance

Instruction

M25P05-A Instructions

21/52

6.3 Read identification (RDID)

The read identification (RDID) instruction is available in products with process technology

code X and Y.

The read identificat ion (RDID) instruction allows the 8-bit manufacturer identification to be

read, followed by two bytes of device identification. The manufacturer identification is

assigned by JEDEC, and has the value 20h for Numonyx. The device identification is

assigned by the device manufacturer, and indicates the memory type in the first byte (20h),

and the memor y capacity of the device in the second byte (10h).

Any read identification (RDID) instru ction while an erase or program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The read identificat ion (RDID) instruction should not be issued while the device is in deep

power-down mode.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. This is followed by the 24-bit device identification, stored in

the memory, being shifted out on Serial Data output (Q), each bit being shifted out during

the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 9.

The read identification (RDID) instruction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the standby power mode. Once in

the standb y po w er mode , the device waits to be selected, so t hat it ca n receiv e , deco de and

execute instructions.

Figure 9. Read identification (RDID) instru ction sequence and data-out sequence

Table 5. Read identificat ion (RDID) data-out sequence

Manufacturer identification Device identification

Memory type Memory capacity

20h 20h 10h

21 3456789101112131415

Instruction

AI06809b

Manufacturer identification

High Impedance

MSB

15 1413 3210

Device identification

MSB

16 17 18 28 29 30 31

Instructions M25P05-A

22/52

6.4 Read status register (RDSR)

The read stat us register ( RDSR) instruction allo ws the status re gister to be read. The status

is in progress. When one of these cycles is in progress, it is recommended to check the

write in progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the status register continuously, as shown in Figure 10.

The status and control bits of the status register are as follows:

6.4.1 WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write status

‘0’ no such cycle is in progress.

6.4.2 WEL bit

The write enable la tch (WEL) bit indicates t he status of the internal write enable latc h. When

set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is

reset and no write status register, program or erase instruction is accepted.

6.4.3 BP1, BP0 bits

The bloc k protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected again st program and erase instructions. These bits are written with the

write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0)

bits is set to ‘1’, the relevant memory area (as defined in Table 2) becomes protected

against page program (PP) and sector erase (SE) instructions. The block protect (BP1,

BP0) bits can be written provided that the hardware protected mode has not been set. The

bulk erase (BE) instruction is executed if, and only if, both block protect (BP1, BP0) bits are

6.4.4 SRWD bit

The status register write disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The stat us regist er write disable (SRWD) bit and write protec t (W) sig nal

allow the device to be put in the hardware protected mode (when the status register write

disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). I n this mode, the non-

volatile bits of the status register (SRWD, BP1, BP0) become read-only bits and the write

status register (WRSR) instruction is no longer accepted for execution.

Table 6. Status register format

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status register write protect

Block p r ot ect bits

Write enable latch bit

Write in progress bit

M25P05-A Instructions

23/52

Figure 10. Read status regist er (RDSR) instruction seque nce and data-o ut sequence

6.5 Write status register (WRSR)

The write status register (WRSR) instruction allows new values to be written to the status

been executed. After the write enable (WREN) instruction has been decoded and executed,

the device sets the write enable latch (WEL).

The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data input (D).

The instruction sequence is shown in Figure 11.

The write status register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of t he

status register. b6, b5 and b4 are alw ays read as 0.

Chip Select (S) must be driv en Hig h after the eighth bit of the d ata b yte has bee n latched in.

If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed write status register cycle (whose duration is tW) is initiated.

While the write status register cycle is in progress, the status register may still be read to

chec k the v a lue of the write in prog ress (WIP ) bit. The write in prog ress (WIP) bit is 1 during

the self-timed write status register cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the write enable latch (WEL) is reset.

The write status register (WRSR) instruction allows the user to change the values of the

bl ock pro tect (BP1, BP0) bits , to define the siz e of the area that is to be treated as read-o nly,

as defined in Table 2. The write status register (WRSR) instruction also allows the user to

set or reset the status register write disab le (SR WD) bit in accordance with the Write Protect

(W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allo w

the device to be put in the hardware protected mode (HPM). The write status register

(WRSR) instruction is not executed once the hardw are protected mode (HPM) is entered.

The protection features of the device are summarized in Table 7.

When the status register write disable (SRWD) bit of the status register is 0 (its initial

deliv ery state), it is possible to write to the stat us register provide d that the write enab le latch

(WEL) bit has pr eviously been set by a write enable (WREN) instruction, regardless of the

whether Write Protect (W) is driven High or Low.

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status register out

High Impedance

MSB

76543210

Status register out

MSB

Instructions M25P05-A

24/52

When the status register write disabl e (SRWD) bit of the sta tus register is set to ‘1’, two

cases need to be considered, depending on the state of Write Protect (W):

●If Write Protect (W) is driven High, it is possible to write to the status register provided

that the write enab le latch (WEL) bit ha s pre viously been set b y a write enab le (WREN)

instruction

●If Write Protect (W) is driven Low, it is not possible to write to the status register even if

the write enable latch (WEL) bit has previously been set by a write enable (WREN)

instruction (attempts to write to the status register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the b loc k protect (BP1, BP0) bits of the status r egister , are

also hardw are protected against data modification.

Regardless of the order of the two ev ents, the hardware protected mode (HPM) can be

entered:

●by set ting the status regist er write disable (SRWD) bit after driving Write Protect (W)

Low

●or by driving Write Protect (W) Low after settin g th e sta tu s re gist er write disable

(SRWD) bit.

The only way to exit the hardware protected mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can

never be activated, and only the software protected mode (SPM), using the block protect

(BP1, BP0) bits of the status register, can be used.

Figure 11. Write status register (WRSR) instruction sequence

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

M25P05-A Instructions

25/52

Table 7. Protection modes

signal SRWD

bit Mode Write protection of the status

Memory content

Protected

area(1)

1. As defined by the values in the block protect (BP1, BP0) bits of the status register, as shown in Table 2.

Unprotected

area(1)

Software

protected

(SPM)

Status regist er is writabl e (if th e

WREN instruction has set the WEL

bit).

The values in the SRWD, BP1 and

BP0 bits can be changed

Protected

against page

program, sector

erase and bulk

erase

Ready to

accept page

program and

sector erase

instructions

Hardware

protected

(HPM)

Status regist er is hardware write

protected.

The values in the SRWD BP1 and

BP0 bits cannot be changed

Protected

against page

program, sector

erase and bulk

erase

Ready to

accept page

program and

sector erase

instructions

Instructions M25P05-A

26/52

6.6 Read data bytes (READ)

The de vice is first selected by driving Chip Select (S) Low. The inst ruction co de for the read

data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum

frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifte d out. The whole memory can,

therefore, be read with a single read data bytes (READ) instruction.

There is no address roll-over; when the highest address (0FFFFh) is reached, the

instruction should be terminated.

The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any read data bytes (READ)

instruction, while an erase, program or write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Figure 12. Rea d data bytes (READ) instruction sequence and data-out sequence

1. Address bits A23 to A16 must be set to 00h.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data out 1

Instruction 24-bit address

MSB

Data out 2

M25P05-A Instructions

27/52

6.7 Read data bytes at higher speed (FAST_READ)

The de vice is first selected by driving Chip Select (S) Low. The inst ruction co de for the read

data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memo ry contents , at that addre ss, is shift ed out on Serial Data ou tput (Q), each b it

being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifte d out. The whole memory can,

therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.

There is no address roll-over; when the highest address (0FFFFh) is reached, the

instruction should be terminated.

The read data b ytes at hig her speed (FAST_READ) instruction is terminated by driving Chip

Select (S) High. Chip Select (S) can be driven High at an y time du ring data output. An y read

data bytes at higher speed (FAST_READ) instruction, while an erase, prog ram or write cycle

is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 13. R ead data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence

1. Address bits A23 to A16 must be set to 00h.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24-bit address

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

Instructions M25P05-A

28/52

6.8 Page program (PP)

The page prog ram (PP) instruction allo ws bytes to be pr ogrammed in the m emory (changing

bits from 1 to 0). Before it can be accepted, a write enable (WREN) instruction must

previously have been executed. After the write enable (WREN) instruction has been

decoded, the device sets the write enable latch (WEL).

The page prog ram (PP) instruction is entered b y driving Chip Select (S) Low, follo wed by the

instruction code, three address bytes and at least one data byte on Serial Data input (D). If

the 8 least significant address bit s (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

If more tha n 256 bytes are sent t o the device, previously latched data are disca rded an d th e

last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same p age.

F or optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Table 14: Instruction

times).

Chip Select (S) must be driven High after the eighth bit of the last data b yte has been

latched in, otherwise the page program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose

duration is tPP) is initiated. While the page program cycle is in progress, the status register

may be read to check the value of the write in progress (WIP) bit. The write in progress

(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is complet ed. At

some unspecified time before the cycle is completed, the write enable latch (WEL) bit is

reset.

A page program (PP) instruction applied t o a page which is protected by the block protect

(BP1, BP0) bits (see Table 3. and Table 2.) is not executed.

M25P05-A Instructions

29/52

Figure 14. Page pr ogram (PP) instruction sequence

1. Address bits A23 to A16 must be set to 00h.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-bit address

765432 0

Data byte 1

765432 0

Data byte 2

765432 0

Data byte 3 Data byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

Instructions M25P05-A

30/52

6.9 Sector erase (SE)

The sector er a se (SE) instruction sets to ‘1’ (FF h) all bits inside th e chosen sector. Bef or e it

can be accepted, a write enable (WREN) instruction must previously have been executed.

After the write enable (WREN) instruction has been decoded, the device sets the write

enable latch (WEL).

The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data input (D). Any address inside the

sector (see Table 3) is a valid address for the sector erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed sector er ase cycle (whose duration is tSE) is

initiated. While the sector erase cycle is in progress, the status register may be read to

chec k the v a lue of the write in prog ress (WIP ) bit. The write in prog ress (WIP) bit is 1 during

the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the write enable latch (WEL) bit is reset .

A sector erase (SE) instruction applied to a page which is protected by the block protect

(BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Figure 15. S ector erase (SE) instruction sequence

1. Address bits A23 to A16 must be set to 00h.

24-bit address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M25P05-A Instructions

31/52

6.10 Bulk erase (BE)

The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write

enable (WREN) instruction must previously hav e been executed. Afte r the write enable

(WREN) instruction has been decoded, the device sets the write enable latch (WEL).

The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)

is driven High, the self-timed bulk erase cycle (whose duration is tBE) is initiated. While the

bulk erase cycle is in progress, the status register may be read to check the value of the

write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk

erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the write enable latch (WEL) bit is reset.

The bulk erase (BE) instruction is executed only if both block protect (BP1, BP0) bits are 0.

The bulk erase (BE) instruction is ignored if one , or more, sectors are protected.

Figure 16. Bulk erase (BE) instruction sequence

AI03752D

21 345670

Instruction

Instructions M25P05-A

32/52

6.11 Deep power-down (DP)

Executing the deep power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the deep power-down mode). It can also be used as a software

protection me ch an ism , wh ile the device is not in active use, as in this mode, the device

ignores all write, program and erase inst ructions.

Driving Chip Select (S) High deselects the device, and puts the device in standby mode (if

there is no internal cycle currently in progress). But this mode is not the deep power-down

mode. The deep po wer- down mod e can only be entere d by ex ecuting the deep po we r-do wn

(DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified

in Table 13).

To take the device out of deep power-down mode, the release from deep power-down and

read electronic signature (RES) instruction must be issued. No other instruction must be

issued while the device is in deep power-down mode.

The release from deep po wer-do wn and read electr onic signature (RES) inst ruction, and the

read identification (RDID) instruction also allow the electronic signature of the device to be

output on Serial Data output (Q).

The deep power-down mode automatically stops at power-down, and the device always

powers-up in the standby mode.

The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP before the supply current is r educe d

to ICC2 and the deep power-down mode is entered.

Any deep power-down (DP) instruction, while an erase, program or write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Deep power-down (DP) instruction sequence

AI03753D

21 345670tDP

Deep power-down mode

Standby mode

Instruction

M25P05-A Instructions

33/52

6.12 Release from deep power-down and read electronic

signature (RES)

To take the device out of deep power-down mode, the release from deep power-down and

read electronic signature (RES) instruction must be issued. No other instruction must be

issued while the device is in deep power-down mode.

The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic

signature, whose value for the M25P05-A is 05h.

Except while an erase , program or write status registe r cycle is in progress , the release from

deep power-down and read electronic signature (RES) instruction always provides access

to the 8-bit electronic signature of the d evice, and can be applied even if the deep power-

down mode has not been entered.

Any rel ease from deep pow er-down and re ad electronic signature (RES) instruction wh ile an

erase, program or write status register cycle is in progress, is not decoded, and has no

effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. The instruction code is followed

by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge

of Serial Clock (C). Then, the 8-bit electronic sig nature, stored in the memory, is shifted out

on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 18.

The release from de ep power-down and read electronic signature (RES) instruction is

terminated by driving Chip Select (S) High after the electronic signature has been read at

least once. Sending additional clock cycles on Serial Clock (C), while Chip Se lect (S) is

driven Low, cause the electronic signature to be output repe atedly.

When Chip Select (S) is driven High, the device is put in the standby power mode. If the

de vice was not pre viously in the deep power- down mode, the transition to the st andby po wer

mode is immediate . If the device was previously in the deep pow er-d o wn mode , th ough, th e

transitio n to the standby power mode is de layed by t RES2, and Chip Select (S) must remain

High f or at least tRES2(max), as specified in Table 15. Once in the st an dby power mod e, the

device waits to be selected, so that it can receive, decode and execute instructions.

Driving Chip Select (S) High after the 8-bit instruction b yte has be en receiv ed b y the device,

but before the whole of the 8-bit el ectronic signature has been transmitted for the first time

(as shown in Figure 19), still ensures that the device is put into standby power mode. If the

de vice was not pre viously in the deep power- down mode, the transition to the st andby po wer

mode is immediate . If the device was previously in the deep pow er-d o wn mode , th ough, th e

transitio n to the standby power mode is de layed by t RES1, and Chip Select (S) must remain

High f or at least tRES1(max), as specified in Table 15. Once in the st an dby power mod e, the

device waits to be selected, so that it can receive, decode and execute instructions.

Instructions M25P05-A

34/52

Figure 18. Release from deep power-down and read electronic signature (RES)

instruction sequence and data-out sequence

1. The value of the 8-bit electronic signature, for the M25P05-A, is 05h.

Figure 19. Release fro m deep power-down (RES) instruction sequence

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic signature Out

Instruction 3 dummy bytes

MSB

Standby mode

Deep power-down mode

MSB

RES2

AI04078B

21 345670tRES1

Standby mode

Deep power-down mode

QHigh Impedance

Instruction

M25P05-A Power-up and power-down

35/52

7 Power-up and power-down

At power-up and powe r-down, the de vice must not be selected (that is Chip Select ( S) m ust

follow the voltage applied on VCC) until VCC reaches the correct value:

●VCC(min) at power-up, and then for a further delay of tVSL

●VSS at power-down

A safe configuration is provided in Section 3: SPI modes.

To av oid data corruption and inadvertent write operations during power-up , a power on reset

(POR) circuit is includ ed. T he logic in side th e d evice is held reset while VCC is less t han the

power on reset (POR) threshold voltage, VWI – all operations are disabled, and the device

does not respond to any instruction.

Moreover, the device ignores all write enable (WREN), page program (PP), sector erase

(SE), bulk erase (BE) and write status register (WRSR) instructions until a time delay of

tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the

correct opera tion of t he device is not guaranteed if, by this ti me , V CC is still belo w VCC(min).

No write status register, program or erase instructions should be sent until the later of:

●tPUW after VCC passed the VWI threshold

●tVSL after VCC passed the VCC(min) level

These values are specified in Ta ble 8.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for read instructions even if the tPUW delay is not yet fully elapsed.

At power-up, the device is in the following state:

●The device is in the standby mode (not the deep power-down mode )

●The write enab le latch (WEL) bit is reset

●The write in progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.

Each de vice in a system should ha v e the V CC rail decoupled b y a suitab le capacitor close to

the package pins (generally, this capacitor is of the or der of 100 nF).

At power-down, when VCC drops from the operating voltage, to below the power on reset

(POR) threshold voltage, VWI, all operations are disabled and the device does not respond

to any instruction (the designe r needs to be a ware th at if a pow er-down occur s while a write,

program or erase cycle is in progress , some data corruption can result).

Initial delivery state M25P05-A

36/52

Figure 20. Power-up timing

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte

contains FFh). The sta tus register co ntains 00h (all status register bits are 0).

Table 8. Power-up timing and VWI threshold

Symbol Parameter Min Max Unit

tVSL(1)

1. These parameters are characterized only.

VCC(min) to S low 10 µs

tPUW(1) Time delay to Write instruction 1 10 ms

VWI(1) Write inhibit voltage 1 2 V

VCC

AI04009C

VCC(min)

VWI

Reset state

of the

device

Chip selection not allowed

Program, erase and write commands are rejected by the device

tVSL

tPUW

time

Read access allowed Device fully

accessible

VCC(max)

M25P05-A Maximum ratings

37/52

9 Maximum ratings

Stressing the device above the rating listed in Table 9: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exp osur e to abso lute maximum rating conditions for

extended periods may affect device reliability.

Table 9. Absolute maximum ratings

Symbol Parameter Min Max Unit

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering see(1)

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances

(RoHS) 2002/95/EU.

°C

VIO Input and output voltage (with respect to ground) –0.6 VCC +0.6 V

VCC Supply voltage –0.6 4.0 V

VESD Electrostatic discharge voltage (human body

model)(2)

2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

–2000 2000 V

DC and AC parameters M25P05-A

38/52

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived fr om tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurem ent conditions when relying on the quoted parameters.

Figure 21. AC measurement I/O waveform

Table 10. Operating conditions

Symbol Parameter Min Max Unit

VCC Supply voltage 2.3(1)

1. Only in products with process technology code Y. In products with process technology code X, VCC(min) is

2.7 V.

3.6 V

TAAmbient operating temperature –40 85 °C

Table 11. AC measurement conditions(1)

1. Output Hi-Z is defined as the point where data out is no longer driven.

Symbol Parameter Min Max Unit

CLLoad capacitance 30 pF

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8VCC V

Input timing reference voltag es 0.3VCC to 0.7VCC V

Output timing reference voltages VCC / 2 V

Table 12. Capacitance(1)

1. Sampled only, not 100% tested, at TA= 25 °C and a frequency of 25 MHz.

Symbol Parameter Test condition Min Max Unit

COUT Output capacitance (Q) VOUT = 0 V 8 p F

CIN Input capacitance (other pins) VIN = 0 V 6 pF

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and output

timing reference levels

Input levels

0.5VCC

M25P05-A DC and AC parameters

39/52

Table 13. DC characteristics

Symbol Parameter Test condition (in addition to

those in Table 10.)Min Max Unit

ILI Input leakage current ± 2 µA

ILO Output leakage current ± 2 µA

ICC1 Standby current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep power-do wn current S = VCC, VIN = VSS or VCC 5µA

ICC3 Operating current (READ)

C = 0.1VCC / 0.9.VCC at 50 MHz,

Q = open 8mA

C = 0.1VCC / 0.9.VCC at 25 MHz,

Q = open 4mA

ICC4 Operating current (PP) S = VCC 15 mA

ICC5 Operating current (WRSR) S = VCC 15 mA

ICC6 Operating current (SE) S = VCC 15 mA

ICC7 Operating current (BE) S = VCC 15 mA

VIL Input low voltage – 0.5 0.3VCC V

VIH Input high voltage 0.7VCC VCC+0.4 V

VOL Output low voltage IOL = 1.6 mA 0.4 V

VOH Output high voltage IOH = –100 µAV

CC–0.2 V

Table 14 . Instruction times

Test conditions specified in Table 10 and Table 11.

Symbol Alt. Parameter Min Typ Max Unit

tWWrite status register cycle time 5 15 ms

tPP(1)

1. When using the page program (PP) instruction to program consecutive bytes, optimized timings are

obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤

256).

Page program cycle time (256 bytes) 1.4 5ms

Page program cycle time (n bytes) 0.4+n*1/256(2)

2. tPP=2µs+8µs*[int(n-1)/2+1]+4µs*[int(n-1)/2]+2µs, only in products with process technology code X and Y.

tSE Sector erase cycle time 0.65 3 s

tBE Bulk erase cycle time 0.85 6 s

DC and AC parameters M25P05-A

40/52

Table 15. AC characteristics (25 MHz operation)

Te st conditions specified in Table 10 and Table 11.

Symbol Alt. Parameter Min Typ Max Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,

RDSR, WRSR D.C. 25 MHz

fRClock frequency for read instructions D.C. 20 MHz

tCH(1)

1. tCH + tCL must be greater than or equal to 1/ fC.

tCLH Clock high time 18 ns

tCL(1) tCLL Clock low time 18 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

Clock rise time(3) (peak to peak)

3. Expressed as a slew-rate.

0.1 V/ns

tCHCL(2) Clock fall time(3) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 10 ns

tCHSL S not active hold time (relative to C) 10 ns

tDVCH tDSU Data in setup time 5 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 10 ns

tSHCH S not active setup time (relative to C) 10 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(2) tDIS Output disable time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO Output hold time 0 ns

tHLCH HOLD setup time (relative to C) 10 ns

tCHHH HOLD hold time (relative to C) 10 ns

tHHCH HOLD setup time (relative to C) 10 ns

tCHHL HOLD hold time (relative to C) 10 ns

tHHQX(2) tLZ HOLD to Output Low-Z 15 ns

tHLQZ(2) tHZ HOLD to Output High-Z 20 ns

tWHSL(4)

4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

Write protect setup time 20 ns

tSHWL(4) Write protect hold time 100 ns

tDP (2) S High to deep power-down mode 3 µs

tRES1(2) S High to standby mode without electronic signature

read 3µs

tRES2(2) S High to standby mode with electronic signature

read 1.8 µs

M25P05-A DC and AC parameters

41/52

Table 16. AC characteristics (40 MHz operation)

40 MH z available for products marked since week 20 of 2004, only(1)

Test conditions specified in Table 10. and Table 11.

1. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

Symbol Alt. Parameter Min Typ Max Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,

RDSR, WRSR D.C. 40 MHz

fRClock frequency for read instructions D.C. 20 MHz

tCH(2)

2. tCH + tCL must be greater than or equal to 1/ fC.

tCLH Clock high time 11 ns

tCL(2) tCLL Clock low time 11 ns

tCLCH(3)

3. Value guaranteed by characterization, not 100% tested in production.

Clock rise time(4) (peak to peak)

4. Expressed as a slew-rate.

0.1 V/ns

tCHCL(3) Clock fall time(4) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not active hold time (relative to C) 5 ns

tDVCH tDSU Data in setup time 2 ns

tCHDX tDH Data in hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(3) tDIS Output disa ble time 9 ns

tCLQV tVClock Low to Output Valid 9 ns

tCLQX tHO Output hold time 0 ns

tHLCH HOLD setup time (relative to C) 5 ns

tCHHH HOLD hold time (relative to C) 5 ns

tHHCH HOLD setup time (relative to C) 5 ns

tCHHL HOLD hold time (relative to C) 5 ns

tHHQX(3) tLZ HOLD to Output Low-Z 9 ns

tHLQZ(3) tHZ HOLD to Output High-Z 9 ns

tWHSL(5)

5. Details of how to find the date of marking are given in application note, AN1995.

Write protect setu p time 20 ns

tSHWL(1) Write protect hold time 100 ns

tDP(3) S High to deep power-down mode 3 µs

tRES1(3) S High to standby mode without electronic signature

read 3µs

tRES2(3) S High to standby mode with electronic signature read 1.8 µs

DC and AC parameters M25P05-A

42/52

Table 17. AC characteristics (50 MHz operation)

50 MHz available only in products with process technology code Y(1)(2)

Test conditions specified in Table 10 and Table 11.

Symbol Alt. Parameter Min Typ Max Unit

fCfCClock frequency(1) for the following instructions: FAST_READ,

PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz

fRClock frequency for read instructions D.C. 25 MHz

tCH(3) tCLH Cloc k high time 9 ns

tCL(3) tCLL Clock low time 9 ns

tCLCH(4) Clock rise time(5) (peak to peak) 0.1 V/ns

tCHCL(4) Clock f all time(5) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not active hold time (relative to C) 5 ns

tDVCH tDSU Data in setup time 2 ns

tCHDX tDH Data in ho l d ti me 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(4) tDIS Output disable time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output hold time 0 ns

tHLCH HOLD setup time (relative to C) 5 ns

tCHHH HOLD hold time (relative to C) 5 ns

tHHCH HOLD setup time (relative to C) 5 ns

tCHHL HOLD hold time (relative to C) 5 ns

tHHQX(4) tLZ HOLD to Output Low-Z 8 ns

tHLQZ(4) tHZ HOLD to Output High-Z 8 ns

tWHSL(6) Write protect setup time 20 ns

tSHWL(6) Write protect hold time 100 ns

tDP(4) S High to deep power-down mode 3 µs

tRES1(4) S High to standby mode without electronic signature read 30 µs

tRES2(4) S High to standby mode with electronic signature read 30 µs

1. Details of how to find the process on the device marking are given in application note AN1995.

2. 50 MHz operation is also available in products with process technology code X, but with a reduced supply voltage range

(2.7 to 3.6 V).

3. tCH + tCL must be greater than or equal to 1/ fC.

4. Value guaranteed by characterization, not 100% tested in production.

5. Expressed as a slew-rate.

6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.

M25P05-A DC and AC parameters

43/52

Figure 22. Serial input timing

Figure 23. Write protect setup and hold timing during WRSR when SRWD =1

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

DC and AC parameters M25P05-A

44/52

Figure 24. Hold timing

Figure 25. Output timing

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

AI01449e

LSB OUT

ADDR

.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

M25P05-A Package mechanical

45/52

11 Package mechanical

In order to mee t en viron mental requir ements , Numo nyx o ff er s these devices in ECOPA CK®

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ra tings related to soldering

conditions are also mark ed on the inner box label.

Figure 26. SO8N – 8 lead plasti c small outline, 150 mils body width, package outline

1. Drawing is not to scale.

Table 18 . SO8N – 8 lead plas tic small outline, 150 mils body width, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.750.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.28 0.48 0.011 0.019

c 0.17 0.23 0.007 0.009

ccc 0.10 0.004

D 4.90 4.80 5.00 0.193 0.189 0.197

E 6.00 5.80 6.20 0.236 0.228 0.244

E1 3.90 3.80 4.00 0.154 0.150 0.157

e1.27– –0.050– –

h 0.25 0.50 0.010 0.020

k0°8°0°8°

L 0.40 1.27 0.016 0.050

L1 1.04 0.041

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

Package mechanical M25P05-A

46/52

Figure 27. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat pack age no lead,

6 × 5 mm, package outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 19. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,

6 × 5 mm, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.033 0.031 0.039

A1 0.00 0.05 0.000 0.002

A2 0.65 0.026

A3 0.20 0.008

b 0.40 0.35 0.48 0.016 0.014 0.019

D6.00 0.236

D1 5.75 0.226

D2 3.40 3.20 3.60 0.134 0.126 0.142

E5.00 0.197

E1 4.75 0.187

E2 4.00 3.80 4.30 0.157 0.150 0.169

e1.27– –0.050– –

R1 0.10 0.00 0.004 0.000

L 0.60 0.50 0.75 0.024 0.020 0.029

Q 12° 12°

aaa 0.15 0.006

bbb 0.10 0.004

ddd 0.05 0.002

70-ME

AA3

eE2

ddd

bbb

CAB

aaa CA

aaa CB

0.10 CA

0.10 CB

M25P05-A Package mechanical

47/52

Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline

1. Drawing is not to scale.

Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 1.00 0.80 1.05 0.039 0.031 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.003 0.008

CP 0.10 0.004

D 3.00 2.90 3.10 0.118 0.114 0.122

e0.65– –0.026– –

E 6.40 6.20 6.60 0.252 0.244 0.260

E1 4.40 4.30 4.50 0.173 0.169 0.177

L 0.60 0.45 0.75 0.024 0.018 0.029

L1 1.00 0.039

α0° 8° 0° 8°

N8 8

TSSOP8AM

EE1

A2A

Package mechanical M25P05-A

48/52

Figure 29. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,

2 x 3 mm package outline

1. Drawing is not to scale.

Table 21. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,

2 x 3 mm package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.55 0.45 0.60 0.022 0.018 0.024

A1 0.02 0.00 0.05 0.001 0.000 0.002

b(1)

1. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.

0.25 0.20 0.30 0.010 0.008 0.012

D 2.00 1.90 2.10 0.079 0.075 0.083

D2 1.60 1.50 1.70 0.063 0.059 0.067

ddd(2)

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measuring.

0.08 0.003

E 3.00 2.90 3.10 0.118 0.114 0.122

E2 0.20 0.10 0.30 0.008 0.004 0.012

e0.50– –0.020– –

L 0.45 0.40 0.50 0.018 0.016 0.020

L1 0.15 0.006

L3 0.30 0.012

UFDFPN-01

A1 ddd

M25P05-A Ordering information

49/52

12 Ordering information

Note: F o r a list of available options (speed, pac k age, etc.) or f or fu rther information on an y aspect

of this device, please contact your nearest Numonyx sales office.

Table 22. Ordering information scheme

Example: M25P05-A V MN 6 T P

Device type

M25P

Device function

05-A = 512 Kbits (64 Kbit x8)

Operatin g voltage

V = VCC = 2.3 to 3.6 V

Package

MN = SO8 (150 mil width)

MP = VFQFPN8 (MLP8)

DW = TSSOP8(1)

1. The TSSOP8 package is available in products with process technology code X and Y (details of how to

find the process on the device marking are given in application note AN1995).

MB = UFDFPN8 (MLP8)

Temperature range

6 = –40 to 85 °C

Option

blank = standard packing

T = tape & reel packing

Plating technology

P or G = ECOPACK® (RoHS compliant)

Revision history M25P05-A

50/52

13 Revision history

Table 23 . Document revision history

Date Revision Changes

25-Feb-2001 1.0 Initial release.

11-Apr-2002 1.1 Clarification of descrip tions of entering Standby Power mode from Deep

Power-down mode, and of termi nating an instruction sequence or data-

out sequence.

12-Sep-2002 1.2 VFQFPN8 package (MLP8) added.

13-Dec-2002 1.3

Typical Page Program time improved. Write Protect setup and hold times

specified, for applications that switch Write Protect to exit the Hardware

Protection mode immediately before a WRSR, and to enter the Hardware

Protection mode again immediately after.

24-Nov-2003 2

Table of contents, warnin g about exposed paddle on MLP8, and Pb-free

options added.

40 MHz AC characteristics table included as well as 25 MHz. ICC3(max),

tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8

package

13-Jan-2005 3

Devices with process technology code X added ( Read identification

(RDID) and Table 17: AC characteristics (50 MHz operation)) add ed.

TSSOP8 package added.

Notes 1 and 2 removed from Table 22: Ordering information scheme and

Note 1 added.

Note 1 to Table 9: Absolute maximum ratings changed, note 2 and TLEAD

values removed.

Small text changes.

01-Apr-2005 4

F requency test condition modified f or ICC3 in Table 13: DC characteristics.

Read identification (RDID), Deep power-down (DP) and Release from

deep power-down and read electronic signature (RES) instructions and

Active power, standby power and deep power-down modes paragraph

clarified.

SO8 package specifications updated (see Figure 26. and Table 18).

01-Aug-2005 5 Updated Page Program (PP) instructions in Page programming, Page

program (PP) and Instru ction times .

06-Jul-2006 6

P ackages are fully ECOPACK® compliant. SO8N and VFQFPN8 package

specifications updated (see Section 11: Package mechanical).

Figure 3: Bus master and memory devices on the SPI b u s updated and

Note 2 added. TLEAD remov ed from Section Table 9.: Absolute maximum

ratings. Small text changes.

19-Dec-2006 7

VCC supply voltage and VSS ground descriptions added. Figure 3: Bus

master and memory devices on the SPI bus updated, note 2 removed

replaced by explanatory paragraph.

WIP bit behavior at power-up specified in Section 7: Power-up and po w er-

down. TLEAD added and VIO max modified in Table 9: Absolute maximum

ratings. VFQFPN8 and SO8N packages updated (see Section 11:

Package mechanical).

M25P05-A Revision history

51/52

07-Aug-2007 8

Removed ‘low voltage’ from the title. Small text changes.

Changed note below Table 12: Capacitance.

Changed the minimum value for VCC (from 2.7 to 2.3 V).

UFDFPN8 package (MLP8) added.

Frequency test condition modified for ICC3 in Table 13: DC characteristics.

tSE(typ), tBE(typ) and tPP(typ) values improved in Table 14: Instruction

times.

Changed maximum value for fR in Table 17: AC charac teristics (50 MHz

operation).

10-Oct-2007 9 Added the reference to a new process technology (code Y).

10-Dec-2007 10 Applied Numonyx branding.

18-Apr-2008 11 Updated Table 3: Bus master and memory devices on the SPI bus.

Modified the code for UFDFPN8 package from ‘ZW’ to ‘MB’.

Minor text changes.

Table 23. Document revision history (continued)

Date Revision Changes

M25P05-A

52/52

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