LMV1090TLX/NOPB - NATIONAL SEMICONDUCTOR

LMV1090

LMV1090 Dual Input, Far Field Noise Suppression Microphone Amplifier

Literature Number: SNAS472H

LMV1090

July 2, 2010

Dual Input, Far Field Noise Suppression Microphone

Amplifier

General Description

The LMV1090 is a fully analog dual differential input, differ-

ential output, microphone array amplifier designed to reduce

background acoustic noise, while delivering superb speech

clarity in voice communication applications.

The LMV1090 preserves near-field voice signals within 4cm

of the microphones while rejecting far-field acoustic noise

greater than 50cm from the microphones. Up to 20dB of far-

field rejection is possible in a properly configured and using

±0.5dB matched microphones.

Part of the Powerwise™ family of energy efficient solutions,

the LMV1090 consumes only 600μA of supply current pro-

viding superior performance over DSP solutions consuming

greater than ten times the power.

The dual microphone inputs and the processed signal output

are differential to provide excellent noise immunity. The mi-

crophones are biased with an internal low-noise bias supply.

Key Specifications

■Far Field Noise Suppression Electrical * 34dB (typ)

■SNRIE26dB (typ)

■Supply current 600μA (typ)

■Standby current 0.1μA (typ)

■Signal-to-Noise Ratio (Voice band) 65dB (typ)

■Total Harmonic Distortion + Noise 0.1% (typ)

■PSRR (217Hz) 99dB (typ)

*FFNSE at f = 1kHz

Features

■No loss of voice intelligibility

■No added processing delay

■Low power consumption

■Differential outputs

■Excellent RF immunity

■Adjustable 12 - 54dB gain

■Shutdown function

■Space-saving 16–bump micro SMD package

Applications

■Mobile headset

■Mobile and handheld two-way radios

■Bluetooth and other powered headsets

■Hand-held voice microphones

■Cell phones

System Diagram

30083340

LMV1090 Dual Input, Far Field Noise Suppression Microphone Amplifier

Typical Application

30083309

FIGURE 1. Typical Dual Microphone Far Field noise Cancelling Application

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LMV1090

Connection Diagrams

16–Bump micro SMD package

30083306

Top View

Order Number LMV1090TL

See NS Package Number TLA1611A

16–Bump micro SMD Marking

30083331

Top View

X = Plant Code

YY = Date Code

TT = Die Traceability

ZA3 = LMV1090TL

micro SMD Package View

30083303

Bottom View

Ordering Information

Order Number Package Package Drawing

Number Device Marking Transport Media

LMV1090TL 16 Bump µSMD TLA1611A XYTTZA3 250 units on tape and reel

LMV1090TLX 16 Bump µSMD TLA1611A XYTTZA3 1000 units on tape and reel

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LMV1090

Pin Descriptions

TABLE 1. Pin Name and Function

Bump Number Pin Name Pin Function Pin Type

A1 MIC1– Microphone 1 negative input Analog Input

A2 MIC1+ Microphone 1 positive input Analog Input

A3 MIC2– Microphone 2 negative input Analog Input

A4 MIC2+ Microphone 2 positive input Analog Input

B1 GND Amplifier ground Ground

B2 LPF+ Low Pass Filter for positive output Analog Input

B3 OUT+ Positive optimized audio output Analog Output

B4 REF Reference voltage de-coupling Analog Reference

C1 VDD Power supply Supply

C2 LPF- Low Pass Filter for negative output Analog Input

C3 OUT- Negative optimized audio output Analog Output

C4 Mic Bias Microphone Bias Analog Output

D1 EN Chip enable Digital input

D2 SDA I2C data Digital Input/Output

D3 SCL I2C clock Digital Input

D4 I2CVDD I2C power supply Supply

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LMV1090

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage 6.0V

Storage Temperature -85°C to +150°C

Power Dissipation (Note 3) Internally Limited

ESD Rating (Note 4) 2000V

ESD Rating (Note 5) 200V

CDM 500V

Junction Temperature (TJMAX) 150°C

Mounting Temperature

Infrared or Convection (20 sec.)

235°C

Thermal Resistance

θJA (microSMD) 70°C/W

Soldering Information See AN-112 “microSMD Wafers Level

Chip Scale Package.”

Operating Ratings (Note 1)

Supply Voltage 2.7V ≤ VDD ≤ 5.5V

I2CVDD

Supply Voltage (Note 8)

1.7V ≤ I2CVDD ≤ 5.5V

TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

Electrical Characteristics 3.3V (Note 1, Note 2)

Unless otherwise specified, all limits guaranteed for TA = 25°C, VDD = 3.3V, VIN = 18mVP-P, f = 1kHz, EN = VDD, Pre Amp gain =

20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, f = 1kHz pass through mode.

Symbol Parameter Conditions

LMV1090 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

SNR Signal-to-Noise Ratio

VIN = 18mVP-P

A-weighted, Audio band 63 dB

VOUT = 18VP-P,

voice band (300–3400Hz) 65 dB

eNInput Referred Noise level A-Weighted 5 μVRMS

VIN Maximum Input Signal THD+N < 1%, Pre Amp Gain = 6dB 880 820 mVP-P (min)

VOUT

Maximum AC Output Voltage Differential Out+, Out-

THD+N < 1% 1.2 1.1 VRMS (min)

DC Level at Outputs Out+, Out- 820 mV

THD+N Total Harmonic Distortion + Noise Differential Out+ and Out- 0.1 0.2 % (max)

ZIN Input Impedance 142 kΩ

ZOUT Output Impedance (Differential) 220 Ω

ZLOAD Load Impedance (Out+, Out-) (Note 10)RLOAD

CLOAD

100

kΩ (min)

pF (max)

AMMicrophone Preamplifier Gain Range minimum

maximum

36 dB

AMR Microphone Preamplifier Gain Adjustment Resolution 21.7

2.3

dB (min)

dB (max)

APPost Amplifier Gain Range minimum

maximum

18 dB

APR Post Amplifier Gain Resolution 3 2.6

3.4

dB (min)

dB (max)

FFNSEFar Field Noise Suppression Electrical f = 1kHz (See Test Method)

f = 300Hz (See Test Method)

26 dB

SNRIESignal-to-Noise Ratio Improvement Electrical f = 1kHz (See Test Method)

f = 300Hz (See Test Method)

18 dB

PSRR Power Supply Rejection Ratio

Input Referred, Input AC grounded

fRIPPLE = 217Hz (VRIPPLE = 100mVP-P)99 85 dB (min)

fRIPPLE = 1kHz (VRIPPLE = 100mVP-P)95 80 dB (min)

CMRR Common Mode Rejection Ratio input referred 60 dB

VBM Microphone Bias Supply Voltage IBIAS = 1.2mA 2.0 1.85

2.15

V (min)

V (max)

eVBM Mic bias noise voltage on VREF pin A-Weighted, CB = 10nF 7 μVRMS

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LMV1090

Symbol Parameter Conditions

LMV1090 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

IDDQ Supply Quiescent Current VIN = 0V 0.60 0.80 mA (max)

IDD Supply Current VIN = 25mVP-P both inputs

Noise cancelling mode 0.60 mA

ISD Shut Down Current EN pin = GND 0.1 0.7 μA (max)

IDDI2C I2C supply current I2C Idle Mode 25 100 nA (max)

TON Turn-On Time (Note 10) 40 ms (max)

TOFF Turn-Off Time (Note 10) 60 ms (max)

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LMV1090

Electrical Characteristics 5.0V (Note 1, Note 8)

Unless otherwise specified, all limits guaranteed for TA = 25°C, VDD = 5V, VIN = 18mVP-P, EN = VDD, Pre Amp gain = 20dB, Post

Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, f = 1kHz pass through mode.

Symbol Parameter Conditions LMV1090 Units

(Limits)

Typical Limit

(Note 6) (Note 7)

SNR Signal-to-Noise Ratio

VIN = 18mVP-P

A-weighted, Audio band 63 dB

VOUT = 18mVP-P,

voice band (300–3400Hz) 65 dB

eNInput Referred Noise level A-Weighted 5 μVRMS

VIN Maximum Input Signal THD+N < 1% 880 820 mVP-P (min)

VOUT

Maximum AC Output Voltage f = 1kHz, THD+N < 1%

between differential output 1.2 1.1 VRMS (min)

DC Output Voltage 820 mV

THD+N Total Harmonic Distortion + Noise Differential Out+ and Out- 0.1 0.2 % (max)

ZIN Input Impedance 142 kΩ

ZOUT Output Impedance 220 Ω

AMMicrophone Preamplifier Gain Range minimum

maximum

AMR Microphone Preamplifier Gain Adjustment Resolution 2 1.7

2.3

dB (min)

dB (max)

APPost Amplifier Gain Range minimum

maximum

APR Post Amplifier Gain Adjustment Resolution 3 2.6

3.4

dB (min)

dB (max)

FFNSEFar Field Noise Suppression Electrical f = 1kHz (See Test Method)

f = 300Hz (See Test Method)

26 dB

SNRIESignal-to-Noise Ratio Improvement Electrical f = 1kHz (See Test Method)

f = 300Hz (See Test Method)

18 dB

PSRR Power Supply Rejection Ratio

Input Referred, Input AC grounded

fRIPPLE = 217Hz (VRIPPLE = 100mVP-P)99 85 dB (min)

fRIPPLE = 1kHz (VRIPPLE = 100mVP-P)95 80 dB (min)

CMRR Common Mode Rejection Ratio input referred 60 dB

VBM Microphone Bias Supply Voltage IBIAS = 1.2mA 2.0 1.85

2.15

V ( min)

V (max)

eVBM Microphone bias noise voltage on VREF pin A-Weighted, CB = 10nF 7 μVRMS

IDDQ Supply Quiescent Current VIN = 0V 0.60 0.80 mA (max)

IDD Supply Current VIN = 25mVP-P both inputs

Noise cancelling mode 0.60 mA

ISD Shut Down Current EN pin = GND 0.1 μA

IDDI2C I2C supply current I2C Idle Mode 25 100 nA (max)

TON Turn On Time (Note 10) 40 mA (max)

TOFF Turn Off Time (Note 10) 60 ms (max)

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LMV1090

Digital Interface Characteristics I2C_VDD = 2.2V to 5.5V (Note 2, Note 8)

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2C_VDD ≤ 5.5V, unless otherwise specified.

Symbol Parameter Conditions

LMV1090 Units

(Limits)

Typical

(Note 4)

Limits

(Note 5, Note 7)

t1I2C Clock Period 2.5 µs (min)

t2I2C Data Setup Time 100 ns (min)

t3I2C Data Stable Time 0 ns (min)

t4Start Condition Time 100 ns (min)

t5Stop Condition Time 100 ns (min)

t6I2C Data Hold Time 100 ns (min)

VIH I2C Input Voltage High EN, SCL, SDA 0.7xI2CVDD V (min)

VIL I2C Input Voltage Low EN, SCL, SDA 0.3xI2CVDD V (max)

Digital Interface Characteristics I2C_VDD = 1.7V to 2.2V

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.

Symbol Parameter Conditions

LMV1090 Units

(Limits)

Typical

(Note 6)

Limits

(Note 7)

t1I2C Clock Period 2.5 µs (min)

t2I2C Data Setup Time 250 ns (min)

t3I2C Data Stable Time 0 ns (min)

t4Start Condition Time 250 ns (min)

t5Stop Condition Time 250 ns (min)

t6I2C Data Hold Time 250 ns (min)

VIH I2C Input Voltage High EN, SCL, SDA 0.7xI2CVDD V (min)

VIL I2C Input Voltage Low EN, SCL, SDA 0.3xI2CVDD V (max)

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJC, and the ambient temperature TA. The maximum

allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMV1090, TJMAX =

150°C and the typical θJA for this microSMD package is 70°C/W and for the LLP package θJA is 64°C/W Refer to the Thermal Considerations section for more

information.

Note 4: Human body model, applicable std. JESD22-A114C.

Note 5: Machine model, applicable std. JESD22-A115-A.

Note 6: Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 7: Datasheet min/max specification limits are guaranteed by test, or statistical analysis.

Note 8: The voltage at I2CVDD must not exceed the voltage on VDD.

Note 9: Default value used for performance measurements.

Note 10: Guaranteed by design.

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LMV1090

Test Methods

30083312

FIGURE 2. FFNSE, NFSLE, SNRIE Test Circuit

FAR FIELD NOISE SUPPRESSION (FFNSE)

For optimum noise suppression the far field noise should be

in a broadside array configuration from the two microphones

(see Figure 8). Which means the far field sound source is

equidistance from the two microphones. This configuration

allows the amplitude of the far field signal to be equal at the

two microphone inputs, however a slight phase difference

may still exist. To simulate a real world application a slight

phase delay was added to the FFNSE test. The block diagram

from Figure 3 is used with the following procedure to measure

the FFNSE.

1. A sine wave with equal frequency and amplitude

(25mVP-P) is applied to Mic1 and Mic2. Using a signal

generator, the phase of Mic 2 is delayed by 1.1° when

compared with Mic1.

2. Measure the output level in dBV (X)

3. Mute the signal from Mic2

4. Measure the output level in dBV (Y)

5. FFNSE = Y - X dB

NEAR FIELD SPEECH LOSS (NFSLE)

For optimum near field speech preservation, the sound

source should be in an endfire array configuration from the

two microphones (see Figure 9). In this configuration the

speech signal at the microphone closest to the sound source

will have greater amplitude than the microphone further away.

Additionally the signal at microphone further away will expe-

rience a phase lag when compared with the closer micro-

phone. To simulate this, phase delay as well as amplitude

shift was added to the NFSLE test. The schematic from Figure

3 is used with the following procedure to measure the NF-

SLE.

1. A 25mVP-P and 17.25mVP-P (0.69*25mVP-P) sine wave is

applied to Mic1 and Mic2 respectively. Once again, a

signal generator is used to delay the phase of Mic2 by

15.9° when compared with Mic1.

2. Measure the output level in dBV (X)

3. Mute the signal from Mic2

4. Measure the output level in dBV (Y)

5. NFSLE = Y - X dB

SIGNAL TO NOISE RATIO IMPROVEMENT ELECTRICAL

(SNRIE)

The SNRIE is the ratio of FFNSE to NFSLE and is defined as:

SNRIE = FFNSE - NFSLE

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LMV1090

Typical Performance Characteristics Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage

= 18mVP-P, f =1 kHz, pass through mode (Note 8), Pre Amp gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.

THD+N vs Frequency

Mic1 = AC GND, Mic2 = 36mVP-P

Noise Canceling Mode

30083319

THD+N vs Frequency

Mic2 = AC GND, Mic1 = 36mVP-P

Noise Canceling Mode

30083318

THD+N vs Frequency

Mic1 = 36mVP-P

Mic1 Pass Through Mode

30083317

THD+N vs Frequency

Mic2 = 36mVP-P

Mic2 Pass Through Mode

30083320

THD+N vs Input Voltage

Mic1 = AC GND, f = 1kHz

Mic2 Noise Canceling Mode

30083321

THD+N vs Input Voltage

Mic2 = AC GND, f = 1kHz

Mic1 Noise Canceling Mode

30083323

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LMV1090

THD+N vs Input Voltage

f = 1kHz

Mic1 Pass Through Mode

30083322

THD+N vs Input Voltage

f = 1kHz

Mic2 Pass Through Mode

30083325

PSRR vs Frequency

Pre Amp Gain = 20dB, Post Amp Gain = 6dB

VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND

Mic1 Pass Through Mode

30083314

PSRR vs Frequency

Pre Amp Gain = 20dB, Post Amp Gain = 6dB

VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND

Mic2 Pass Through Mode

30083315

PSRR vs Frequency

Pre Amp Gain = 20dB, Post Amp Gain = 6dB

VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND

Noise Canceling Mode

30083316

Far Field Noise Suppression Electrical vs Frequency

30083357

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LMV1090

Signal-to-Noise Ratio Electrical vs Frequency

30083358

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LMV1090

Application Data

INTRODUCTION

The LMV1090 is a fully analog single chip solution to reduce

the far field noise picked up by microphones in a communi-

cation system. A simplified block diagram is provided in

Figure 3.

30083324

FIGURE 3. Simplified Block Diagram of the LMV1090

The output signal of the microphones is amplified by a pre-

amplifier with adjustable gain between 6dB and 36dB. After

the signals are matched the analog noise cancelling sup-

presses the far field noise signal. The output of the analog

noise cancelling processor is amplified in the post amplifier

with adjustable gain between 6dB and 18dB. For optimum

noise and EMI immunity, the microphones have a differential

connection to the LMV1090 and the output of the LMV1090

is also differential. The adjustable gain functions can be con-

trolled via I2C.

Power Supply Circuits

A low drop-out (LDO) voltage regulator in the LMV1090 allows

the device to be independent of supply voltage variations.

The Power On Reset (POR) circuitry in the LMV1090 requires

the supply voltage to rise from 0V to VDD in less than 100ms.

The Mic Bias output is provided as a low noise supply source

for the electret microphones. The noise voltage on the Mic

Bias microphone supply output pin depends on the noise volt-

age on the internal the reference node. The de-coupling

capacitor on the VREF pin determines the noise voltage on this

internal reference. This capacitor should be larger than 1nF;

having a larger capacitor value will result in a lower noise

voltage on the Mic Bias output.

Most of the logic levels for the digital control interface are rel-

ative to I2CVDD voltage. This eases interfacing to the micro

controller of the application containing the LMV1090. The

supply voltage on the I2CVDD pin must never exceed the volt-

age on the VDD pin.

Only the four pins that determine the default power up gain

have logic levels relative to VDD.

Shutdown Function

As part of the Powerwise™ family, the LMV1090 consumes

only 0.50mA of current. In many applications the part does

not need to be continuously operational. To further reduce the

power consumption in the inactive period, the LMV1090 pro-

vides two individual microphone power down functions. When

either one of the shutdown functions is activated the part will

go into shutdown mode consuming only a few μA of supply

current.

SHUTDOWN VIA HARDWARE PIN

The hardware shutdown function is operated via the EN pin.

In normal operation the EN pin must be at a 'high' level

(VDD). Whenever a 'low' level (GND) is applied to the EN pin

the part will go into shutdown mode disabling all internal cir-

cuits.

Gain Balance and Gain Budget

In systems where input signals have a high dynamic range,

critical noise levels or where the dynamic range of the output

voltage is also limited, careful gain balancing is essential for

the best performance. Too low of a gain setting in the pream-

plifier can result in higher noise levels while too high of a gain

setting in the preamplifier will result in clipping and saturation

in the noise cancelling processor and output stages.

The gain ranges and maximum signal levels for the different

functional blocks are shown in Figure 4. Two examples are

given as a guideline on how to select proper gain settings.

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LMV1090

30083337

FIGURE 4. Maximum Signal Levels

Example 1

An application using microphones with 50mVP-P maximum

output voltage, and a baseband chip after the LMV1091 with

1.5VP-P maximum input voltage.

For optimum noise performance, the gain of the input stage

should be set to the maximum.

1. 50mVP-P +36 dB = 3.1VP-P.

2. 3.1VP-P is higher than the maximum 1.4VP-P allowed for

the Noise Cancelling Block (NCB). This means a gain

lower than 29.5dB should be selected.

3. Select the nearest lower gain from the gain settings

shown in Table 4, 28dB is selected. This will prevent the

NCP from being overloaded by the microphone. With this

setting, the resulting output level of the Pre Amplifier will

be 1.26VP-P.

4. The NCB has a gain of 0dB which will result in 1.26VP-P

at the output of the LMV1091. This level is less than

maximum level that is allowed at the input of the post amp

of the LMV1091.

5. The baseband chip limits the maximum output voltage to

1.5VP-P with the minimum of 6dB post amp gain, this

results in requiring a lower level at the input of the post

amp of 0.75VP-P. Now calculating this for a maximum

preamp gain, the output of the preamp must be no more

than 0.75VP-P.

6. Calculating the new gain for the preamp will result in

<23.5dB gain.

7. The nearest lower gain will be 22dB.

So using preamp gain = 22dB and postamp gain = 6dB is the

optimum for this application.

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LMV1090

Example 2

An application using microphones with 10mVP-P maximum

output voltage, and a baseband chip after the LMV1090 with

3.3VP-P maximum input voltage.

For optimum noise performance we would like to have the

maximum gain at the input stage.

1. 10mVP-P + 36dB = 631mVP-P.

2. This is lower than the maximum 1.5VP-P so this is OK.

3. The NCB has a gain of 0dB which will result in 1.5VP-P at

the output of the LMV1091. This level is lower than

maximum level that is allowed at the input of the Post

Amp of the LMV1091.

4. With a Post Amp gain setting of 6dB the output of the

Post Amp will be 3VP-P which is OK for the baseband.

5. The nearest lower Post Amp gain will be 6dB.

So using preamp gain = 36dB and postamp gain = 6dB is

optimum for this application.

I2C Compatible Interface

The LMV1090 is controlled through an I2C compatible serial

interface that consists of a serial data line (SDA) and a serial

clock (SCL). The clock line are uni-directional. *The LMV1090

and the master can communicate at clock rates up to 400kHz.

Figure 5 shows the I2C Interface timing diagram. Data on the

SDA line must be stable during the HIGH period of SCL. The

LMV1090 is a transmit/receive slave-only device, reliant upon

the master to generate the SCL signal. Each transmission

sequence is framed by a START condition and a STOP con-

dition (Figure 6). The data line is 8 bits long and is always

followed by an acknowledge pulse (Figure 7).

I2C Compatible Interface Power

Supply Pin (I2CVDD)

The LMV1090 I2C interface is powered up through the

I2CVDD pin. The LMV1090 I2C interface operates at a voltage

level set by the I2CVDD pin which can be set independent to

that of the main power supply pin VDD. This is ideal whenever

logic levels for the I2C Interface are dictated by a microcon-

troller or microprocessor that is operating at a lower supply

voltage than the main battery of a portable system.

I2C Bus Format

The I2C bus format is shown in Figure 7. The START signal,

the transition of SDA from HIGH to LOW while SCL is HIGH

is generated, alerting all devices on the bus that a device ad-

dress is being written to the bus. The 7-bit device address is

written to the bus, most significant bit (MSB) first followed by

the R/W bit, R/W = 0 indicates the master is writing to the slave

device, R/W = 1 indicates the master wants to read data from

the slave device. Set R/W = 0; the LMV1090 is a WRITE-

ONLY device and will not respond to the R/W = 1. The data

is latched in on the rising edge of the clock. Each address bit

must be stable while SCL is HIGH. After the last address bit

is transmitted, the mater device release SDA, during which

time, an acknowledge clock pulse is generated by the slave

device. If the LMV1090 receives the correct address, the de-

vice pulls the SDA line low, generating an acknowledge bit

(ACK)

Once the master device registers the ACK bit, the 8-bit reg-

ister data word is sent. Each data bit should be stable while

SCL is HIGH. After the 8-bit register data word is sent, the

LMV1090 sends another ACK bit. Following the acknowl-

edgement of the last register data word, the master issues a

STOP bit, allowing SDA to go high while SCL is high.

30083313

FIGURE 5. I2C Timing Diagram

*The data line is bi-directional (open drain)

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LMV1090

300833q2

FIGURE 6. I2C Start Stop Conditions

30083308

FIGURE 7. Start and Stop Diagram

TABLE 2. Chip Address

B7 B6 B5 B4 B3 B2 B1 B0/W

Chip Address 1 1 0 0 1 1 1 0

NOTE: The 7th Bit (B7) of the Register Data determines whether it will activate Register A or Register B.

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LMV1090

TABLE 3. I2C Register Description

Address

B[7] Reg. Bits Description Default

0 A

Gain setting for the pre amplifier from 6dB up to 36dB in 2dB steps

[3:0]

0000 6dB

0000

0001 8dB

0010 10dB

0011 12dB

0100 14dB

0101 16dB

0110 18dB

0111 20dB

1000 22dB

1001 24dB

1010 26dB

1011 28dB

1100 30dB

1101 32dB

1110 34dB

1111 36dB

Gain setting for the post amplifier from 6dB to 18dB in 3dB steps

[6:4]

000 6dB

000

001 9dB

010 12dB

011 15dB

100 18dB

101 18dB

110 18dB

111 18dB

1 B

[1:0] B[0] = mute mic 1 and B[1] = mute mic 2

( 0 = microphone on) 00

[3:2] Mic enable bits, B[3] = enable Mic 2, B[2] = enable Mic 1

(1 = enable), B3 and B2 both 0 = disable Mic 1 and Mic 2 00

Mic select bits

[5:4]

00 Noise cancelling mode

01 Only Mic 1 enabled (pass through)

10 Only Mic 2 enabled (pass through)

11 Mic 1 + Mic 2

[6] Not Used

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LMV1090

Microphone Placement

Because the LMV1090 is a microphone array Far Field Noise

Reduction solution, proper microphone placement is critical

for optimum performance. Two things need to be considered:

The spacing between the two microphones and the position

of the two microphones relative to near field source

If the spacing between the two microphones is too small near

field speech will be canceled along with the far field noise.

Conversely, if the spacing between the two microphones is

large, the far field noise reduction performance will be de-

graded. The optimum spacing between Mic 1 and Mic 2 is

1.5-2.5cm. This range provides a balance of minimal near

field speech loss and maximum far field noise reduction. The

microphones should be in line with the desired sound source

'near speech' and configured in an endfire array (see Figure

9) orientation from the sound source. If the 'near speech' (de-

sired sound source) is equidistant to the source like a broad-

side array (see Figure 8) the result will be a great deal of near

field speech loss.

30083343

FIGURE 8. Broadside Array (WRONG)

30083342

FIGURE 9. Endfire Array (CORRECT)

www.national.com 18

LMV1090

Low-Pass Filter At The Output

At the output of the LMV1090 there is a provision to create a

1st order low-pass filter (only enabled in 'Noise Cancelling'

mode). This low-pass filter can be used to compensate for the

change in frequency response that results from the noise

cancellation process. The change in frequency response re-

sembles a first-order high-pass filter, and for many of the

applications it can be compensated by a first-order low-pass

filter with cutoff frequency between 1.5kHz and 2.5kHz.

The transfer function of the low-pass filter is derived as:

This low-pass filter is created by connecting a capacitor be-

tween the LPF pin and the OUT pin of the LMV1090. The

value of this capacitor also depends on the selected output

gain. For different gains the feedback resistance in the low-

pass filter network changes as shown in Table 4.

This will result in the following values for a cutoff frequency of

2000 Hz:

TABLE 4. Low-Pass Filter Capacitor For 2kHz

Post Amplifier Gain Setting (dB) Rf (kΩ) Cf (nF)

6 20 3.9

9 29 2.7

12 40 2.0

15 57 1.3

18 80 1.0

A-Weighted Filter

The human ear is sensitive for acoustic signals within a fre-

quency range from about 20Hz to 20kHz. Within this range

the sensitivity of the human ear is not equal for each frequen-

cy. To approach the hearing response, weighting filters are

introduced. One of those filters is the A-weighted filter.

The A-weighted filter is used in signal to noise measurements,

where the wanted audio signal is compared to device noise

and distortion.

The use of this filter improves the correlation of the measured

values to the way these ratios are perceived by the human

ear.

30083310

FIGURE 10. A-Weighted Filter

19 www.national.com

LMV1090

Measuring Noise and SNR

The overall noise of the LMV1090 is measured within the fre-

quency band from 10Hz to 22kHz using an A-weighted filter.

The Mic+ and Mic- inputs of the LMV1090 are AC shorted

between the input capacitors, see Figure 11.

30083311

FIGURE 11. Noise Measurement Setup

For the signal to noise ratio (SNR) the signal level at the out-

put is measured with a 1kHz input signal of 18mVP-P using an

A-weighted filter. This voltage represents the output voltage

of a typical electret condenser microphone at a sound pres-

sure level of 94dB SPL, which is the standard level for these

measurements. The LMV1090 is programmed for 26dB of to-

tal gain (20dB preamplifier and 6dB postamplifier) with only

Mic1 or Mic2 used. (See also I2C Compatible Interface).

The input signal is applied differentially between the Mic+ and

Mic-. Because the part is in Pass Through mode the low-pass

filter at the output of the LMV1090 is disabled.

www.national.com 20

LMV1090

Revision History

Rev Date Description

1.0 07/01/09 Initial released.

1.01 07/10/09 Deleted the Limit values (on Zin) from both the 3.3V and 5V EC tables.

1.02 07/30/09 Edited the package dimensions (X1, X2, and X3).

1.03 09/02/09 Deleted the “Measurement Setup” paragraph.

1.04 10/12/09 Text edits.

1.05 10/15/09 Deleted the input limits on Zin (both from the 3.3V and 5.0V).

1.06 10/29/09 Text edits.

1.07 07/02/10 Edited curves 30083357 and 30083358.

21 www.national.com

LMV1090

www.national.com 22

LMV1090

Physical Dimensions inches (millimeters) unless otherwise noted

16 Bump micro SMD Technology

NS Package Number TLA1611A

X1 = 1970µm X2 = 1970µm X3 = 600µm

23 www.national.com

LMV1090

Notes

LMV1090 Dual Input, Far Field Noise Suppression Microphone Amplifier

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