February 2002 Advance Information AS7C1024A AS7C31024A (R) 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) Features * Latest 6T 0.25u CMOS technology * Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages * AS7C1024A (5V version) * AS7C31024A (3.3V version) * Industrial and commercial temperatures * Organization: 131,072 words x 8 bits * High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - 300 mil SOJ 400 mil SOJ 8 x 20mm TSOP 1 8 x 13.4mm sTSOP 1 * ESD protection 2000 volts * Latch-up current 200 mA - 660 mW (AS7C1024A) / max @ 10 ns - 324 mW (AS7C31024A) / max @ 10 ns * Low power consumption: STANDBY Pin arrangement - 55 mW (AS7C1024A) / max CMOS - 36 mW (AS7C31024A) / max CMOS Logic block diagram NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND VCC GND Input buffer A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 I/O0 Control circuit A9 A10 A11 A12 A13 A14 A15 A16 Column decoder 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32-pin (8 x 20mm) TSOP I 32-pin (8 x 13.4mm) sTSOP1 WE OE CE1 CE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1024A AS7C31024A 512x256x8 Array (1,048,576) Sense amp I/O7 Row decoder A0 A1 A2 A3 A4 A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1024A AS7C31024A 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Selection guide -10 Maximum address access time Maximum output enable access time AS7C1024A Maximum operating current AS7C31024A AS7C1024A Maximum CMOS standby current AS7C31024A 2/15/02; 0.9.7 10 5 120 90 10 10 -12 12 6 110 80 10 10 Alliance Semiconductor -15 15 7 100 80 10 10 -20 20 8 100 75 15 15 Unit ns ns mA mA mA mA P. 1 of 9 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1024A AS7C31024A (R) Functional description The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024A is guaranteed not to exceed 36mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter AS7C1024A AS7C31024A Both Both Both Both Both Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 -0.50 - -65 -55 - Max +7.0 +5.0 VCC +0.50 1.0 +150 +125 20 Unit V V V W C C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = Don't Care, L = Low, H = High 2/15/02; 0.9.7 Alliance Semiconductor P. 2 of 9 AS7C1024A AS7C31024A (R) Recommended operating conditions Parameter Device AS7C1024A AS7C31024A ASAS7C1024A AS7C31024A Supply voltage Input voltage commercial industrial Ambient operating temperature Symbol VCC VCC VIH VIH VIL1 TA TA Min 4.5 3.0 2.2 2.0 -0.5 0 -40 Nominal 5.0 3.3 - - - - - Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V C C 1 VILmin. = -3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range) -10 Parameter Input leakage current Output leakage current Operating power supply current -15 -20 Unit Sym Test conditions Device Min Max Min Max Min Max Min Max |ILI| VCC = Max, VIN = GND to VCC Both - 1 - 1 - 1 - 1 A 1 - 1 - 1 - 1 A 120 - 110 - 100 - 100 90 - 80 - 80 - 75 30 - 25 - 20 - 20 30 - 25 - 20 - 20 10 - 10 - 10 - 15 10 - 10 - 10 - 15 0.4 - - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - |ILO| ICC ISB Standby power supply current ISB1 Output voltage -12 VOL VOH VCC = Max, CE1 = VIH or Both - CE2 = VIL, VOUT = GND to VCC VCC = Max, CE1 = VIL, AS7C1024A - CE2 = VIH, f = fMax, IOUT = 0 AS7C31024A - mA VCC = Max, CE1 VIH and/or AS7C1024A - CE2 VIL, VIN = VIH or VIL, AS7C31024A - f = fMax, IOUT = 0mA VCC = Max, CE1 VCC-0.2V AS7C1024A - VIN GND + 0.2V or AS7C31024A - VIN VCC -0.2V, f = 0 IOL = 8 mA, VCC = Min - Both IOH = -4 mA, VCC = Min 2.4 mA mA mA V V Capacitance (f = 1 MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance 2/15/02; 0.9.7 Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Alliance Semiconductor Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF P. 3 of 9 AS7C1024A AS7C31024A (R) Read cycle (over the operating range) Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 Low to output in low Z CE2 High to output in low Z CE1 Low to output in high Z CE2 Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time -10 Min Max 10 - - 10 - 10 - 10 - 5 2 - 0 - 0 - - 3 - 3 0 - - 3 0 - - 10 Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD -12 Min Max 12 - - 12 - 12 - 12 - 6 3 - 0 - 0 - - 3 - 3 0 - - 3 0 - - 12 -15 Min Max 15 - - 15 - 15 - 15 - 7 3 - 0 - 0 - - 4 - 4 0 - - 4 0 - - 15 -20 Min Max 20 - - 20 - 20 - 20 - 8 3 - 0 - 0 - - 5 - 5 0 - - 5 0 - - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 3 3, 12 3, 12 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 Key to switching waveforms Rising input Falling input Undefined / don't care Read waveform 1 (address controlled) tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE1, CE2, and OE controlled) tRC1 CE1 CE2 tOE OE DOUT Current supply 2/15/02; 0.9.7 tOHZ tCHZ1, tCHZ2 tOLZ tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% Alliance Semiconductor ICC ISB P. 4 of 9 AS7C1024A AS7C31024A (R) Write cycle (over the operating range) Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Write recovery time Symbol tWC tCW1 tCW2 tAW tAS tWP tWR Min 10 8 8 8 0 7 0 Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end tAH tDW tDH tWZ tOW 0 5 0 - 1 -10 Max - - - - - - - -12 Min Max 12 - 10 - 10 - 9 - 0 - 8 - 0 - - - - 6 - 0 6 0 - 1 -15 Min Max 15 - 12 - 12 - 10 - 0 - 9 - 0 - - - - 6 - 0 8 0 - 1 - - - 6 - -20 Min Max 20 - 12 - 12 - 12 - 0 - 12 - 0 - 0 10 0 - 2 - - - 8 - Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes 12 12 12 4, 5 4, 5 4, 5 Write waveform 1 (WE controlled) tWC tWR tAH tAW Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CE1 and CE2 controlled) tAW tWC tAH tWR Address tAS tCW1, tCW2 CE1 CE2 tWP WE tWZ DIN tDW tDH Data valid DOUT 2/15/02; 0.9.7 Alliance Semiconductor P. 5 of 9 AS7C1024A AS7C31024A (R) AC test conditions - - - - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V +3.3V 480W +3.0V GND 90% 10% 90% 2 ns 10% Figure A: Input pulse DOUT 255W C(14) GND Figure B: 5V Output load 320W DOUT 255W C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE1 and OE are Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except all high Z and low Z parameters, C=5pF. 2/15/02; 0.9.7 Alliance Semiconductor P. 6 of 9 AS7C1024A AS7C31024A (R) Typical DC and AC Characteristcs 1.4 1.0 0.8 0.6 0.4 ISB 0.2 0.0 MIN NOMINAL Supply voltage (V) 0.4 ISB 625 25 1 0.2 0.04 -10 35 80 125 Ambient temperature (C) -55 Ta = 25 C 1.1 1.0 0.9 1.2 1.3 Normalized ICC 1.2 VCC = VCC(NOMINAL) 1.2 1.1 1.0 0.9 0.8 MIN NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH 140 Output sink current (mA) 100 80 VCC = VCC(NOMINAL) 60 Ta = 25 C 40 20 0 VCC Output voltage (V) 2/15/02; 0.9.7 0.6 VCC = VCC(NOMINAL) 0.4 Ta = 25 C 0.0 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading 35 30 120 100 VCC = VCC(NOMINAL) 80 Ta = 25 C 60 40 25 VCC = VCC(NOMINAL) 20 15 10 5 20 0 0 0 0.8 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL 140 120 1.0 0.2 0.8 -55 MAX -10 35 80 125 Ambient temperature (C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.4 1.4 1.3 VCC = VCC(NOMINAL) 5 Normalized access time tAA vs. ambient temperature Ta 1.5 Normalized access time Normalized access time 0.6 0.0 -55 MAX 1.4 Output source current (mA) 0.8 0.2 Normalized access time tAA vs. supply voltage VCC 1.5 ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC 0 VCC Output voltage (V) Alliance Semiconductor 0 250 500 750 Capacitance (pF) 1000 P. 7 of 9 AS7C1024A AS7C31024A (R) Package dimensions D e E1 E2 B Pin 1 c A A1 A2 b Seating Plane E b e c D Hd A2 L pin 1 A A1 pin 32 A A1 A2 B b c D E E1 E2 e 32-pin SOJ 300 mil Min Max 0.145 0.025 0.086 0.105 0.026 0.032 0.014 0.020 0.006 0.013 0.820 0.830 0.250 0.275 0.292 0.305 0.330 0.340 0.050 BSC A A1 A2 b c D e E Hd L E 2/15/02; 0.9.7 pin 16 32-pin SOJ 400 mil Min Max 0.145 0.025 0.086 0.115 0.026 0.032 0.015 0.020 0.007 0.013 0.820 0.830 0.360 0.380 0.395 0.405 0.435 0.445 0.050 BSC 32-pin TSOP 8x20 mm Min Max - 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.10 0.21 18.20 18.60 0.50 nominal 7.80 8.20 19.80 20.20 0.50 0 0.70 5 pin 17 Alliance Semiconductor P. 8 of 9 ASAS7C1024A ASAS7C31024A (R) Ordering codes Package \ Access time Plastic SOJ, 300 mil Plastic SOJ, 400 mil TSOP1 8x20 mm sTSOP1 8 x 13.4mm Volt/Temp 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial 5V commercial 5V industrial 3.3V commercial 3.3V industrial 10 ns 12 ns 15 ns 20 ns AS7C1024A-10TJC AS7C1024A-12TJC AS7C1024A-15TJC AS7C1024A-20TJC AS7C1024A-10TJI AS7C1024A-12TJI AS7C1024A-15TJI AS7C1024A-20TJI AS7C31024A-10TJC AS7C31024A-12TJC AS7C31024A-15TJC AS7C31024A-20TJC AS7C31024A-10TJI AS7C31024A-12TJI AS7C31024A-15TJI AS7C31024A-20TJI AS7C1024A-10JC AS7C1024A-12JC AS7C1024A-15JC AS7C1024A-20JC AS7C1024A-10JI AS7C1024A-12JI AS7C1024A-15JI AS7C1024A-20JI AS7C31024A-10JC AS7C31024A-12JC AS7C31024A-15JC AS7C31024A-20JC AS7C31024A-10JI AS7C31024A-12JI AS7C31024A-15JI AS7C31024A-20JI AS7C1024A-10TC AS7C1024A-12TC AS7C1024A-15TC AS7C1024A-20TC AS7C1024A-10TI AS7C1024A-12TI AS7C1024A-15TI AS7C1024A-20TI AS7C31024A-10TC AS7C31024A-12TC AS7C31024A-15TC AS7C31024A-20TC AS7C31024A-10TI AS7C31024A-12TI AS7C31024A-15TI AS7C31024A-20TI AS7C1024A-10STC AS7C1024A-12STC AS7C1024A-15STC AS7C1024A-20STC AS7C1024A-10STI AS7C1024A-12STI AS7C1024A-15STI AS7C1024A-20STI AS7C31024A-10STC AS7C31024A-12STC AS7C31024A-15STC AS7C31024A-20STC AS7C31024A-10STI AS7C31024A-15STI AS7C31024A-20STI AS7C31024A-12STI Part numbering system AS7C X 1024A -XX SRAM prefix Blank=5V CMOS 3=3.3V CMOS Device number Access time 2/15/02; 0.9.7 X Package:T=TSOP1 8x20 mm ST=sTSOP1 8 x 13.4 mm J=SOJ 400 mil TJ=SOJ 300 mil Alliance Semiconductor X Temperature range C = Commercial, 0C to 70C I = Industrial, -40C to 85C P. 9 of 9 (c) Copyright A lliance Sem iconductor Corporation. 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