NCP1380CDR2G - ON Semiconductor L.L.C.

June, 2012 − Rev. 4

1Publication Order Number:

NCP1380/D

NCP1380

Quasi-Resonant

Current-Mode Controller for

High-Power Universal

Off-Line Supplies

The NCP1380 hosts a high−performance circuitry aimed to

powering quasi−resonant converters. Capitalizing on a proprietary

valley−lockout system, the controller shifts gears and reduces the

switching frequency as the power loading becomes lighter. This

results in a stable operation despite switching events always occurring

in the drain−source valley. This system works down to the 4th valley

and toggles to a variable frequency mode beyond, ensuring an

excellent standby power performance.

To improve the safety in overload situations, the controller includes

an Over Power Protection (OPP) circuit which clamps the delivered

power at high−line. Safety−wise, a fixed internal timer relies on the

feedback voltage to detect a fault. Once the timer elapses, the

controller stops and stays latched for option A and C or enters

auto−recovery mode for option B and D.

Particularly well suited for adapter applications, the controller

features a pin to implement either a combined overvoltage /

overtemperature protection (Version A and B) or a combined

brown−out/overvoltage protection (Version C and D).

Features

•Quasi−Resonant Peak Current−Mode Control Operation

•Valley Switching Operation with Valley−Lockout for Noise−Immune

Operation

•Frequency Foldback at Light Load to Improve the Light Load

Efficiency

•Adjustable Over Power Protection

•Auto−Recovery or Latched Internal Output Short−Circuit Protection

•Fixed Internal 80 ms Timer for Short−Circuit Protection

•Combined Overvoltage and Overtemperature Protection (A and B

Versions)

•Combined Overvoltage Protection and Brown−Out (C and D

Versions)

•+500 mA/−800 mA Peak Current Source/Sink Capability

•Internal Temperature Shutdown

•Direct Optocoupler Connection

•Extended VCC Range Operation Up to 28 V

•Extremely Low No−Load Standby Power

•SO−8 Package

•These Devices are Pb−Free and are RoHS Compliant

Typical Applications

•High Power ac−dc Converters for TVs, Set−Top Boxes etc.

•Offline Adapters for Notebooks

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See detailed ordering and shipping information in the package

dimensions section on page 25 of this data sheet.

ORDERING INFORMATION

1380x

ALYW

1380x = Specific Device Code

x = Device Option (A, B, C, or D)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

MARKING DIAGRAMS

SOIC−8

D SUFFIX

CASE 751

PIN CONNECTIONS

ZCD

GND

FAULT

VCC

DRV

QUASI−RESONANT PWM

CONTROLLER FOR HIGH

POWER AC−DC WALL

ADAPTERS

NCP1380

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TYPICAL APPLICATION EXAMPLE

Figure 1. Typical Application Schematic for A and B Versions

Vout

HV−Bulk

GND

NCP1380 A/B

OVP / OTP

ZCD / OPP 1

Figure 2. Typical Application Schematic for C and D Versions

Vout

HV−Bulk

GND

NCP1380 C/D

BO / OVP

ZCD / OPP1

NCP1380

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PIN FUNCTION DESCRIPTION

Pin N5Pin Name Function Pin Description

1 ZCD Zero Crossing Detection

Adjust the over power protection

Connected to the auxiliary winding, this pin detects the core

reset event.

Also, injecting a negative voltage smaller than 0.3 V on this

pin will perform over power protection.

2 FB Feedback pin Hooking an optocoupler collector to this pin will allow

regulation.

3 CS Current sense This pin monitors the primary peak.

4 GND −The controller ground

5 DRV Driver output The driver’s output to an external MOSFET

6 VCC Supplies the controller This pin is connected to an external auxiliary voltage.

7 Fault Over voltage and Over temperature

protection (A and B versions)

Over−voltage and Brown−out

protection (C and D versions)

Pulling this pin down with an NTC or up with a zener diode

allows to latch the controller.

This pin observes the HV rail and protects the circuit in

case of low main conditions. It also offers a way to latch the

circuit in case of over voltage event.

8 CTTiming capacitor A capacitor connected to this pin acts as the timing

capacitor in foldback mode.

NCP1380 OPTIONS

OTP OVP Brown−Out

Auto−Recovery

Overcurrent

Protection

Latched

Overcurrent

Protection

NCP1380 / A Yes Yes Yes

NCP1380 / B Yes Yes Yes

NCP1380 / C Yes Yes Yes

NCP1380 / D Yes Yes Yes

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INTERNAL CIRCUIT ARCHITECTURE

ICt

−

ZCD

La ux

10 V

ESD Vth

DRV

de ma g

Rsense

LEB 1

−

/ 4

VDD

Soft-start

VCC

aux

VCC management

latch

VDD

Rpullup

fa ul t

DRV

ga te

gr a nd

reset

gr a nd

reset

gr a nd

reset

DRV

clamp

Soft−s ta rt e nd ? the n 1

else 0

l a tc he d

IpFlag

−

SS end

IpFlag

PWMreset

P W Mr eset

GN D

Down

TIM ER

Reset

VCCstop

BO r eset

L OGI C BL OCK

VDD

Fa ul t

VCC

VOVP

IOTP(REF)

OPP

VILIMIT

−

VDD

−

VOTP

SS end

noi s e de l a y

5 ms

Ti me Out

LEB 2 +

−

VC S(stop)

CsS top

Cs S top

LEB 2 is shorter than LEB 1

40 ms

Ti me Out

SS end

The 40 ms Time Out is active

only during s oft−start

SS end

Figure 3. Internal Circuit Architecture for Versions A and B

Ipeak(VCO) = 17.5% VILIMIT

Ct s e tpoi nt

Discharge

3 ms blanking

NCP1380

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ICt

−

ZCD

La ux

10 V

ESD Vth

DRV

de ma g

/ 4

VCC

VDD

VCC

aux

VCC management

latch

VDD

Rpullup

fa ul t

DRV

ga te

gr a nd

reset

gr a nd

reset

gr a nd

reset

DRV

clamp

IpFlag

P W Mreset

OVP/BO

GN D

Down

TIMER

Res et

VCCstop

−

IBO

noi s e de l a y VBO

BO r es et

−

Vclamp

VOVP

nois e de la y

BO reset

LOGIC BLOCK

VDD

Rclamp

VDD

C :

l a tc he d

Rsense

LEB 1

−

Soft-start

Soft−s ta r t e nd ? the n 1

else 0

IpFlag

−

SS end

P W Mreset

OPP

VILIMIT

LEB 2 +

−

VCS ( st op)

CsS top

LEB 2 is shorter than LEB 1

CsS top

5 ms

Time Out

40 ms

Time Out

SS end

The 40 ms Time Out is active

only during s oft−start

SS end

Figure 4. Internal Circuit Architecture for Versions C and D

Ipeak(VCO) = 17.5% VILIMIT

Ct se tpoint

3 ms blanking

discharge

NCP1380

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MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

VCC(MAX)

ICC(MAX)

Maximum Power Supply voltage, VCC pin, continuous voltage

Maximum current for VCC pin

−0.3 to 28

±30

VDRV(MAX)

IDRV(MAX)

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3 to 20

±1000

VMAX

IMAX

Maximum voltage on low power pins (except pins DRV and VCC)

Current range for low power pins (except pins ZCD, DRV and VCC)

−0.3 to 10

±10

IZCD(MAX) Maximum current for ZCD pin +3 / −2 mA

RqJA Thermal Resistance Junction−to−Air 120 °C/W

TJ(MAX) Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

ESD Capability, HBM Model (Note 1) 4 kV

ESD Capability, MM Model (Note 1) 200 V

ESD Capability, CDM Model (Note 1) 2 kV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 4000 V per JEDEC Standard JESD22, Method A114E

Machine Model 200 V per JEDEC Standard JESD22, Method A115A

Charged Device Model 2000 V per JEDEC Standard JESD22−C101D.

2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,

VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)

Symbol Condition Min Typ Max Unit

SUPPLY SECTION − STARTUP AND SUPPLY CIRCUITS

VCC(on)

VCC(off)

VCC(HYS)

VCC(latch)

VCC(reset)

Supply Voltage

Startup Threshold

Minimum Operating Voltage

Hysteresis VCC(on) − VCC(off)

Clamped VCC when latched−off

Internal logic reset

VCC increasing

VCC decreasing

VCC decreasing, ICC = 30 mA

8.3

7.2

6.2

8.0

7.2

9.4

9.2

8.2

tVCC(off)

tVCC(reset)

VCC(off) noise filter

VCC(reset) noise filter

−

ICC(start) Startup current FB pin open

VCC = VCC(on) − 0.5 V

−10 20 mA

ICC(disch) Current that discharges VCC when the controller

gets latched

VCC = 12 V 3.0 4.0 5.0 mA

ICC(latch) Current into VCC that keeps the controller latched

(Note 3)

VCC = VCC(latch) 30 − − mA

ICC1

ICC2

ICC3A

ICC3B

Supply Current

Device Disabled/Fault (Note 3) B, C, and D only

Device Enabled/No output load on pin 5

Device Switching (FSW = 65 kHz)

Device Switching VCO mode

VCC > VCC(off)

Fsw = 10 kHz

CDRV = 1 nF, FSW = 65 kHz

CDRV = 1 nF, VFB = 1.25 V

−

1.7

2.65

2.0

3.0

−

CURRENT COMPARATOR − CURRENT SENSE

VILIM Current Sense Voltage Threshold VFB = 4 V, VCS increasing 0.76 0.8 0.84 V

tLEB Leading Edge Blanking Duration for VILIM Minimum on time minus tILIM 210 275 330 ns

3. Guaranteed by design.

4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)

5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear

6. Minimum value for TJ = 125°C

7. NTC with R110 = 8.8 kW.

NCP1380

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ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,

VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)

Symbol UnitMaxTypMinCondition

CURRENT COMPARATOR − CURRENT SENSE

Ibias Input Bias Current (Note 3) DRV high −2−2mA

tILIM Propagation Delay VCS > VILIM to DRV turn−off −125 175 ns

Ipeak(VCO) Percentage of maximum peak current level at

which VCO takes over (Note 4)

VFB = 0.4 V, VCS increasing 15.4 17.5 19.6 %

VOPP(MAX) Setpoint decrease for VZCD = −300 mV (Note 5) VZCD = −300 mV, VFB = 4 V,

VCS increasing

35 37.5 40 %

VCS(stop) Threshold for immediate fault protection activation 1.125 1.200 1.275 V

tBCS Leading Edge Blanking Duration for VCS(stop) −120 −ns

DRIVE OUTPUT − GATE DRIVE

RSNK

RSRC

Drive Resistance

DRV Sink

DRV Source

VDRV = 10 V

VDRV = 2 V

−

12.5

−

ISNK

ISRC

Drive current capability

DRV Sink

DRV Source

VDRV = 10 V

VDRV = 2 V

−

800

500

−

trRise Time (10% to 90%) CDRV = 1 nF, VDRV from 0 to

12 V

−40 75 ns

tfFall Time (90% to 10%) CDRV = 1 nF, VDRV from 0 to

12 V

−25 60 ns

VDRV(low) DRV Low Voltage VCC = VCC(off) + 0.2 V

CDRV = 1 nF, RDRV = 33 kW

8.4 9.1 −V

VDRV(high) DRV High Voltage (Note 6) VCC = VCC(MAX)

CDRV = 1 nF

10.5 13.0 15.5 V

DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT

VZCD(TH) ZCD threshold voltage VZCD decreasing 35 55 90 mV

VZCD(HYS) ZCD hysteresis VZCD increasing 15 35 55 mV

VCH

VCL

Input clamp voltage

High state

Low state

Ipin1 = 3.0 mA

Ipin1 = −2.0 mA

−0.9

−0.7

−0.3

tDEM Propagation Delay VZCD decreasing from 4 V to

−0.3 V

−150 250 ns

CPAR Internal input capacitance −10 −pF

tBLANK Blanking delay after on−time 2.30 3.15 4.00 ms

toutSS

tout

Timeout after last demag transition During soft−start

After the end of soft−start

5.0

5.9

6.7

RZCD(pdown) Pulldown resistor (Note 3) 140 320 700 kW

TIMING CAPACITOR

VCT(MAX) Maximum voltage on CT pin VFB < VFB(TH) 5.15 5.40 5.65 V

ICT Source current VCT = 0 V 18 20 22 mA

VCT(MIN) Minimum voltage on CT pin, discharge switch

activated

− − 90 mV

CTRecommended timing capacitor value 220 pF

3. Guaranteed by design.

4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)

5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear

6. Minimum value for TJ = 125°C

7. NTC with R110 = 8.8 kW.

NCP1380

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ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,

VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)

Symbol UnitMaxTypMinCondition

FEEDBACK SECTION

RFB(pullup) Internal pullup resistor 15 18 22 kW

Iratio Pin FB to current setpoint division ratio 3.8 4.0 4.2

VFB(TH) FB pin threshold under which CT is clamped to

VCT(MAX)

0.26 0.3 0.34 V

VH2D

VH3D

VH4D

VHVCOD

VHVCOI

VH4I

VH3I

VH2I

Valley threshold

FB voltage where 1st valley ends and 2nd valley

starts

FB voltage where 2nd valley ends and 3rd valley

starts

FB voltage where 3rd valley ends and 4th valley

starts

FB voltage where 4th valley ends and VCO starts

FB voltage where VCO ends and 4th valley starts

FB voltage where 4th valley ends and 3rd valley

starts

FB voltage where 3rd valley ends and 2nd valley

starts

FB voltage where 2nd valley ends and 1st valley

starts

VFB decreases

VFB increases

1.316

1.128

0.846

0.732

1.316

1.504

1.692

1.880

1.4

1.2

0.9

0.8

1.4

1.6

1.8

2.0

1.484

1.272

0.954

0.828

1.484

1.696

1.908

2.120

FAULT PROTECTION (ALL VERSIONS)

TSHDN Thermal Shutdown Device switching (FSW

around 65 kHz)

140 −170 °C

TSHDN(HYS) Thermal Shutdown Hysteresis −40 −°C

tOVLD Overload Timer VFB = 4 V, VCS > VILIM 75 85 95 ms

tSSTART Soft−start duration VFB = 4 V, VCS ramping up,

measured from 1st DRV

pulse to VCS(peak) = 90% of

VILIM

2.8 3.8 4.8 ms

RFault(clamp) Clamp series resistor 1.3 1.55 1.8 kW

VOVP Fault detection level for OVP VFault increasing 2.35 2.5 2.65 V

tlatch(delay) Delay before latch confirmation 22.5 30 37.5 ms

FAULT PROTECTION A & B VERSIONS

IOTP(REF) Reference current for direct connection of an

NTC (Note 7)

VFault = VOTP + 0.2 V 85 91 97 mA

VOTP Fault detection level for OTP VFault decreasing 0.744 0.8 0.856 V

VFault(clamp) Clamped voltage (Fault pin left open) Fault pin open 1.13 1.35 1.57 V

FAULT PROTECTION C & D VERSIONS

VBO Brown−Out level VFault decreasing 0.744 0.8 0.856 V

IBO Sourced hysteresis current VFault > VBO VFault = VBO + 0.2 V 9 10 11 mA

tBO(delay) Delay before entering and exiting Brown−out 22.5 30 37.5 ms

VFault(clamp) Clamped voltage (Fault pin left open) Fault pin open 1.0 1.2 1.4 V

3. Guaranteed by design.

4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)

5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear

6. Minimum value for TJ = 125°C

7. NTC with R110 = 8.8 kW.

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17.00

17.05

17.10

17.15

17.20

17.25

17.30

−40 −20 0 20 40 60 80 100 120

Figure 5. VCC(on) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

VCC(on), (V)

8.70

8.75

8.80

8.85

8.90

8.95

9.00

−40 −20 0 20 40 60 80 100 120

Figure 6. VCC(off) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

VCC(off), (V)

1.30

1.40

1.50

1.60

1.70

1.80

1.90

−40 −20 0 20 40 60 80 100 120

Figure 7. ICC2 vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

ICC2, (mA)

2.20

2.30

2.40

2.50

2.60

2.70

2.80

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

Figure 8. ICC3A vs. Junction Temperature

ICC3A, (mA)

1.60

1.70

1.80

1.90

2.00

2.10

2.20

2.30

2.40

−40 −20 0 20 40 60 80 100 120

Figure 9. ICC3B vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

ICC3B, (mA)

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

−40 −20 0 20 40 60 80 100 120

ICC(start), (mA)

TJ, JUNCTION TEMPERATURE (°C)

Figure 10. ICC(start) vs. Junction Temperature

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780

785

790

795

800

805

810

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

VILIM, (mV)

Figure 11. VILIM vs. Junction Temperature

210

230

250

270

290

310

330

−40 −20 0 20 40 60 80 100 120

TLEB, (ns)

TJ, JUNCTION TEMPERATURE (°C)

Figure 12. TLEB vs. Junction Temperature

1.125

1.145

1.165

1.185

1.205

1.225

1.245

1.265

−40 −20 0 20 40 60 80 100 120

Figure 13. VCS(stop) vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

VCS(stop), (V)

36.0

36.5

37.0

37.5

38.0

38.5

39.0

−40 −20 0 20 40 60 80 100 120

Figure 14. VOPP(MAX) vs. Junction Temperature

VOPP(max), (%)

8.8

8.9

9.0

9.1

9.2

9.3

9.4

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

VDRV(low), (V)

Figure 15. VDRV(low) vs. Junction Temperature

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

−40 −20 0 20 40 60 80 100 120

VDRV(high), (V)

TJ, JUNCTION TEMPERATURE (°C)

Figure 16. VDRV(high) vs. Junction Temperature

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−40 −20 0 20 40 60 80 100 120

VZCD(th), (V)

TJ, JUNCTION TEMPERATURE (°C)

Figure 17. VZCD(th) vs. Junction Temperature

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

Figure 18. VZCD(hys) vs. Junction Temperature

VZCD(hys), (V)

2.90

3.0

3.10

3.20

3.30

3.40

3.50

−40 −20 0 20 40 60 80 100 120

TBLANK, (ms)

Figure 19. TBLANK vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

35.0

37.0

39.0

41.0

43.0

45.0

47.0

49.0

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

ToutSS, (ms)

Figure 20. ToutSS vs. Junction Temperature

5.0

5.2

5.4

5.6

5.8

6.0

6.2

6.4

6.6

−40 −20 0 20 40 60 80 100 120

Figure 21. Tout vs. Junction Temperature

Tout, (ms)

TJ, JUNCTION TEMPERATURE (°C)

780

785

790

795

800

805

810

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

VOTP

, (mV)

Figure 22. VOTP vs. Junction Temperature

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86.0

87.0

88.0

89.0

90.0

91.0

92.0

−40 −20 0 20 40 60 80 100 120

IOTP

, (mA)

TJ, JUNCTION TEMPERATURE (°C)

Figure 23. IOTP vs. Junction Temperature

780

785

790

795

800

805

810

−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

VBO, (mV)

Figure 24. VBO vs. Junction Temperature

9.2

9.4

9.6

9.8

10.0

10.2

10.4

−40 −20 0 20 40 60 80 100 120

IBO, (mA)

TJ, JUNCTION TEMPERATURE (°C)

Figure 25. IBO vs. Junction Temperature

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APPLICATION INFORMATION

The NCP1380 implements a standard current−mode

architecture operating in quasi−resonant mode. Due to a

proprietary circuitry, the controller prevents

valley−jumping instability and steadily locks out in selected

valley as the power demand goes down. Once the fourth

valley is reached, the controller continues to reduce the

frequency further down, offering excellent efficiency over

a wide operating range. Thanks to a fault timer combined to

an OPP circuitry, the controller is able to efficiently limit the

output power at high−line.

•Quasi−Resonance Current−mode operation:

implementing quasi−resonance operation in peak

current−mode control, the NCP1380 optimizes the

efficiency by switching in the valley of the MOSFET

drain−source voltage. Thanks to a proprietary circuitry,

the controller locks−out in a selected valley and

remains locked until the output loading significantly

changes. When the load becomes lighter, the controller

jumps into the next valley. It can go down to the 4th

valley if necessary. Beyond this point, the controller

reduces its switching frequency by freezing the peak

current setpoint. During quasi−resonance operation, in

case of very damped valleys, a 5.5 ms timer emulates

the missing valleys.

•Frequency reduction in light−load conditions: when

the 4th valley is left, the controller reduces the

switching frequency which naturally improves the

standby power by a reduction of all switching losses.

•Overpower protection (OPP): When the voltage on

ZCD pin swings in flyback polarity, a direct image if

the input voltage is applied on ZCD pin. We can thus

reduce the peak current depending of VZCD during the

on−time.

•Internal soft−start: A soft−start precludes the main

power switch from being stressed upon startup. Its

duration is fixed and equal to 4 ms.

•Fault input (A and B versions): By combining a dual

threshold on the Fault pin, the controller allows the

direct connection of an NTC to ground plus a zener

diode to a monitored voltage. In case the pin is brought

below the OTP threshold by the NTC or above the OVP

threshold by the zener diode, the circuit permanently

latches−off and VCC is clamped to 7.2 V.

•Fault input (C and D versions): The C and D versions

of NCP1380 include a brown−out circuit which safely

stops the controller in case the input voltage is too low.

Restart occurs via a complete startup sequence (latch

reset and soft−start). During normal operation, the

voltage on this pin is clamped to Vclamp to give enough

room for OVP detection. If the voltage on this pin

increases above 2.5 V, the part latches−off.

•Short−circuit protection: Short−circuit and especially

over−load protections are difficult to implement when a

strong leakage inductance between auxiliary and power

windings affects the transformer (where the auxiliary

winding level does not properly collapse in presence of

an output short). Here, when the internal 0.8 V

maximum peak current limit is activated, the timer

starts counting up. If the fault disappears, the timer

counts down. If the timer reaches completion while the

error flag is still present, the controller stops the pulses.

This protection is latched on A and C version (the user

must unplug and re−plug the power supply to restart the

controller) and auto−recovery on B and D versions (if

the fault disappears, the SMPS automatically resumes

operation). In addition, all versions feature a winding

short−circuit protection, that senses the CS signal and

stops the controller if VCS reaches 1.5 x VILIM (after a

reduced LEB of tBCS). This additional comparator is

enabled only during the main LEB duration tLEB, for

noise immunity reason.

NCP1380 OPERATING MODES

NCP1380 has two operating mode: quasi−resonant

operation and VCO operation for the frequency foldback.

The operating mode is fixed by the FB voltage as

portrayed by Figure 26:

•Quasi−resonant operation occurs for FB voltage higher

than 0.8 V (FB decreasing) or higher than 1.4 V (FB

increasing) which correspond to high output power and

medium output power. The peak current is variable and

is set by the FB voltage divided by 4.

•Frequency foldback or VCO mode occurs for FB

voltage lower than 0.8 V (FB decreasing) or lower than

1.4 V (FB increasing). This corresponds to low output

power.

During VCO mode, the peak current decreases down to

17.5% of its maximum value and is then frozen. The

switching frequency is variable and decreases as the

output load decreases.

The switching frequency is set by the end of charge of

the capacitor connected to the CT pin. This capacitor is

charged with a constant current source and the

capacitor voltage is compared to an internal threshold

fixed by FB voltage. When this capacitor voltage

reaches the threshold the capacitor is rapidly discharged

down to 0 V and a new period start.

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Figure 26. Operating Valley According to FB Voltage

VALLEY DETECTION AND SELECTION

The valley detection is done by monitoring the voltage of

the auxiliary winding of the transformer. A valley is detected

when the voltage on pin 1 crosses down the 55 mV internal

threshold. When a valley is detected, an internal counter is

incremented. The operating valley (1st, 2nd, 3rd or 4th) is

determined by the FB voltage as shown by Figure 26.

ICt

−

ZCD

La ux

10 V

ES D Vth

DRV

3 us puls e

de m a g

leakage

blanking

VDD

Discharge

Rpullup

DRV

LOGIC BLOCK

VDD

Tim e Out CS comparator

VFBth

VFB

Ct setpoint

Figure 27. Valley Detection Circuit

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As the output load decreases (FB voltage decreases), the

valleys are incremented from the first to the fourth. When

the fourth valley is reached, if FB voltage further decreases

below 0.8 V, the controller enters VCO mode.

During VCO operation, the peak current continues to

decrease until it reaches 17.5% of the maximum peak

current: the switching frequency expands to deliver the

necessary output power. This allows achieving very low

standby power consumption.

The Figure 28 shows a simulation case where the output

current of a 19 V, 60 W adapter decreases from 2.8 A to

0.1 A. No instability is seen during the valley transitions

(Figures 29, 30, 31 and 32)

Figure 28. Output Load is Decreased from 2.8 A Down to 100 mA at 120 Vdc Input Voltage

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Figure 29. Zoom 1: 1st to 2nd Valley Transition

Figure 30. Zoom 2: 2nd to 3rd Valley Transition

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Figure 31. Zoom 3: 3rd to 4th Valley Transition

Figure 32. Zoom 4: 4th Valley to VCO Mode Transition

Time Out

In case of extremely damped free oscillations, the ZCD

comparator can be unable to detect the valleys. To avoid

such situation, NCP1380 integrates a Time Out function that

acts as a substitute clock for the decimal counter inside the

logic bloc. The controller thus continues its normal

operation. To avoid having a too big step in frequency, the

time out duration is set to 5.5 ms. Figures 34 and 35 detail the

time out operation.

The NCP1380 also features an extended time out during

the soft−start.

Indeed, at startup, the output voltage reflected on the

auxiliary winding is low. Because of the voltage drop

introduced by the Over Power Compensation diode

(Figure 40), the voltage on the ZCD pin is very low and the

ZCD comparator might be unable to detect the valleys. In

this condition, setting the DRV Latch with the 5.5 ms

time−out can lead to a continuous conduction mode

operation (CCM) at the beginning of the soft−start. This

CCM operation only last a few cycles until the voltage on

ZCD pin becomes high enough to be detected by the ZCD

comparator. To avoid this, the time−out duration is extended

to 40 ms during the soft−start in order to ensure that the

transformer is fully demagnetized before the MOSFET is

turned−on.

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−

ZC D

10 V

ES D Vth

DRV 3 us pulse

5.5 us time out

de ma g

leakage blanking

LOGI C BL OCK

VDD

TimeOut

SS e nd

40 us time out

Figure 33. Time Out Circuit

Figure 34. Time Out Case n51: the 3rd Valley is Missing

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Figure 35. Time Out Case n52: the 3rd and 4th Valley are Missing

VCO MODE OR FREQUENCY FOLDBACK

VCO operation occurs for FB voltage lower than 0.8 V

(FB decreasing), or lower than 1.4 V (FB increasing). This

corresponds to low output power.

During VCO operation, the peak current is fixed to 17.5%

of his maximum value and the frequency is variable and

expands as the output power decreases.

The frequency is set by the end of charge of the capacitor

connected to the CT pin. This capacitor is charged with a

constant current source and its voltage is compared to an

internal threshold (VFBth) fixed by FB voltage (see

Figure 27). When this capacitor voltage reaches the

threshold, the capacitor is rapidly discharged down to 0 V

and a new period start. The internal threshold is inversely

proportional to FB voltage. The relationship between VFB

and VFBth is given by Equation 1.

VFBth +6.5 *(10ń3)VFB (eq. 1)

When VFB is lower than 0.3 V, VCT is clamped to

VCT(MAX) which is typically 5.5 V. Figure 36 shows the

VCO mode at works.

Figure 36. In VCO Mode, as the Power Output Decreases, the Frequency Expands

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SHORT−CIRCUIT OR OVERLOAD MODE

Figure 37 shows the implementation of the fault timer.

ZCD/OPP

Laux

Rsense

LEB1 +

−

Soft−start

VCC

au x

VCC

management

latch

Vd d

fau l t grand

reset

grand

reset

DRV

Soft −s t art end ?

t hen 1

else 0

IpFlag

−

SS en d

PW Mr eset

Down

TIMER

Reset

VCCstop

FB/4

A&C:

OPP

VIL IM IT

−

LEB2

VCS(stop)

CsStop

Figure 37. Overload Detection Schematic

Latched

When the current in the MOSFET is higher than VILIM /

Rsense, “Max Ip” comparator trips and the digital timer starts

counting: the timer count is incremented each 10 ms. When

the current comes back within safe limits, “Max Ip”

comparator becomes silent and the timer count down: the

timer count is decremented each 10 ms. In normal overload

conditions the timer reaches its completion when it has

counted up 8 times 10 ms.

On B and D version, when the timers reaches its

completion, the circuit enter auto−recovery mode: the

circuit stops all operations and VCC decreases via the circuit

own consumption (ICC1). When VCC reaches VCC(off), the

circuit goes in startup mode and restart switching. (see

Figure 38) This ensures a low duty−cycle burst operation in

fault mode.

On A and C versions, when the timers finishes counting

80 ms, the circuit goes in latch mode (Figure 39): the DRV

pulses stop and VCC is pulled down to VCC(latch) which is

7.2 V typically. The circuit un−latches when the current

circulating in VCC pin drops below ICC(latch).

In parallel to the cycle−by−cycle sensing of the CS pin,

another comparator with a reduced LEB (tBCS) and a

threshold of 1.2 V is able to sense winding short−circuit and

immediately shut down the controller. Depending on the

version, this additional protection is either latched or

auto−recovery, according to the overload protection

behavior.

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Figure 38. Auto−Recovery Short−Circuit Protection on B and D Versions

Figure 39. Latched Short−Circuit Protection on A and C Versions

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OVER POWER COMPENSATION

The over power compensation is achieved by monitoring

the signal on ZCD pin (pin 1). Indeed, a negative voltage

applied on this pin directly affects the internal voltage

reference setting the maximum peak current (Figure 40).

When the power MOSFET is turned−on, the auxiliary

winding voltage becomes a negative voltage proportional to

the input voltage. As the auxiliary winding is already

connected to ZCD pin for the valley detection, by selecting

the right values for Ropu and Ropl, we can easily perform

over power compensation.

ZCD/OPP

ESD

protection

Au x

Ropu

Ropl

Rz cd

−

Vt h

DRV Tblank

leakage blanking

Demag

OPP

VIL IMIT

IpFlag

Figure 40. Over Power Compensation Circuit

To ensure optimal zero−crossing detection, a diode is

needed to bypass Ropu during the off−time.

If we apply the resistor divider law on the pin 1 during the

on−time, we obtain the following relationship:

RZCD )Ropu

Ropl

Np,auxVin *VOPP

VOPP

(eq. 2)

Where:

Np,aux is the auxiliary to primary turn ration: Np,aux = Naux

/ Np

Vin is the DC input voltage

VOPP is the negative OPP voltage

By selecting a value for Ropl, we can easily deduce Ropu

using Equation 2. While selecting the value for Ropl, we

must be careful not choosing a too low value for this resistor

in order to have enough voltage for zero−crossing detection

during the off−time. We recommend having at least 8 V on

ZCD pin, the maximum voltage being 10 V.

During the off−time, ZCD pin voltage can be expressed as

follows:

VZCD +

Ropl

RZCD )Ropl

ǒVaux *VdǓ(eq. 3)

We can thus deduce the relationship between Ropl and

RZCD:

RZCD

Ropl

Vaux *Vd*VZCD

VZCD

(eq. 4)

Design example:

Vaux = 18 V

Vd = 0.6 V

Np,aux = 0.18

If we want at least 8 V on ZCD pin, we have:

RZCD

Ropl

Vaux *Vd*VZCD

VZCD (eq. 5)

+18 *0.6 *8

8[1.2

We can choose: RZCD = 1 kW and Ropl = 1 kW.

For the over power compensation, we need to decrease the

peak current by 37.5% at high line (370 Vdc). The

corresponding OPP voltage is:

VOPP +0.375 VILIM +−300 mV (eq. 6)

Using Equation 2, we have:

RZCD )Ropu

Ropt

Np,auxVlin *VOPP

VOPP (eq. 7)

+−0.18 370 *(−0.3)

(−0.3)+221

Thus,

Ropu +221Ropl *RZCD +221 1k *1k +220 kW

(eq. 8)

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OVERVOLTAGE/OVERTEMPERATURE DETECTION (A AND B VERSIONS)

Overvoltage and overtemperature detection is achieved

by reading the voltage on pin 7 (See Figure 41).

grand

reset

Fa ult

VCC

IOTP(REF)

VDD

−

SS end

nois e de lay

OT Pc o mp

OVPcomp

Rc l a mp

Vclam p

Clamp

Latch

OTP

OVP

NTC

Figure 41. OVP/OTP Circuitry

The IOTP(REF) current (91 mA typ.) biases the Negative

Temperature Coefficient sensor (NTC), naturally imposing

a dc voltage on the OTP pin. An internal clamp limit the

pin 7 voltage to 1.2 V when the NTC resistance is high (For

example, at 25°C, RNTC > 100 kW). When the temperature

increases, the NTC’s resistance reduces bringing the pin 7

voltage down until it reaches a typical value of 0.8 V: the

comparator trips and latches−off the controller (see

Figure 42).

In case of overvoltage, the zener diode starts to conduct

and inject current inside the internal clamp resistor Rclamp

thus causing the pin 7 voltage to increase. When this voltage

reaches the OVP threshold (2.5 V typ), the controller is

latched−off: all the DRV pulses stops and VCC is

pulled−down to VCC(latch) (7.2 V typ). The circuit

un−latches when the current circulating in VCC pin drops

below ICC(latch), thus the user must unplug and replug the

power supply.

Figure 42. Overvoltage and Overtemperature Chronograms

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OVERVOLTAGE PROTECTION/BROWN−OUT (C AND D VERSIONS)

The C and D versions of NCP1380 combine brown−out

and overvoltage detection on pin 7.

VCC

gr a nd

reset

DRV

OVP/BO

HV−Bulk

−

IBO

noi s e de l a y

VBO

BO reset

−

Vclamp

VOVP

noi s e de l a y

Rc l a mp

CS c omp

Rbou

Rbol

VDD

La tc h

Clamp

Figure 43. Brown−out and Overvoltage Protection

In order to protect the power supply against low input

voltage condition, the pin 7 permanently monitors a fraction

of the bulk voltage through a voltage divider. When this

image of bulk voltage is below the VBO threshold, the

controller stops switching. When the bulk voltage comes

back within safe limits, the circuit will restart pulsing only

when VCC reaches VCC(on) (Figure 44): this ensures a clean

startup sequence with soft−start. The hysteresis for the

brown−out function is implemented with a high side current

source sinking 10 mA when the brown−out comparator is

high (Vbulk > Vbulk(on))

Figure 44. Brown−out Operating Chronograms

In order to avoid having a too high voltage on pin 7 if the

bulk voltage is high, an internal clamp limits the voltage.

In case of overvoltage, the zener diode will start to

conduct and inject current inside the internal clamp resistor

Rclamp thus causing pin 7 voltage to increase. When this

voltage reaches VOVP

, the controller latches−off and stays

latched until the user cycles down the power supply

(Figure 45).

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Figure 45. Operating Chronograms in Case of Overvoltage

The following equations show how to calculate the

brownout resistors.

First of all, select the bulk voltage value at which the

controller must start switching (Vbulk(on)) and the bulk

voltage for shutdown (Vbulk(off)). Then use the following

equation to calculate Rbou and Rbol.

Rbol +

VBOǒVbulk(on)*VbulkǒoffǓǓ

IBOǒVbulk(on)*VBOǓ

(eq. 9)

Rbou +

RbolǒVbulk(on)*VBOǓ

VBO

(eq. 10)

ORDERING INFORMATION

Device Package Shipping†

NCP1380ADR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCP1380BDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCP1380CDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCP1380DDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

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NCP1380/D

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