SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS307J - MARCH 1993 - REVISED FEBRUARY 2005 FEATURES * * * * * * * * * DB, DGV, DW, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.7 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q LE DESCRIPTION/ORDERING INFORMATION This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION PACKAGE (1) TA SOIC - DW SSOP - DB -40C to 85C TSSOP - PW TVSOP - DGV (1) ORDERABLE PART NUMBER Tube of 25 SN74LVC841ADW Reel of 2000 SN74LVC841ADWR Reel of 2000 SN74LVC841ADBR Tube of 60 SN74LVC841APW Reel of 2000 SN74LVC841APWR Reel of 250 SN74LVC841APWT Reel of 2000 SN74LVC841ADGVR TOP-SIDE MARKING LVC841A LC841A LC841A LC841A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1993-2005, Texas Instruments Incorporated SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS307J - MARCH 1993 - REVISED FEBRUARY 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) OE LE 1 13 C1 2 1D 1D To Nine Other Channels 2 23 1Q SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com Absolute Maximum Ratings SCAS307J - MARCH 1993 - REVISED FEBRUARY 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V -0.5 6.5 V -0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND JA Package thermal impedance (4) Tstg (1) (2) (3) (4) DB package 63 DGV package 86 DW package 46 PW package 88 Storage temperature range -65 V C/W C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 Low-level input voltage VI Input voltage VO Output voltage 1.7 VCC = 2.7 V to 3.6 V 2 High-level output current 0.35 x VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC 3-state 0 5.5 Low-level output current t/v Input transition rise or fall rate TA Operating free-air temperature (1) V V V -4 VCC = 2.3 V -8 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V IOL V VCC = 2.3 V to 2.7 V VCC = 1.65 V IOH V 0.65 x VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA 10 ns/V 85 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS307J - MARCH 1993 - REVISED FEBRUARY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 A VOH 1.65 V to 3.6 V 1.2 IOH = -8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2.2 IOL = 100 A 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 V V 3.6 V 5 A Ioff VI or VO = 5.5 V 0 10 A IOZ VO = 0 to 5.5 V 3.6 V 10 A ICC ICC (1) (2) VI = 0 to 5.5 V UNIT VCC - 0.2 1.65 V IOL = 24 mA II TYP (1) MAX IOH = -4 mA IOH = -12 mA VOL MIN VI = VCC or GND IO = 0 3.6 V VI 5.5 V (2) One input at VCC - 0.6 V, 10 3.6 V Other inputs at VCC or GND 10 2.7 V to 3.6 V 500 A A Ci VI = VCC or GND 3.3 V 5 pF Co VO = VCC or GND 3.3 V 7 pF All typical values are at VCC = 3.3 V, TA = 25C. This applies in the disabled state only. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN UNIT MAX Pulse duration (1) (1) 3.3 3.3 ns tsu Setup time, data before LE (1) (1) 2.1 2.1 ns th Hold time, data after LE (1) (1) 1 1 ns tw (1) This information was not available at the time of publication. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) D LE TO (OUTPUT) Q 4 VCC = 2.5 V 0.2 V MIN MAX MIN MAX (1) (1) (1) (1) (1) (1) VCC = 2.7 V MIN VCC = 3.3 V 0.3 V UNIT MAX MIN MAX (1) 7.5 2.4 6.7 (1) 8.6 2.7 7.6 ns ten OE Q (1) (1) (1) (1) 8.5 1.3 7.2 ns tdis OE Q (1) (1) (1) (1) 6.6 1.9 5.9 ns 1 ns tsk(o) (1) VCC = 1.8 V 0.2 V This information was not available at the time of publication. SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS307J - MARCH 1993 - REVISED FEBRUARY 2005 Operating Characteristics TA = 25C TEST CONDITIONS PARAMETER Cpd (1) Power dissipation capacitance per latch Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 25 (1) (1) 6 UNIT pF This information was not available at the time of publication. 5 SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS307J - MARCH 1993 - REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 2.7 V 3.3 V 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V 1.5 V 2 x VCC 2 x VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC841ADBLE OBSOLETE SSOP DB 24 SN74LVC841ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWLE OBSOLETE TSSOP PW 24 TBD Call TI SN74LVC841APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWT ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC841APWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 8.8 2.5 12.0 16.0 Q1 SN74LVC841ADBR SSOP DB 24 2000 330.0 16.4 SN74LVC841ADGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC841APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 SN74LVC841APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC841ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74LVC841ADGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74LVC841APWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74LVC841APWT TSSOP PW 24 250 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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