© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 4 1Publication Order Number:
NTB75N03R/D
NTB75N03R, NTP75N03R
Power MOSFET
75 Amps, 25 Volts
N−Channel D2PAK, TO−220
Features
•Planar HD3e Process for Fast Switching Performance
•Low RDS(on) to Minimize Conduction Loss
•Low Ciss to Minimize Driver Loss
•Low Gate Charge
•Pb−Free Packages are Available
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 25 Vdc
Gate−to−Source Voltage − Continuous VGS ±20 Vdc
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C
− Single Pulse (tp = 10 ms)
RqJC
PD
ID
IDM
1.68
74.4
75
225
°C/W
W
A
A
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
60
2.08
12.6
°C/W
W
A
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
100
1.25
9.7
°C/W
W
A
Operating and Storage Temperature Range TJ, Tstg −55 to
150 °C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 10 Vdc, IL = 12 Apk,
L = 1 mH, RG = 25 W)
EAS 71.7 mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
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75 AMPERES
25 VOLTS
RDS(on) = 5.6 mW (Typ)
TO−220AB
CASE 221A
STYLE 5
123
4
MARKING DIAGRAMS
& PIN ASSIGNMENTS
xxxxxxx = Device Code
G = Pb−Free Device
A = Assembly Location
Y = Year
WW = Work Week
P75N03RG
AYWW
1
Gate 3
Source
4
Drain
2
Drain
1
Gate 3
Sourc
e
4
Drain
2
Drain
123
4
D2PAK
CASE 418B
75N03RG
AYWW
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
NTB75N03R, NTP75N03R
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified)
Characteristics Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(br)DSS 25
−28
20.5 −
−
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS −
−−
−1.0
10
mAdc
Gate−Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)IGSS − − ±100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th) 1.0
−1.5
4.0 2.0
−
Vdc
mV/°C
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 4.5 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 20 Adc)
RDS(on) −
−8.1
5.6 13
8.0
mW
Forward Transconductance (Note 3)
(VDS = 10 Vdc, ID = 15 Adc)gFS − 27 − Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 20 Vdc, VGS = 0 V,
f = 1 MHz)
Ciss − 1333 − pF
Output Capacitance Coss − 600 −
Transfer Capacitance Crss − 218 −
SWITCHING CHARACTERISTICS (Note 4)
T urn−On Delay Time
(VGS = 10 Vdc, VDD = 10 Vdc,
ID = 30 Adc, RG = 3 W)
td(on) − 6.9 − ns
Rise Time tr− 1.3 −
Turn−Off Delay Time td(off) − 18.4 −
Fall Time tf− 5.5 −
Gate Charge (VGS = 5 Vdc, ID = 30 Adc,
VDS = 10 Vdc) (Note 3)
QT− 13.2 − nC
Q1− 3.3 −
Q2− 6.2 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD −
−0.86
0.73 1.2
−
Vdc
Reverse Recovery Time
(IS = 35 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
trr − 15.6 − ns
ta− 13.8 −
tb− 1.78 −
Reverse Recovery Stored Charge QRR − 0.004 − mC
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperatures.
NTB75N03R, NTP75N03R
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3
10 V
0
0.018
6040
0.014
0.006
0.002 20 100
0.022
14
0
1.6
1.2
1.4
1.0
0.8
0.6
10,000
100,000
010
40
42
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
0
0.018
6040
0.010
0.006
0.002 20 80
Figure 3. On−Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
IDSS, LEAKAGE (nA)
140
−50 50250−25 75 125100
23
01510 2
5
5
6
20
60
VDS ≥ 10 V
TJ = 25°C
TJ = −55°C
TJ = 125°C
TJ = 150°C
VGS = 10 V VGS = 4.5 V
150
VGS = 0 V
ID = 30 A
VGS = 10 V
80
0.022
VGS = 2.5 V
TJ = 25°C
TJ = −55°C
TJ = 125°C
100
TJ = 150°C
TJ = 125°C
40
0
140
20
60
80
45
TJ = 25°C
TJ = −55°C
20
100
8 V 4 V
6 V
3.5 V
5 V 4.5 V
1.8
6
1000
8
100
120
3 V
10
100
120
TJ = 150°C
120 140
0.014 TJ = 125°C
80
0.010
120
NTB75N03R, NTP75N03R
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−of f delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t d(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is a ffected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Crss
10 0 10 15 20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
2400
800
0
VGS VDS
1200
400
55
VGS = 0 VVDS = 0 V
TJ = 25°C
Ciss
Coss
Crss Ciss
1600
2000
NTB75N03R, NTP75N03R
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5
VGS
70
00
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
IS, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
11010
0
1000
1
t, TIME (ns)
VGS = 0 V
Figure 10. Diode Forward Voltage versus Current
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
6
2
0
QG, TOTAL GATE CHARGE (nC)
8
4
12
100
48
0.2 0.4 1.0
10
20
30
ID = 35 A
TJ = 25°C
Q2
Q1
QT
tr
td(off)
td(on)
tf
10
VDS = 10 V
ID = 35 A
VGS = 10 V
0.6 0.8
16
40
60
50
TJ = 150°C
TJ = 25°C
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored ener gy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), i n a ccordance w ith i ndustry c ustom.
The energy rating must be derated for temperature as shown
in the accompanying graph ( Figure 1 2). Maximum e ner gy a t
currents below rated continuous ID can safely be assumed to
equal the values indicated.
NTB75N03R, NTP75N03R
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6
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1 1 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
1000
ID, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1 ms
100 ms
10 ms
dc
10 ms
100
t, TIME (s)
1
0.1 1100.10.010.0001
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
0.001
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
Figure 12. Thermal Response
ORDERING INFORMATION
Device Package Shipping†
NTP75N03R TO−220AB 50 Units / Rail
NTB75N03R D2PAK 50 Units / Rail
NTB75N03RG D2PAK
(Pb−Free) 50 Units / Rail
NTB75N03RT4 D2PAK 800 Tape & Reel
NTB75N03RT4G D2PAK
(Pb−Free) 800 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NTB75N03R, NTP75N03R
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7
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
SEATING
PLANE
S
G
D
−T−
M
0.13 (0.005) T
231
4
3 PL
K
J
H
V
E
C
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.340 0.380 8.64 9.65
B0.380 0.405 9.65 10.29
C0.160 0.190 4.06 4.83
D0.020 0.035 0.51 0.89
E0.045 0.055 1.14 1.40
G0.100 BSC 2.54 BSC
H0.080 0.110 2.03 2.79
J0.018 0.025 0.46 0.64
K0.090 0.110 2.29 2.79
S0.575 0.625 14.60 15.88
V0.045 0.055 1.14 1.40
−B−
M
B
W
W
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
F0.310 0.350 7.87 8.89
L0.052 0.072 1.32 1.83
M0.280 0.320 7.11 8.13
N0.197 REF 5.00 REF
P0.079 REF 2.00 REF
R0.039 REF 0.99 REF
M
L
F
M
L
F
M
L
F
VARIABLE
CONFIGURATION
ZONE RN P
U
VIEW W−W VIEW W−W VIEW W−W
123
8.38
0.33
1.016
0.04
17.02
0.67
10.66
0.42
3.05
0.12
5.08
0.20
ǒmm
inchesǓ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NTB75N03R, NTP75N03R
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8
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.570 0.620 14.48 15.75
B0.380 0.405 9.66 10.28
C0.160 0.190 4.07 4.82
D0.025 0.035 0.64 0.88
F0.142 0.147 3.61 3.73
G0.095 0.105 2.42 2.66
H0.110 0.155 2.80 3.93
J0.018 0.025 0.46 0.64
K0.500 0.562 12.70 14.27
L0.045 0.060 1.15 1.52
N0.190 0.210 4.83 5.33
Q0.100 0.120 2.54 3.04
R0.080 0.110 2.04 2.79
S0.045 0.055 1.15 1.39
T0.235 0.255 5.97 6.47
U0.000 0.050 0.00 1.27
V0.045 −−− 1.15 −−−
Z−−− 0.080 −−− 2.04
B
Q
H
Z
L
V
G
N
A
K
F
123
4
D
SEATING
PLANE
−T−
C
S
T
U
R
J
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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NTB75N03R/D
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