To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
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does not warrant that such information is error free. Ren esas E lectronics assumes no liability whatsoever for any da mages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified acco rding to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
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written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
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expressly specified in a Renesas Electronics data sheets or data books, et c.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electro nic app liances; machine tool s; p ersonal electron ic equipment; and indu strial robots .
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equ i pment; submersible repeaters; nu clear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
interven tion (e.g. excision, et c.), and any oth er applications or purposes that pose a direct th reat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,
Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for det ai ls as to enviro nmental matters such as the en vi ronmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
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Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
7534 Group
User’s Manual
8
User’s Manual
Rev.3.00 2006.10
RENESAS 8-BIT SINGLE-CHIP
MICROCOMPUTER
740 FAMILY / 740 SERIES
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Notes regarding these materials
General Precautions in the Handling of MPU/MCU Products
The following usa ge notes a re applicable to all MPU/MCU pr o duct s fr om Renesas. For detail ed usage n ote s on the
products covered by this manual, refer to the relevant sect i o ns of the manu al . If the descri pt i ons un der General
Precautions in the Handling of MPU/MCU Produ cts and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, write-
only and read and write. In the figure, these attributes are represented as follows :
: Bit in which nothing is arranged
0 1 :
Name Function
At reset
RWB
0
1
2
3
4
0
0
0
0
0
✕
✕
5
6
7
1
b0b1b2b3b4b5b6b7 Contents immediately after reset release
Bit attributes
(Note 1)
Processor mode bits
Stack page selection bit
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
Main clock (X
IN
-X
OUT
) stop bit
Internal system clock selection bit
0 0 : Single-chip mode
1 0 :
1 1 : Not available
b1 b0
0 : 0 page
1 : 1 page
0 : Operating
1 : Stopped
0 : X
IN
-X
OUT
selected
1 : X
CIN
-X
COUT
selected
: Bit that is not used for control of the corresponding function
0
Note 1:. Contents immediately after reset release
0.......“0” at reset release
1.......“1” at reset release
?.......Undefined at reset release
✽.......Contents determined by option at reset release
R.......Read
...... Read enabled
✕.......Read disabled
W......Write
.....Write enabled
✕...... Write disabled
✽.......“0” write
(Note 2)
CPU mode register (CPUM) [Address : 3B
16
]
Bits
✽
✽
3. Supplementation
For details of software, refer to the “740 FAMILY SOFTWARE MANUAL.”
For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com).
7534 Group
Table of contents
Rev.3.00 Oct 23, 2006 page 1 of 9
REJ09B0178-0300
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2
FEATURES......................................................................................................................................... 2
APPLICATION ................................................................................................................................... 2
PIN CONFIGURATION ..................................................................................................................... 2
FUNCTIONAL BLOCK ..................................................................................................................... 5
PIN DESCRIPTION ........................................................................................................................... 8
GROUP EXPANSION ....................................................................................................................... 9
FUNCTIONAL DESCRIPTION ....................................................................................................... 10
Central Processing Unit (CPU) ............................................................................................... 10
Memory ....................................................................................................................................... 14
I/O Ports..................................................................................................................................... 16
Interrupts .................................................................................................................................... 20
Timers ......................................................................................................................................... 23
Serial Interface .......................................................................................................................... 25
A/D Converter ............................................................................................................................ 36
Reset Circuit .............................................................................................................................. 38
Clock Generating Circuit .......................................................................................................... 40
NOTES ON PROGRAMMING ........................................................................................................ 42
NOTES ON USE ............................................................................................................................. 42
DATA REQUIRED FOR MASK ORDERS ................................................................................... 43
FUNCTIONAL DESCRIPTION SUPPLEMENT............................................................................ 45
Interrupt ...................................................................................................................................... 45
Timing After Interrupt................................................................................................................ 46
A/D Converter ............................................................................................................................ 47
Stop mode .................................................................................................................................. 49
Wait mode .................................................................................................................................. 50
DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP ................................... 51
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN ............................................................. 51
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY ............................. 53
CHAPTER 2 APPLICATION
2.1 I/O port ........................................................................................................................................ 2
2.1.1 Memory map ...................................................................................................................... 2
2.1.2 Relevant registers ............................................................................................................. 2
2.1.3 Application example of key-on wake up........................................................................ 6
2.1.4 Handling of unused pins .................................................................................................. 7
2.1.5 Notes on input and output pins ...................................................................................... 8
2.1.6 Termination of unused pins ............................................................................................. 9
2.2 Timer.......................................................................................................................................... 10
2.2.1 Memory map .................................................................................................................... 10
2.2.2 Relevant registers ........................................................................................................... 10
2.2.3 Timer application examples ........................................................................................... 16
2.3 Serial I/O ................................................................................................................................... 29
2.3.1 Memory map .................................................................................................................... 29
2.3.2 Relevant registers ........................................................................................................... 29
2.3.3 Serial I/O connection examples .................................................................................... 35
Table of contents
7534 Group
Rev.3.00 Oct 23, 2006 page 2 of 9
REJ09B0178-0300
2.3.4 Serial I/O transfer data format ...................................................................................... 37
2.3.5 Serial I/O application examples .................................................................................... 38
2.3.6 Notes on serial I/O ......................................................................................................... 49
2.4 USB ............................................................................................................................................ 50
2.4.1 Outline of USB ................................................................................................................ 50
2.4.2 Memory map .................................................................................................................... 56
2.4.3 Relevant registers ........................................................................................................... 57
2.4.4 USB application example............................................................................................... 62
2.4.5 Notes concerning USB ................................................................................................... 69
2.5 A/D converter .......................................................................................................................... 71
2.5.1 Memory map .................................................................................................................... 71
2.5.2 Relevant registers ........................................................................................................... 71
2.5.3 A/D converter application examples ............................................................................. 75
2.5.4 Notes on A/D converter ................................................................................................. 77
2.6 Reset.......................................................................................................................................... 78
2.6.1 Connection example of reset IC ................................................................................... 78
_____________
2.6.2 Notes on RESET pin...................................................................................................... 78
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ........................................................................................................ 2
3.1.1 Absolute maximum ratings ............................................................................................... 2
3.1.2 Recommended operating conditions ............................................................................... 3
3.1.3 Electrical characteristics ................................................................................................... 4
3.1.4 A/D converter characteristics........................................................................................... 5
3.1.5 Timing requirements ......................................................................................................... 6
3.1.6 Switching characteristics .................................................................................................. 6
3.2 Typical characteristics ............................................................................................................ 8
3.2.1 Power source current characteristic example (ICC-VCC characteristic)........................ 8
3.2.2 VOH-IOH characteristic example ....................................................................................... 11
3.2.3 A/D conversion typical characteristics example .......................................................... 15
3.3 Notes on use ........................................................................................................................... 17
3.3.1 Notes on interrupts ......................................................................................................... 17
3.3.2 Notes on serial I/O ......................................................................................................... 18
3.3.3 Notes on A/D converter ................................................................................................. 19
3.3.4 Notes on watchdog timer............................................................................................... 20
_____________
3.3.5 Notes on RESET pin...................................................................................................... 20
3.3.6 Notes on input and output pins .................................................................................... 20
3.3.7 Notes on programming................................................................................................... 21
3.3.8 Programming and test of built-in PROM version........................................................ 22
3.3.9 Notes on built-in PROM version ................................................................................... 23
3.3.10 Termination of unused pins......................................................................................... 24
3.3.11 Notes on CPU mode register ...................................................................................... 25
3.3.12 Notes on using 32-pin version.................................................................................... 25
3.3.13
Electric characteristic differences among mask ROM and One TIme PROM version MCUs ...
25
3.3.14 Note on power source voltage .................................................................................... 25
3.3.15 USB communication...................................................................................................... 26
3.4 Countermeasures against noise ......................................................................................... 27
3.4.1 Shortest wiring length ..................................................................................................... 27
3.4.2 Connection of bypass capacitor across VSS line and VCC line .................................. 29
3.4.3 Wiring to analog input pins ........................................................................................... 30
7534 Group
Table of contents
Rev.3.00 Oct 23, 2006 page 3 of 9
REJ09B0178-0300
3.4.4 Oscillator concerns.......................................................................................................... 30
3.4.5 Setup for I/O ports .......................................................................................................... 32
3.4.6 Providing of watchdog timer function by software ..................................................... 33
3.5 List of registers ...................................................................................................................... 34
3.6 Package outline ...................................................................................................................... 53
3.7 List of instruction code ........................................................................................................ 55
3.8 Machine instructions ............................................................................................................. 56
3.9 SFR memory map................................................................................................................... 67
3.10 Pin configurations ................................................................................................................ 68
List of figures
7534 Group
Rev.3.00 Oct 23, 2006 page 4 of 9
REJ09B0178-0300
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP.................................................... 2
Fig. 2 Pin configuration of M37534M4-XXXGP, M37534E4GP .................................................. 3
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP ........................... 4
Fig. 4 Functional block diagram (PRSP0036GA-A package type)............................................. 5
Fig. 5 Functional block diagram (PLQP0032GB-A package type) ............................................. 6
Fig. 6 Functional block diagram (PRDP0042BA-A package type) ............................................. 7
Fig. 7 Memory expansion plan ........................................................................................................ 9
Fig. 8 740 Family CPU register structure.................................................................................... 10
Fig. 9 Register push and pop at interrupt generation and subroutine call ............................ 11
Fig. 10 Structure of CPU mode register ...................................................................................... 13
Fig. 11 Switching method of CPU mode register ....................................................................... 13
Fig. 12 Memory map diagram ....................................................................................................... 14
Fig. 13 Memory map of special function register (SFR) ........................................................... 15
Fig. 14 Structure of pull-up control register ................................................................................ 16
Fig. 15 Structure of port P1P3 control register .......................................................................... 16
Fig. 16 Block diagram of ports (1) ............................................................................................... 18
Fig. 17 Block diagram of ports (2) ............................................................................................... 19
Fig. 18 Interrupt control.................................................................................................................. 21
Fig. 19 Structure of Interrupt-related registers ........................................................................... 21
Fig. 20 Connection example when using key input interrupt and port P0 block diagram ... 22
Fig. 21 Structure of timer X mode register ................................................................................. 23
Fig. 22 Timer count source set register ...................................................................................... 23
Fig. 23 Block diagram of timer X, timer 1 and timer 2 ............................................................. 24
Fig. 24 Block diagram of UART serial I/O1 ................................................................................ 25
Fig. 25 Operation of UART serial I/O1 function ......................................................................... 25
Fig. 26 Continuous transmission operation of UART serial I/O ............................................... 26
Fig. 27 USB mode block diagram ................................................................................................ 27
Fig. 28 USB transceiver block diagram ....................................................................................... 27
Fig. 29 Structure of serial I/Orelated registers (1)..................................................................... 28
Fig. 30 Structure of serial I/O1-related registers (2) ................................................................. 29
Fig. 31 Structure of serial I/O1-related registers (3) ................................................................. 30
Fig. 32 Structure of serial I/O1-related registers (4) ................................................................. 31
Fig. 33 Structure of serial I/O1-related registers (5) ................................................................. 32
Fig. 34 Structure of serial I/O2 control registers ........................................................................ 34
Fig. 35 Block diagram of serial I/O2............................................................................................ 34
Fig. 36 Serial I/O2 timing (LSB first) ........................................................................................... 35
Fig. 37 Structure of A/D control register ..................................................................................... 36
Fig. 38 Structure of A/D conversion register .............................................................................. 36
Fig. 39 Block diagram of A/D converter ...................................................................................... 36
Fig. 40 Block diagram of watchdog timer.................................................................................... 37
Fig. 41 Structure of watchdog timer control register ................................................................. 37
Fig. 42 Example of reset circuit .................................................................................................... 38
Fig. 43 Timing diagram at reset ................................................................................................... 38
Fig. 44 Internal status of microcomputer at reset...................................................................... 39
Fig. 45 External circuit of ceramic resonator.............................................................................. 40
Fig. 46 External clock input circuit ............................................................................................... 40
Fig. 47 Structure of MISRG ........................................................................................................... 40
7534 Group
List of figures
Rev.3.00 Oct 23, 2006 page 5 of 9
REJ09B0178-0300
Fig. 48 Block diagram of system clock generating circuit (for ceramic resonator) ............... 41
Fig. 49 Countermeasure (2) by software..................................................................................... 43
Fig. 50 Method to stabilize A/D conversion accuracy ............................................................... 43
Fig. 51 Programming and testing of One Time PROM version ............................................... 44
Fig. 52 Timing chart after an interrupt occurs............................................................................ 46
Fig. 53 Time up to execution of the interrupt processing routine ........................................... 46
Fig. 54 A/D conversion equivalent circuit.................................................................................... 48
Fig. 55 A/D conversion timing chart ............................................................................................. 48
Fig. 56 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP................... 53
Fig. 57 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP, M37534E4GP .................. 54
Fig. 58
Handling of V
CC
, USBV
REFOUT
pins of M37534E8SP, M37534M4-XXXSP, M37534RSS ........
55
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of registers relevant to I/O port ............................................................ 2
Fig. 2.1.2 Structure of Port Pi (i = 0 to 4).................................................................................... 2
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 4) ..................................................... 3
Fig. 2.1.4 Structure of Pull-up control register ............................................................................. 3
Fig. 2.1.5 Structure of P1P3 control register ................................................................................ 4
Fig. 2.1.6 Structure of Interrupt edge selection register ............................................................. 4
Fig. 2.1.7 Structure of Interrupt request register 1 ...................................................................... 5
Fig. 2.1.8 Structure of Interrupt control register 1 ....................................................................... 5
Fig. 2.1.9 Relevant registers setting .............................................................................................. 6
Fig. 2.1.10 Application circuit example .......................................................................................... 6
Fig. 2.1.11 Control procedure.......................................................................................................... 7
Fig. 2.2.1 Memory map of registers relevant to timers ............................................................. 10
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X...................................................................... 10
Fig. 2.2.3 Structure of Timer 1 ..................................................................................................... 11
Fig. 2.2.4 Structure of Timer 2 ..................................................................................................... 11
Fig. 2.2.5 Structure of Timer X..................................................................................................... 12
Fig. 2.2.6 Structure of Timer X mode register............................................................................ 13
Fig. 2.2.7 Structure of Timer count source set register ............................................................ 14
Fig. 2.2.8 Structure of Interrupt edge selection register ........................................................... 14
Fig. 2.2.9 Structure of Interrupt request register 1 .................................................................... 15
Fig. 2.2.10 Structure of Interrupt control register 1 ................................................................... 15
Fig. 2.2.11 Timers connection and setting of division ratios.................................................... 17
Fig. 2.2.12 Relevant registers setting .......................................................................................... 18
Fig. 2.2.13 Control procedure........................................................................................................ 19
Fig. 2.2.14 Peripheral circuit example.......................................................................................... 20
Fig. 2.2.15 Timers connection and setting of division ratios.................................................... 20
Fig. 2.2.16 Relevant registers setting .......................................................................................... 21
Fig. 2.2.17 Control procedure........................................................................................................ 22
Fig. 2.2.18 Judgment method of valid/invalid of input pulses .................................................. 23
Fig. 2.2.19 Relevant registers setting .......................................................................................... 24
Fig. 2.2.20 Control procedure........................................................................................................ 25
Fig. 2.2.21 Timers connection and setting of division ratios.................................................... 26
Fig. 2.2.22 Relevant registers setting .......................................................................................... 27
Fig. 2.2.23 Control procedure........................................................................................................ 28
Fig. 2.3.1 Memory map of registers relevant to serial I/O........................................................ 29
Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................... 29
Fig. 2.3.3 Structure of UART status register .............................................................................. 30
Fig. 2.3.4 Structure of Serial I/O1 control register..................................................................... 30
List of figures
7534 Group
Rev.3.00 Oct 23, 2006 page 6 of 9
REJ09B0178-0300
Fig. 2.3.5 Structure of UART control register ............................................................................. 31
Fig. 2.3.6 Structure of Baud rate generator................................................................................ 31
Fig. 2.3.7 Structure of Serial I/O2 control register..................................................................... 32
Fig. 2.3.8 Structure of Serial I/O2 register .................................................................................. 32
Fig. 2.3.9 Structure of Interrupt edge selection register ........................................................... 33
Fig. 2.3.10 Structure of Interrupt request register 1.................................................................. 33
Fig. 2.3.11 Structure of Interrupt control register 1 ................................................................... 34
Fig. 2.3.12 Serial I/O connection examples (1).......................................................................... 35
Fig. 2.3.13 Serial I/O connection examples (2).......................................................................... 36
Fig. 2.3.14 Serial I/O transfer data format .................................................................................. 37
Fig. 2.3.15 Connection diagram .................................................................................................... 38
Fig. 2.3.16 Timing chart ................................................................................................................. 38
Fig. 2.3.17 Registers setting relevant to transmission side...................................................... 39
Fig. 2.3.18 Transmission data setting of serial I/O2.................................................................. 40
Fig. 2.3.19 Registers setting relevant to reception side ............................................................ 40
Fig. 2.3.20 Control procedure of transmission side ................................................................... 41
Fig. 2.3.21 Control procedure of reception side......................................................................... 42
Fig. 2.3.22 Connection diagram .................................................................................................... 43
Fig. 2.3.23 Timing chart ................................................................................................................. 43
Fig. 2.3.24 Registers setting relevant to transmission side...................................................... 45
Fig. 2.3.25 Registers setting relevant to reception side ............................................................ 46
Fig. 2.3.26 Control procedure of transmission side ................................................................... 47
Fig. 2.3.27 Control procedure of reception side......................................................................... 48
Fig. 2.3.28 Sequence of clearing serial I/O ................................................................................ 49
Fig. 2.4.1 Communication sequence of USB .............................................................................. 51
Fig. 2.4.2 Data structure of USB packet ..................................................................................... 52
Fig. 2.4.3 USB (L.S.) interface...................................................................................................... 55
Fig. 2.4.4 USB (L.S.) connection example .................................................................................. 55
Fig. 2.4.5 Memory map of registers relevant to USB ................................................................ 56
Fig. 2.4.6 Description of the register structure........................................................................... 57
Fig. 2.4.7 Register structures relevant to USB (1) .................................................................... 58
Fig. 2.4.8 Register structures relevant to USB (2) .................................................................... 59
Fig. 2.4.9 Register structures relevant to USB (3) .................................................................... 60
Fig. 2.4.10 Register structures relevant to USB (4) .................................................................. 61
Fig. 2.4.11 Control method of control sequence ........................................................................ 62
Fig. 2.4.12 Timing chart of the transaction according to each token ..................................... 63
Fig. 2.4.13 USB interrupt processing example (OUT token) .................................................... 65
Fig. 2.4.14 USB interrupt processing example (IN token) ........................................................ 66
Fig. 2.4.15 Data read timing of SETUP token ............................................................................ 67
Fig. 2.4.16 Data read timing of OUT token ................................................................................ 67
Fig. 2.4.17 Data read timing of IN token (endpoint 0) and IN token (endpoint 1) token .... 67
Fig. 2.4.18 Timing chart of each signal....................................................................................... 68
Fig. 2.4.19 Example for determination of resume interrupt ...................................................... 69
Fig. 2.4.20 Processing for width of SE0 signal .......................................................................... 69
Fig. 2.4.21 Countermeasure (2) by software .............................................................................. 70
Fig. 2.5.1 Memory map of registers relevant to A/D converter ................................................ 71
Fig. 2.5.2 Structure of A/D control register ................................................................................. 71
Fig. 2.5.3 Structure of A/D conversion register (high-order) .................................................... 72
Fig. 2.5.4 Structure of A/D conversion register (low-order)...................................................... 72
Fig. 2.5.5 Structure of Interrupt edge selection register ........................................................... 73
Fig. 2.5.6 Structure of Interrupt request register 1 .................................................................... 73
Fig. 2.5.7 Structure of Interrupt control register 1 ..................................................................... 74
7534 Group
List of figures
Rev.3.00 Oct 23, 2006 page 7 of 9
REJ09B0178-0300
Fig. 2.5.8 Connection diagram ...................................................................................................... 75
Fig. 2.5.9 Relevant registers setting ............................................................................................ 75
Fig. 2.5.10 Control procedure for 8-bit read ............................................................................... 76
Fig. 2.5.11 Control procedure for 10-bit read ............................................................................. 76
Fig. 2.5.12 Method to stabilize A/D conversion accuracy......................................................... 77
Fig. 2.6.1 Example of poweron reset circuit ............................................................................... 78
CHAPTER 3 APPENDIX
Fig. 3.1.1 Power source current measurement circuit in USB mode at oscillation stop ........ 5
Fig. 3.1.2 Output switching characteristics measurement circuit ............................................... 6
Fig. 3.1.3 Timing chart ..................................................................................................................... 7
Fig. 3.2.1 ICC-VCC characteristic example (in double-speed mode)............................................. 8
Fig. 3.2.2 ICC-VCC characteristic example (at WIT instruction execution) .................................. 8
Fig. 3.2.3 ICC-VCC characteristic example (At STP instruction execution, Ta = 25 °C) ........... 9
Fig. 3.2.4 ICC-VCC characteristic example (At STP instruction execution, Ta = 85 °C) ........... 9
Fig. 3.2.5 ICC-VCC characteristic example (at USB suspend, Ta = 25 °C) .............................. 10
Fig. 3.2.6 ICC-VCC characteristic example (A/D conversion executed/not executed, f(XIN) = 6MHz,
in double-speed mode) ................................................................................................. 10
Fig. 3.2.7 VOH-IOH characteristic example of P-channel (Ta = 25 °C): normal port ............... 11
Fig. 3.2.8 VOH-IOH characteristic example of P-channel (Ta = 85 °C): normal port ............... 11
Fig. 3.2.9 VOL-IOL characteristic example of N-channel (Ta = 25 °C): Normal port............... 12
Fig. 3.2.10 VOL-IOL characteristic example of N-channel (Ta = 85 °C): Normal port............. 12
Fig. 3.2.11 VOL-IOL characteristic example of N-channel (Ta = 25 °C): LED drive port........ 13
Fig. 3.2.12 VOL-IOL characteristic example N-channel (Ta = 85 °C): LED drive port ............. 13
Fig. 3.2.13 “L” input current of port at pull-up transistor connected ....................................... 14
Fig. 3.2.14 Definition of A/D conversion accuracy ..................................................................... 15
Fig. 3.2.15 A/D conversion typical characteristic example........................................................ 16
Fig. 3.3.1 Sequence of switch the detection edge..................................................................... 17
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................... 17
Fig. 3.3.3 Structure of interrupt control register 1 ..................................................................... 18
Fig. 3.3.4 Sequence of clearing serial I/O .................................................................................. 18
Fig. 3.3.5 Method to stabilize A/D conversion accuracy ........................................................... 19
Fig. 3.3.6 Initialization of processor status register ................................................................... 21
Fig. 3.3.7 Sequence of PLP instruction execution ..................................................................... 21
Fig. 3.3.8 Stack memory contents after PHP instruction execution ........................................ 21
Fig. 3.3.9 Status flag at decimal calculations............................................................................. 22
Fig. 3.3.10 Programming and testing of One Time PROM version......................................... 22
Fig. 3.3.11 Switching method of CPU mode register ................................................................ 25
Fig. 3.3.12 Countermeasure (2) by software .............................................................................. 26
Fig. 3.4.1 Selection of packages .................................................................................................. 27
_____________
Fig. 3.4.2 Wiring for the RESET pin ............................................................................................ 27
Fig. 3.4.3 Wiring for clock I/O pins .............................................................................................. 28
Fig. 3.4.4 Wiring for CNVSS pin ................................................................................................... 28
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM........................................................ 29
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................... 29
Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................... 30
Fig. 3.4.8 Wiring for a large current signal line ......................................................................... 30
Fig. 3.4.9 Wiring of signal lines where potential levels change frequently ............................ 31
Fig. 3.4.10 VSS pattern on the underside of an oscillator.......................................................... 31
Fig. 3.4.11 Setup for I/O ports ...................................................................................................... 32
Fig. 3.4.12 Watchdog timer by software...................................................................................... 33
List of figures
7534 Group
Rev.3.00 Oct 23, 2006 page 8 of 9
REJ09B0178-0300
Fig. 3.5.1 Structure of Port Pi (i = 0 to 4).................................................................................. 34
Fig. 3.5.2 Structure of Port Pi direction register (i = 0 to 4) ................................................... 34
Fig. 3.5.3 Structure of Pull-up control register ........................................................................... 35
Fig. 3.5.4 Structure of Port P1P3 control register ..................................................................... 35
Fig. 3.5.5 Structure of Transmit/Receive buffer register ........................................................... 36
Fig. 3.5.6 Structure of UART status register .............................................................................. 36
Fig. 3.5.7 Structure of USB status register................................................................................. 37
Fig. 3.5.8 Structure of Serial I/O1 control register..................................................................... 38
Fig. 3.5.9 Structure of UART control register ............................................................................. 38
Fig. 3.5.10 Structure of Baud rate generator .............................................................................. 39
Fig. 3.5.11 Structure of USB data toggle synchronization register ......................................... 39
Fig. 3.5.12 Structure of USB interrupt source discrimination register 1 ................................. 39
Fig. 3.5.13 Structure of USB interrupt source discrimination register 2 ................................. 40
Fig. 3.5.14 Structure of USB interrupt control register .............................................................. 40
Fig. 3.5.15 Structure of USB transmit data byte number set register 0 ................................. 41
Fig. 3.5.16 Structure of USB transmit data byte number set register 1 ................................. 41
Fig. 3.5.17 Structure of USB PID control register 0.................................................................. 41
Fig. 3.5.18 Structure of USB PID control register 1.................................................................. 42
Fig. 3.5.19 Structure of USB address register ........................................................................... 42
Fig. 3.5.20 Structure of USB sequence bit initialization register ............................................. 42
Fig. 3.5.21 Structure of USB control register ............................................................................. 42
Fig. 3.5.22 Structure of Prescaler 12, Prescaler X .................................................................... 43
Fig. 3.5.23 Structure of Timer 1 ................................................................................................... 43
Fig. 3.5.24 Structure of Timer 2 ................................................................................................... 44
Fig. 3.5.25 Structure of Timer X mode register ......................................................................... 45
Fig. 3.5.26 Structure of Timer X................................................................................................... 46
Fig. 3.5.27 Structure of Timer count source set register.......................................................... 46
Fig. 3.5.28 Structure of Serial I/O2 control register................................................................... 47
Fig. 3.5.29 Structure of Serial I/O2 register ................................................................................ 47
Fig. 3.5.30 Structure of A/D control register............................................................................... 48
Fig. 3.5.31 Structure of A/D conversion register (high-order) .................................................. 49
Fig. 3.5.32 Structure of A/D conversion register (low-order).................................................... 49
Fig. 3.5.33 Structure of MISRG .................................................................................................... 50
Fig. 3.5.34 Structure of Watchdog timer control register .......................................................... 50
Fig. 3.5.35 Structure of Interrupt edge selection register ......................................................... 51
Fig. 3.5.36 Structure of CPU mode register ............................................................................... 51
Fig. 3.5.37 Structure of Interrupt request register 1.................................................................. 52
Fig. 3.5.38 Structure of Interrupt control register 1 ................................................................... 52
Fig. 3.10.1 M37534M4-XXXFP, M37534E8FP pin configuration .............................................. 68
Fig. 3.10.2 M37534M4-XXXGP, M37534E4GP pin configuration ............................................. 69
Fig. 3.10.3 M37534M4-XXXSP, M37534E8SP, M37534RSS pin configuration ...................... 70
7534 Group
List of tables
Rev.3.00 Oct 23, 2006 page 9 of 9
REJ09B0178-0300
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description .................................................................................................................... 8
Table 2 List of supported products ................................................................................................ 9
Table 3 Push and pop instructions of accumulator or processor status register.................. 11
Table 4 Set and clear instructions of each bit of processor status register.......................... 12
Table 5 I/O port function table ...................................................................................................... 17
Table 6 Interrupt vector address and priority ............................................................................. 20
Table 7 Relation of the width of SE0 and the state of the device ......................................... 33
Table 8 Special programming adapter ......................................................................................... 43
Table 9 Interrupt sources, vector addresses and interrupt priority .......................................... 44
Table 10 Change of A/D conversion register during A/D conversion ..................................... 46
Table 11 Stop mode state ............................................................................................................. 48
Table 12 Wait mode state ............................................................................................................. 49
Table 13 Description of improved USB function for 7534 Group ............................................ 50
Table 14 Differences among 32-pin, 36-pin and 42-pin............................................................ 50
Table 15 Differences among 32-pin, 36-pin and 42-pin (SFR) ................................................ 51
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins ............................................................................................. 7
Table 2.2.1 CNTR0 active edge switch bit function................................................................... 13
Table 2.3.1 Setting example of baud rate generator (BRG) and transfer bit rate values.... 44
Table 2.4.1 Transfer types of USB............................................................................................... 50
Table 2.4.2 Packet types of USB ................................................................................................. 52
Table 2.4.3 Data structure of USB packet .................................................................................. 53
Table 2.4.4 PID ............................................................................................................................... 53
Table 2.4.5 Special signal of USB ............................................................................................... 54
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings .......................................................................................... 2
Table 3.1.2 Recommended operating conditions .......................................................................... 3
Table 3.1.3 Electrical characteristics (1)........................................................................................ 4
Table 3.1.4 Electrical characteristics (2)........................................................................................ 5
Table 3.1.5 A/D Converter characteristics (1)............................................................................... 5
Table 3.1.6 Timing requirements .................................................................................................... 6
Table 3.1.7 Switching characteristics ............................................................................................. 6
Table 3.3.1 Programming adapters .............................................................................................. 23
Table 3.3.2 PROM programmer address setting ........................................................................ 24
Table 3.5.1 CNTR0 active edge switch bit function ................................................................... 45
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION SUPPLEMENT
DESCRIPTION OF IMPROVED USB
FUNCTION FOR 7534 GROUP
DIFFERENCES AMONG 32-PIN, 36-PIN
AND 42-PIN
DESCRIPTION SUPPLEMENT FOR
USE OF USB FUNCTION STABLY
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 2 of 55
REJ09B0178-0300
DESCRIPTION
The 7534 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7534 Group has a USB, 8-bit timers, and an A/D converter, and
is useful for an input device for personal computer peripherals.
FEATURES
•Basic machine-language instructions....................................... 69
•The minimum instruction execution time.......................... 0.34 µs
(at 6 MHz oscillation frequency for the shortest instruction)
•Memory sizeROM ...............................................8K to 16K bytes
RAM ..............................................256 to 384 bytes
•Programmable I/O ports...................................... 28 (36-pin type)
............................................................................ 24 (32-pin type)
............................................................................ 33 (42-pin type)
•Interrupts .................................................... 14 sources, 8 vectors
•Timers ............................................................................ 8-bit ✕ 3
•Serial Interface
Serial I/O1 ................................ used only for Low Speed in USB
(based on Low-Speed USB2.0 specification)
(USB/UART)
Serial I/O2 ...................................................................... 8-bit ✕ 1
(Clock-synchronized)
•A/D converter ................................................ 10-bit ✕ 8 channels
•Clock generating circuit ............................................. Built-in type
(connect to external ceramic resonator or quartz-crystal oscillator )
•Watchdog timer ............................................................ 16-bit ✕ 1
•Power source voltage
At 6 MHz XIN oscillation frequency at ceramic resonator
................................4.1 to 5.5 V(4.4 to 5.25 V at USB operation)
•Power dissipation ............................................ 30 mW (standard)
•Operating temperature range ................................... –20 to 85 °C
(0 to 70 °C at USB operation)
•Built-in USB 3.3 V Regulator + transceiver based on Low-Speed
USB2.0 specification
APPLICATION
Input device for personal computer peripherals
PIN CONFIGURATION (TOP VIEW)
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP
Outline: PRSP0036GA-A (36P2R-A)
1
0
1
2
3
4
6
7
8
9
1
1
1
2
1
4
1
5
1
6
5
1
3
1
7
1
8
3
6
3
5
3
4
3
3
31
3
0
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
3
2
2
7
2
9
2
8
P
0
0
C
N
V
S
S
X
O
U
T
X
I
N
V
S
S
P
0
1
P0
2
P
0
3
P
0
4
P
3
0
(
L
E
D
0
)
Vcc
V
REF
P0
5
P
1
0
/
R
X
D
/
D
-
P
2
6
/
A
N
6
P
2
7
/
A
N
7
P
1
1
/
T
X
D
/
D
+
P1
2
/S
CL
K
P
1
3
/
S
D
A
T
A
P
2
3
/
A
N
3
P
2
2
/
A
N
2
P
2
1
/
A
N
1
P2
0
/AN
0
P
3
1
(
L
E
D
1
)
P
3
7
/
I
N
T
0
P
2
4
/
A
N
4
P
2
5
/
A
N
5
P
0
6
P0
7
USBV
REFOUT
R
E
S
E
T
M
3
7
5
3
4
M
4
-
X
X
X
F
P
M
3
7
5
3
4
E
8
F
P
P
1
4
/
C
N
T
R
0
P
3
5
(
L
E
D
5
)
P
3
4
(
L
E
D
4
)
P
3
3
(
L
E
D
3
)
P3
2
(LED
2
)
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 3 of 55
REJ09B0178-0300
PIN CONFIGURATION (TOP VIEW)
Fig. 2 Pin configuration of M37534M4-XXXGP, M37534E4GP
Outline PLQP0032GB-A (32P6U-A)
P
0
7
P
10/
RXD
/
D
-
P
11/
TXD
/
D
+
P
12/
SC
L
K
P
13/
SD
A
T
A
P
14/
C
N
T
R
0
P
20/A
N
0
P
21/A
N
1
32
31
3
0
29
2
8
2
7
2
6
2
5P
34(
L
E
D4)
P
33(
L
E
D3)
P
32(
L
E
D2)
P
31(
L
E
D1)
P
30(
L
E
D0)
VS
S
XO
U
T
XI
N
9
10
11
1
2
13
14
15
16
2
8
7
6
5
3
1
4
VC
C
C
N
VS
S
R
E
S
E
T
P
22/
A
N2P
05
2
0
1
7
1
8
1
9
2
1
2
4
P
02
P
04
P
03
P
06
2
3
2
2
P
01
P
00
U
S
B
VR
E
F
O
U
T
M37534M4-XXXGP
M37534E4GP
P
23/
A
N3
P
24/
A
N4
P
25/
A
N5
VR
E
F
PIN CONFIGURATION
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 4 of 55
REJ09B0178-0300
PIN CONFIGURATION (TOP VIEW)
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP
Outline 42S1M, PRDP0042BA-A (42P4B)
1
0
1
2
3
4
6
7
8
9
11
1
2
1
4
1
5
1
6
5
1
3
1
7
1
8
3
6
3
5
3
4
3
3
31
3
0
2
6
2
5
2
4
2
3
2
2
3
2
2
7
2
9
2
8
1
9
2
0
2
1
4
2
4
1
4
0
3
9
3
7
3
8
P00
C
N
VS
S
XO
U
T
XIN
VSS
P01
P02
P03
P04
P30(LED0)
V
c
c
VR
E
F
P05
P12/SCLK
P25/AN5
P
26/
A
N6
P13/SDATA
P
14/
C
N
T
R0
P22/AN2
N
C
P
21/
A
N1
P
20/
A
N0
P31(LED1)
P23/AN3
P24/AN4
P06
P07
P37/INT0
RESET
M
3
7
5
3
4
R
S
S
M
3
7
5
3
4
M
4
-
X
X
X
S
P
M
3
7
5
3
4
E
8
S
P
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
USBVREFOUT
P10/RXD/D-
P11/TXD/D+
P27/AN7
P16
P15
P
40
P
41P36(LED6)/INT1
PIN CONFIGURATION
7534 Group
HARDWARE
FUNCTIONAL BLOCK
Rev.3.00 Oct 23, 2006 page 5 of 55
REJ09B0178-0300
FUNCTIONAL BLOCK
Fig. 4 Functional block diagram (PRSP0036GA-A package type)
FUNCTIONAL BLOCK DIAGRAM (Package: PRSP0036GA-A)
S
I
/
O
1
(
8
)
U
S
B
(
L
S
)
R
A
M
R
O
M
C
P
U
A
X
Y
S
P
C
H
P
C
L
P
S
V
S
S
1
8
R
E
S
E
T
1
3
V
C
C
1
5
1
4
C
N
V
S
S
C
N
T
R0
P
0
(
8
)
3
4
3
2
3
0
2
8
3
3
3
1
2
9
2
7
P
1
(
5
)
3
1
3
5
2
3
6
7
5
6
4
P
2
(
8
)
P
3
(
7
)
1
2
1
6
1
7
1
1
9
1
0
8
VR
E
F
0
2
6
I
N
T0
2
0
2
3
2
1
1
9
2
2
2
4
2
5
S
I
/
O
2
(
8
)
U
S
B
V
R
E
F
O
U
T
X
I
N
X
O
U
T
C
l
o
c
k
i
n
p
u
t
C
l
o
c
k
o
u
t
p
u
t
C
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
W
a
t
c
h
d
o
g
t
i
m
e
r
R
e
s
e
t
A
/
D
c
o
n
v
e
r
t
e
r
(
1
0
)
I
/
O
p
o
r
t
P
3
I
/
O
p
o
r
t
P
2
I
/
O
p
o
r
t
P
1
I
/
O
p
o
r
t
P
0
K
e
y
-
o
n
w
a
k
e
u
p
T
i
m
e
r
1
(
8
)
T
i
m
e
r
2
(
8
)
T
i
m
e
r
X
(
8
)
P
r
e
s
c
a
l
e
r
1
2
(
8
)
P
r
e
s
c
a
l
e
r
X
(
8
)
R
e
s
e
t
i
n
p
u
t
HARDWARE
7534 Group FUNCTIONAL BLOCK
Rev.3.00 Oct 23, 2006 page 6 of 55
REJ09B0178-0300
Fig. 5 Functional block diagram (PLQP0032GB-A package type)
FUNCTIONAL BLOCK DIAGRAM (Package: PLQP0032GB-A)
S
I
/
O
1
(
8
)
U
S
B
(
L
S
)
R
A
M
R
O
M
C
P
U
A
X
Y
S
P
C
H
P
C
L
P
S
V
S
S
1
1
R
E
S
E
T
6
V
C
C
8
7
C
N
V
S
S
C
N
T
R0
P
0
(
8
)
2
5
2
3
2
1
1
9
2
4
2
2
2
0
1
8
P
1
(
5
)
3
0
2
8
2
6
2
9
2
7
3
2
3
1
P
2
(
6
)
P
3
(
5
)
5
9
1
0
4
2
3
1
VR
E
F
0
1
7
1
3
1
6
1
4
1
2
1
5
S
I
/
O
2
(
8
)
U
S
B
V
R
E
F
O
U
T
X
I
N
X
O
U
T
C
l
o
c
k
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n
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l
o
c
k
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t
p
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C
l
o
c
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r
a
t
i
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g
c
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r
c
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i
t
W
a
t
c
h
d
o
g
t
i
m
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r
R
e
s
e
t
A
/
D
c
o
n
v
e
r
t
e
r
(
1
0
)
I
/
O
p
o
r
t
P
3
I
/
O
p
o
r
t
P
2
I
/
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p
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t
P
1
I
/
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p
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r
t
P
0
K
e
y
-
o
n
w
a
k
e
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p
T
i
m
e
r
1
(
8
)
T
i
m
e
r
2
(
8
)
T
i
m
e
r
X
(
8
)
P
r
e
s
c
a
l
e
r
1
2
(
8
)
P
r
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s
c
a
l
e
r
X
(
8
)
R
e
s
e
t
i
n
p
u
t
7534 Group
HARDWARE
FUNCTIONAL BLOCK
Rev.3.00 Oct 23, 2006 page 7 of 55
REJ09B0178-0300
Fig. 6 Functional block diagram (PRDP0042BA-A package type)
T
i
m
e
r
1
(
8
)
T
i
m
e
r
2
(
8
)
T
i
m
e
r
X
(
8
)
P
r
e
s
c
a
l
e
r
1
2
(
8
)
P
r
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c
a
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e
r
X
(
8
)
X
I
N
O
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T
X
R
A
M
R
O
M
C
P
U
A
X
Y
S
P
C
H
P
C
L
P
S
V
S
S
2
1
R
E
S
E
T
1
6
V
C
C
1
8
1
7
C
N
V
S
S
C
N
T
R
0
P
1
(
7
)
P
2
(
8
)
P
3
(
8
)
1
9
2
0
V
R
E
F
0
I
N
T
0
U
S
B
V
R
E
F
O
U
T
I
N
T
1
P
4
(
2
)
S
I
/
O
1
(
8
)
U
S
B
(
L
S
)
S
I
/
O
2
(
8
)
C
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
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i
t
W
a
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A
/
D
c
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n
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r
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r
(
1
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)
I
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p
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r
t
P
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4
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1
3
1
4
1
5
2
4
2
7
2
5
2
3
2
6
2
8
2
9
2
2
8
5
7
4
1
2
1
0
1
1
9
3
0
3
1
4
1
2
4
2
3
9
4
0
P
0
(
8
)
3
8
3
6
3
4
3
2
3
7
3
5
3
3
3
1
FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0042BA-A)
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 8 of 55
REJ09B0178-0300
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
VREF
USBVREFOUT
CNVss
RESET
P00–P07
P10/RxD/D-
P11/TxD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P15, P16
XIN
Function
•Apply voltage of 4.1 to 5.5 V (4.4 to 5.25 V at USB operating) to Vcc, and 0 V to Vss.
•Reference voltage input pin for A/D converter
•Output pin for pulling up a D- line with 1.5 kΩ external resistor
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
Function expect a port function
Name
Power source
Analog reference
voltage
USB reference
voltage output
CNVss
Reset input
Clock input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed
as either input or output.
•CMOS 3-state output structure at CMOS compatible input level
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•7-bit I/O port
•I/O direction register allows each pin to be individually programmed
as either input or output.
•CMOS 3-state output structure at CMOS compatible input level
•CMOS/TTL level can be switched for P10, P12, P13.
•When using the USB function, input level of ports P10 and P11
becomes USB input level, and output level of them becomes
USB output level.
•8-bit I/O port having almost the same function as P0
•CMOS 3-state output structure at CMOS compatible input level
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS 3-state output structure at CMOS compatible input level (CMOS/TTL level can be switched
for P36, P37).
•P30 to P36 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•2-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•Key-input (key-on wake up
interrupt input) pins
•Serial I/O1 function pin
•Serial I/O2 function pin
•Timer X function pin
•Input pins for A/D converter
•Interrupt input pins
XOUT Clock output
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
PIN DESCRIPTION
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 9 of 55
REJ09B0178-0300
GROUP EXPANSION
Renesas plans to expand the 7534 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emu-
lator MCU .
Memory size
ROM/PROM size ..................................................8 K to 16 K bytes
RAM size................................................................256 to 384 bytes
Fig. 7 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Part number
M37534M4-XXXFP
M37534M4-XXXGP
M37534M4-XXXSP
M37534E4GP
M37534E8FP
M37534E8SP
M37534RSS
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version (blank)
Emulator MCU
Package
PRSP0036GA-A
PLQP0032GB-A
PRDP0042BA-A
PLQP0032GB-A
PRSP0036GA-A
PRDP0042BA-A
42S1M
(P) ROM size (bytes)
ROM size for User ()
8192 (8062)
8192 (8062)
8192 (8062)
8192 (8062)
16384 (16254)
16384 (16254)
RAM size
(bytes)
256
256
256
256
384
384
384
Package
PRSP0036GA-A .........................0.8 mm-pitch plastic molded SOP
PLQP0032GB-A........................ 0.8 mm-pitch plastic molded LQFP
PRDP0042BA-A.................................... 42 pin plastic molded SDIP
42SIM...................................... 42 pin shrink ceramic PIGGY BACK
ROM size
(Byte)
R
A
M
s
i
z
e
(
B
y
t
e
)
1
2
8
16
K
256 3
8
4
8
K
0
M37534E8
M37534M4
M
3
7
5
3
4
E
4
GROUP EXPANSION
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 10 of 55
REJ09B0178-0300
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7534 group uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine instructions or
the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instructions cannot be used.
The MUL and DIV instructions cannot be used.
The WIT and STP instructions can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the
index addressing modes, the value of the OPERAND is added to the
contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the value
contained in index register X becomes the address for the second
OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls and
interrupts. The stack is used to store the current address data and
processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the con-
tents of the stack pointer. The upper eight bits of the stack address are
determined by the Stack Page Selection Bit. If the Stack Page Selec-
tion Bit is “0”, then the RAM in the zero page is used as the stack area.
If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as
the stack area.
The Stack Page Selection Bit is located in the SFR area in the zero
page. Note that the initial value of the Stack Page Selection Bit varies
with each microcomputer type. Also some microcomputer types have
no Stack Page Selection Bit and the upper eight bits of the stack ad-
dress are fixed. The operations of pushing register contents onto the
stack and popping them from the stack are shown in Figure 9.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PCH and PCL. It is used to indicate the address of the next instruc-
tion to be executed.
Fig. 8 740 Family CPU register structure
b7 b0
X
b7 b0
S
b7 b0
Y
b7 b0
PCL
Processor Status Register (PS)
Carry Flag
b7 b0
b7 b0
A
b15 PCH
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Program Counter
Stack Pointer
Index Register Y
Index Register X
Accumulator
CZIDBTVN
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 11 of 55
REJ09B0178-0300
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 9 Register push and pop at interrupt generation and subroutine call
Execute JSR
On-going Routine
M (S) (PC
H
)
(S)
(S – 1)
M (S) (PC
L
)
Execute RTS
(PC
L
) M (S)
(S)
(S – 1)
(S)
(S + 1)
(S)
(S + 1)
(PC
H
) M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack M (S) (PS)
Execute RTI
(PS) M (S)
(S)
(S – 1)
(S)
(S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S) (PC
H
)
(S)
(S – 1)
M (S) (PC
L
)
(S)
(S – 1)
(PC
L
) M (S)
(S)
(S + 1)
(S)
(S + 1)
(PC
H
) M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 12 of 55
REJ09B0178-0300
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic opera-
tion. Branch operations can be performed by testing the Carry (C) flag,
Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal
mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other flags
are undefined. Since the Index X mode (T) and Decimal mode (D)
flags directly affect arithmetic operations, they should be initialized in
the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”. The saved processor
status is the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory locations,
i.e. between memory and memory, memory and I/O, and I/O and
I/O. In this case, the result of an arithmetic operation performed
on data in memory location 1 and memory location 2 is stored in
memory location 1. The address of memory location 1 is
specified by index register X, and the address of memory
location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag Z flag I flag D flag B flag T flag V flag N flag
SEC
CLC
_
_SEI
CLI SED
CLD
_
_SET
CLT CLV
__
_
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 13 of 55
REJ09B0178-0300
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
Fig. 11 Switching method of CPU mode register
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
Fig. 10 Structure of CPU mode register
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B1
6)
Stack page selection bit
0 : 0 page
1 : 1 page
Main clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied f rom on- c hip oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)
Not used (returns “0” when read)
(Do not write “1” to these bits )
Processor mode bits
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1 N
o
t
a
v
a
i
l
a
b
l
e
b
7
b
0
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
After releasing reset
Main routine
Start with an on-chip oscillator (Note)
Switch to other mode except an on-chip oscillator
(Select one of 1/1, 1/2, and 1/8)
Note. After releasing reset the operation starts by starting an on-chip oscillator automatically.
Do not use an on-chip oscillator at ordinary operation.
Wait until establish ceramic oscillator
clock.
Note on stack page
When 1 page is used as stack area by the stack page selection bit,
the area which can be used as stack depends on RAM size. Espe-
cially, be careful that the RAM area varies in Mask ROM version,
One Time PROM version and Emulator MCU.
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 14 of 55
REJ09B0178-0300
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Fig. 12 Memory map diagram
0100
16
0000
16
0040
16
0440
16
FF00
16
FFEC
16
FFFE
16
FFFF
16
256
384
XXXX
16
013F
16
01BF
16
8192
16384 E000
16
C000
16
E080
16
C080
16
YYYY
16
ZZZZ
16
RAM
ROM
Reserved area
SFR area
Not used
Interrupt vector area
ROM area
Reserved ROM area
(128 bytes)
Zero page
Special page
RAM area
RAM capacity
(bytes) address
XXXX16
ROM capacity
(bytes) address
YYYY16
Reserved ROM area
address
ZZZZ16
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 15 of 55
REJ09B0178-0300
Fig. 13 Memory map of special function register (SFR)
0
0
0
0
1
6
0001
16
0
0
0
2
1
6
0
0
0
3
1
6
0
0
0
4
1
6
0
0
0
5
1
6
0
0
0
6
1
6
0
0
0
7
1
6
0
0
0
8
1
6
0
0
0
9
1
6
0
0
0
A
1
6
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
000E
16
0
0
0
F
1
6
0
0
1
0
1
6
0011
16
0012
16
0
0
1
3
1
6
0
0
1
4
1
6
0
0
1
5
1
6
0016
16
0017
16
0
0
1
8
1
6
0
0
1
9
1
6
001A
16
001B
16
0
0
1
C
1
6
0
0
1
D
1
6
0
0
1
E
1
6
001F
16
Port P0 (P0)
Port P 0 direction registe r (P0D)
Port P1 (P1)
Port P 1 direction registe r (P1D)
Port P2 (P2)
Port P 2 direction registe r (P2D)
Port P3 (P3)
Port P 3 direction registe r (P3D)
Pull-up control register (PULL)
Transmit/Receive buffer register (TB/RB)
USB
stat us reg
i
ster
(USBSTS)
/
UART
status reg
i
ster
(UARTSTS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud r ate generat or ( B RG)
Port P 1P 3 control regis ter (P1P3C)
USB da ta toggle synchronization re gis ter ( TRSYNC)
USB in terrupt sour c e discrimination re gis ter 1 (USBI R1)
USB in terrupt sour c e discrimination re gis ter 2 (USBI R2)
0
0
2
0
1
6
0021
16
0
0
2
2
1
6
0
0
2
3
1
6
0
0
2
4
1
6
0
0
2
5
1
6
0
0
2
6
1
6
0
0
2
7
1
6
0
0
2
8
1
6
0
0
2
9
1
6
0
0
2
A
1
6
0
0
2
B
1
6
0
0
2
C
1
6
0
0
2
D
1
6
002E
16
0
0
2
F
1
6
0
0
3
0
1
6
0031
16
0032
16
0
0
3
3
1
6
0
0
3
4
1
6
0
0
3
5
1
6
0036
16
0037
16
0
0
3
8
1
6
0
0
3
9
1
6
003A
16
003B
16
0
0
3
C
1
6
0
0
3
D
1
6
0
0
3
E
1
6
003F
16
Timer count source set register (TCSS)
A/D conversion register (low-order) (ADL)
Prescaler 12 (PR E 12)
Timer 1 (T1)
Timer 2 (T2)
Timer X mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Serial I/O2 control register (SIO2CON)
Serial I/O2 register (SIO2)
A/D control regis ter (ADC ON)
A/D conv ersion re gis ter (high- or der) (ADH)
MISRG
Watc hdog timer control regis ter (WDTC ON)
Inter rupt edge s election register (INTEDGE)
CPU mode register (CPUM)
Inter r upt request register 1 ( I RE Q1)
Inter r upt control register 1 ( ICON1)
USB in terrupt control regis ter (USBI CON)
USB tr ansm it data byte number set regis ter 0 (EP0BYTE)
USB tr ansm it data byte number set regis ter 1 (EP1BYTE)
USBPID control register 0 (EP0PID)
USBPID control register 1 (EP1PID)
USB address register (USBA)
USB sequence bit initialization reg is ter (INISQ 1)
USB control register (US BC ON)
Port P4 (P4)
Port P 4 direction registe r (P4D)
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 16 of 55
REJ09B0178-0300
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/out-
put direction of each pin. Each bit in a direction register corresponds
to individual pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
[Pull-up control] PULL
By setting the pull-up control register (address 001616), ports P0 and
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control] P1P3C
By setting the port P1P3 control register (address 001716), a CMOS
input level or a TTL input level can be selected for ports P10, P12,
P13, P36 and P37 by program.
Then, as for the 36-pin version, set “1” to each bit 6 of the port P3
direction register and port P3 register.
As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
Fig. 15 Structure of port P1P3 control register
Fig. 14 Structure of pull-up control register
Pull-up control register
(PULL: address 0016
16
)
P0
0
pull-up control bit
P0
1
pull-up control bit
P0
2
, P0
3
pull-up control bit
P0
4
– P0
7
pull-up control bit
P3
0
– P3
3
pull-up control bit
P3
4
pull-up control bit
P3
5
, P3
6
pull-up control bit
P3
7
pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
b7 b0
0: Pull-up off
1: Pull-up on
Initial value: FF
16
Port P1P3 control register
(P1P3C: address 0017
16
)
b7 b0
P3
7
/INT
0
input level selection bit
0 : CMOS level
1 : TTL level
P3
6
/INT
1
input level selection bit
0 : CMOS level
1 : TTL level
P1
0
,P1
2
,P1
3
input level selection bit
0 : CMOS level
1 : TTL level
Not used
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 17 of 55
REJ09B0178-0300
Table 5 I/O port function table
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Pin
P00–P07
P10/RxD/D-
P11/TxD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Related SFRs
Pull-up control register
Serial I/O1 control
register
Serial I/O2 control
register
Timer X mode register
A/D control register
Interrupt edge selection
register
Diagram No.
Input/output
I/O individual
bits
I/O format
•CMOS compatible input level
•CMOS 3-state output
•USB input/output level when
selecting USB function
•CMOS compatible input level
•CMOS 3-state output
(Note)
Non-port function
Key input interrupt
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A/D conversion input
External interrupt input
(1)
(2)
(3)
(4)
(5)
(6)
(10)
(7)
(8)
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL input level.
(9)
(10)
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 18 of 55
REJ09B0178-0300
Fig. 16 Block diagram of ports (1)
Data bus
+
-
(1) Port P0
Data bus
Direction
register
Port latch
Pull-up control
To key input interrupt
generating circuit
Data bus
Direction
register
Port latch
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Receive enable bit
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
P10,P12,P13 input
level selection bit
D- input
D- output
Serial I/O1 input
USB output enable
(internal signal)
USB differential input
D+ input
D+ output
Serial I/O1 output
USB output enable
(internal signal)
Direction
register
Port latch
(3) Port P11
P-channel output disable bit
(2) Port P10
(4) Port P12(5) Port P13
Data bus
Direction
register
P10,P12,P13 input
level selection bit
SCLK pin selection bit
Port latch
Serial I/O2 clock output
Serial I/O2 clock input Serial I/O2 clock output
Serial I/O2 clock input
P10,P12,P13 input
level selection bit
Data bus
Direction
register
Signals during the
SDATA output action
Port latch
SDATA pin selection bit
SDATA pin
selection bit
: P10, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Transmit enable bit
When the TTL level is selected, there is no hysteresis characteristics.
*
**
*
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 19 of 55
REJ09B0178-0300
Fig. 17 Block diagram of ports (2)
(9) Ports P36, P37
Data bus Port latch
Pull-up control
INT interrupt input
*
(7) Ports P20–P27
Analog input pin selection bit
A/D converter input
Data bus Port latch
(8) Ports P30–P35
Data bus Port latch
Pull-up control
(6) Ports P14
CNTR
0 interrupt input
Direction register
Data bus Port latch
Pulse output mode
Timer output
P37/INT0 input
level selection bit
(10) Ports P15, P16, P40, P41
Data bus Port latch
Direction register
Direction register
Direction register
Direction register
: P10, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
*
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 20 of 55
REJ09B0178-0300
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status regis-
ter are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1, CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Remarks
Non-maskable
Valid in UART mode
Valid in USB mode
Valid in UART mode
Valid in USB mode
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
selectable)
Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 inter-
nal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR0 and A/D interrupt sources
with bit 7 of the interrupt edge selection register, timer 2 and serial I/
O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt
sources with bit 5, and serial I/O transmit and INT1 interrupt sources
with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the in-
terrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Priority
1
2
3
4
5
6
7
8
9
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of UART data receive
At detection of IN token
At completion of UART transmit shift or
when transmit buffer is empty
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
At detection of either rising or falling edge
of INT1 input
At detection of either rising or falling edge
of INT0 input
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR0 input
At completion of A/D conversion
At BRK instruction execution
Interrupt source
Reset (Note 2)
UART receive
USB IN token
UART transmit
USB SETUP/OUT token
Reset/Suspend/Resume
INT1
INT0
Timer X
Key-on wake-up
Timer 1
Timer 2
Serial I/O2
CNTR0
A/D conversion
BRK instruction
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 21 of 55
REJ09B0178-0300
Fig. 18 Interrupt control
Fig. 19 Structure of Interrupt-related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7 b0
b7 b0
Interrupt edge selection register
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
Serial I/O1 or INT1 interrupt selection bit
0 : Serial I/O1
1 : INT1
Timer X or key-on wake up interrupt selection bit
0 : Timer X
1 : Key-on wake up
Timer 2 or serial I/O2 interrupt selection bit
0 : Timer 2
1 : Serial I/O2
CNTR0 or AD converter interrupt selection bit
0 : CNTR0
1 : AD converter
(INTEDGE : address 003A16)
Interrupt request register 1
UART receive/USB IN token interrupt request bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt request bit
INT0 interrupt request bit
Timer X or key-on wake up interrupt request bit
Timer 1 interrupt request bit
Timer 2 or serial I/O2 interrupt request bit
CNTR0 or AD converter interrupt request bit
Not used (returns “0” when read) 0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
b7 b0 Interrupt control register 1
UART receive/USB IN token interrupt enable bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt enable bit
INT0 interrupt enable bit
Timer X or key-on wake up interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 or serial I/O2 interrupt enable bit
CNTR0 or AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit) 0 : Interrupts disabled
1 : Interrupts enabled
(ICON1 : address 003E16)
1
1
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 22 of 55
REJ09B0178-0300
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L” level
to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in Fig-
ure 20, where an interrupt request is generated by pressing one of
the keys provided as an active-low key matrix which uses ports P00
to P03 as input ports.
Fig. 20 Connection example when using key input interrupt and port P0 block diagram
Port PXx
“L” level output
PULL register
bit 3 = “0”
Port P0
7
latch
Port P0
7
Direction register = “1”
***
P0
7
output
Key input interrupt request
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS output buffer
PULL register
bit 3 = “0”
Port P0
6
latch
Port P0
6
Direction register = “1”
***
P0
6
output
PULL register
bit 3 = “0”
Port P0
5
latch
Port P0
5
Direction register = “1”
***
P0
5
output
PULL register
bit 3 = “0”
Port P0
4
latch
Port P0
4
Direction register = “1”
***
P0
4
output
PULL register
bit 2 = “1”
Port P0
3
latch
Port P0
3
Direction register = “0”
***
P0
3
input
PULL register
bit 2 = “1”
Port P0
2
latch
Port P0
2
Direction register = “0”
***
P0
2
input
PULL register
bit 1 = “1”
Port P0
1
latch
Port P0
1
Direction register = “0”
***
P0
1
input
PULL register
bit 0 = “1”
Port P0
0
latch
Port P0
0
Direction register = “0”
***
P0
0
input
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 23 of 55
REJ09B0178-0300
Timers
The 7534 Group has 3 timers: timer X, timer 1 and timer 2.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the inter-
rupt request bit corresponding to each timer is set to “1”.
●Timer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always
count the prescaler output and periodically sets the interrupt request
bit.
●Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
• Timer Mode
The timer counts the signal selected by the timer X count source
selection bit.
• Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bit, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the output of the
CNTR0 pin is started with an “H” output.
At “1”, this output is started with an “L” output. When using a timer in
this mode, set the port P14 direction register to output mode.
• Event Counter Mode
The operation in the event counter mode is the same as that in the
timer mode except that the timer counts the input signal from the
CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the timer counts
the rising edge of the CNTR0 pin. When this bit is “1”, the timer
counts the falling edge of the CNTR0 pin.
• Pulse Width Measurement Mode
When the CNTR0 active edge switch bit is “0”, the timer counts the
signal selected by the timer X count source selection bit while the
CNTR0 pin is “H”. When this bit is “1”, the timer counts the signal
while the CNTR0 pin is “L”.
In any mode, the timer count can be stopped by setting the timer X
count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
Fig. 21 Structure of timer X mode register
Fig. 22 Timer count source set register
Timer X mode register
(TM : Address 002B
16
)
CNTR
0
active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
Not used (return “0” when read)
Timer X count stop bit
0 : Count start
1 : Count stop
b7 b0
Timer count source set register
(TCSS : Address 002E
16
)
b7 b0
Timer X count source selection bit (Note)
0 : f(X
IN
)/16
1 : f(X
IN
)/2
Not used (return “0” when read)
Note : To switch the timer X count source selection bit ,
stop the timer X count operation.
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 24 of 55
REJ09B0178-0300
Fig. 23 Block diagram of timer X, timer 1 and timer 2
Timer mode
pulse output mode
Q
R
To timer X
interrupt
request bit
f(X
IN
)/16 Timer X latch (8)
Timer X (8)
Prescaler X latch (8)
Prescaler X (8)
Pulse width
measurement
mode
f(X
IN
)/2
Timer X count
source selection bit
Event
counter
mode Timer X count stop bit
Port P1
4
direction
register
Q
“0”
“1”
CNTR
0
active
edge switch bit
Port P1
4
latch
Pulse output mode
“1”
“0”
CNTR
0
active
edge switch bit
P1
4
/CNTR
0
Toggle
flip-flop
Timer X latch write
Pulse output mode
T
To CNTR
0
interrupt
request bit
Data bus
To timer 1
interrupt
request bit
To timer 2
interrupt
request bit
Data bus
Prescaler 12 (8)
f(X
IN
)/16 Timer 1 (8) Timer 2 (8)
Timer 2 latch (8)Timer 1 latch (8)Prescaler 12 latch (8)
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 25 of 55
REJ09B0178-0300
Fig. 24 Block diagram of UART serial I/O1
Fig. 25 Operation of UART serial I/O1 function
Serial Interface
●Serial I/O1
• Asynchronous serial I/O (UART) mode
Serial I/O1 can be used as an asynchronous (UART) serial I/O. A
dedicated timer (baud rate generator) is also provided for baud rate
generation when serial I/O1 is in operation.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identi-
cal.
Each of the transmit and receive shift registers has a buffer register
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the trans-
mit buffer, and receive data is read from the respective buffer regis-
ters. These buffer registers can also hold the next data to be trans-
mitted and receive 2-byte receive data in succession.
By selecting “1” for continuous transmit valid bit (bit 2 of SIO1CON),
continuous transmission of the same data is made possible.
This can be used as a simplified PWM.
OE
PE FE
1/16
X
IN
1/4
1/16
Data bus
Receive Buffer Register
Address
(0018
16
)
Receive Shift Register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST Detector
SP Detector UART Control Register
Address (001A
16
)
Character length selection bit
7-bit
8-bit
Address (001B
16
)
Clock Control Circuit
Baud Rate Generator
Division ratio 1/(n+1)
Address (001C
16
)
BRG count source selection bit
Transmit Buffer Register
Data bus
Transmit Shift Register
Address
(0018
16
)
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address (0019
16
)
Character length selection bit
Transmit interrupt source selection bit
Continuous transmit valid bit
Serial I/O1 control register
P1
0
/R
X
D
P1
1
/T
X
D
Serial I/O1 status register
ST/SP/PA Generator
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1*
STD
0
D
1
SP D
0
D
1
ST SP
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer at TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Notes
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
Serial Output T
X
D
Receive Buffer Register
Read Signal
Serial Input R
X
D
* Generated at second bit in 2-stop -bit
mode
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 26 of 55
REJ09B0178-0300
[Serial I/O1 control register] SIO1CON
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART control register] UARTCON
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer. One bit in this register (bit 4) is al-
ways valid and sets the output structure of the P11/TxD pin.
[UART status register] UARTSTS
The read-only UART status register consists of seven flags (bits 0 to
6) which indicate the operating status of the UART function and vari-
ous errors. This register functions as the UART status register
(UARTSTS) when selecting the UART.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is trans-
ferred from the receive shift register to the receive buffer, and the
receive buffer full flag is set. A write to the UART status register clears
all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively).
Writing “0” to the serial I/O1 mode selection bits MOD1 and MOD0
(bit 7 and 6 of the Serial I/O1 control register ) also clears all the
status flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “8116” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the continuous transmit valid bit (bit 2)
becomes “1”.
[Transmit/Receive buffer register] TB/RB
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7-bit, the MSB of data stored in
the receive buffer is “0”.
Fig. 26 Continuous transmission operation of UART serial I/O
[Baud Rate Generator] BRG
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
TSC=0
TBE=1
TBE=0
STD
0
D
1
SP D
0
D
1
ST SP ST
1 : When the serial I/O1 mode selection bits (b7, b6) is “10”, the transmit enable bit is “1”, and continuous transmit valid bit is “1”, writing on the
transmit buffer initiates continuous transmission of the same data.
2 : Select 0 for continuous transmit valid bit to stop continuous transmission.
The T
X
D pin will stop at high level after completing transmission of 1 byte.
3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after
completing transmission of 1 byte.
Notes
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
Serial Output T
X
D
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 27 of 55
REJ09B0178-0300
• Universal serial bus (USB) mode
By setting bits 7 and 6 of the serial I/O1 control register (address
001A16) to “11”, the USB mode is selected. This mode conforms to
Low-Speed USB2.0 specification. In this mode serial I/O1 interrupt
have 6 sources; USB in and out token receive, set-up token receive,
USB reset, suspend, and resume. The USB status/UART status
Fig. 28 USB transceiver block diagram
register functions as the USB status register (USBSTS).There is
the USBVREFOUT pin for the USB reference voltage output, and a D-
line with 1.5 kΩ external resistor can be pull up. USB mode block
and USB transceiver block show in figures 27 and 28.
Fig. 27 USB mode block diagram
XIN
Address 001816
Receive shift register
RxRDY
Receive buffer register
SYNC decoder
PID decoder
RxPID
OPID
PIDE
Address
comparative unit
USBA
End pointer
decoder
RxEP
CRC check
CRCE
Reset interrupt request
Suspend interrupt request
Resume interrupt request
Token interrupt request
EOP
NRZI,
bit stuffing decoder
BSTFE
Bus state
detection
Digital
PLL
6 MHz
USB
transceiver
NRZI,
bit stuffing encoder
Data bus
Data bus
Address 001816
Transmit shift register
TxRDY
Transmit buffer register
EP0BYTE
EP1BYTE
SYNC, PID
generating unit
EP0PID
EP1PID
CRC encoder
EOP generating unit
USB transmit unit
P10/D-
P11/D+
Differential input and
Single end input
Output data and
I/O control
1.5 MHz
Serial I/O1 control register
MOD0
MOD1
USB reference
power source voltage
USB control register
UVOE
(initial value “0”)
Output enable signal
Voltage input Output amplifier USBVREFOUT
D+/D-
output amplifier
Internal D- output signal
Internal D+ output signal
D-
D+
Suspend
OE
(internal signal)
Signal for function stop
Output enable signal
-
+
Differential input
Single end input
Single end input
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 28 of 55
REJ09B0178-0300
Fig. 29 Structure of serial I/O1-related registers (1)
b7 b0
b7 b0
USB status register
(USBSTS: address 0019
16
)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
EOP detection flag
0: Not detected
1: Detect
False EOP error flag
0: No error
1: False EOP error
CRC error flag
0: No error
1: CRC error
PID error flag
0: No error
1: PID error
Bit stuffing error flag
0: No error
1: Bit stuffing error
Summing error flag
0: No error
1: Summing error
Receive buffer full flag
0: Buffer empty
1: Buffer full
b7 b0
Transmit buffer register
(TB: address 0018
16
)
After setting data to address 0018
16
, a content of the
transmit buffer register transfers to the transmit shift
register automatically.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Receive buffer register
(RB: address 0018
16
)
By reading data from address 0018
16
, a content of the
receive buffer register can be read out.
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 29 of 55
REJ09B0178-0300
Fig. 30 Structure of serial I/O1-related registers (2)
Not used (return “1” when read)
Endpoint 1 enable
0: Endpoint 1 invalid
1: Endpoint 1 valid
USB reset interrupt enable
0: USB reset invalid
1: USB reset valid
Resume interrupt enable
0: Resume invalid
1: Resume valid
Token interrupt enable
0: Token invalid
1: Token valid
USB enable flag
0: USB invalid
1: USB valid
b7 b0
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
USB data toggle synchronization register
(TRSYNC: address 001D16)
Not used (return “1” when read)
Sequence bit toggle flag
0: No toggle
1: Sequence toggle
b7 b0
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
USB interrupt source discrimination register 1
(USBIR1: address 001E16)
Not used (return “1” when read)
Endpoint determination flag
0: Endpoint 0 interrupt
1: Endpoint 1 interrupt
b7 b0
b7 b0
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
USB interrupt source discrimination register 2
(USBIR2: address 001F16)
Not used (return “1” when read)
Suspend request flag
0: No request
1: Suspend request
USB reset request flag
0: No request
1: Reset request
Not used (return “1” when read)
Token PID determination flag
0: SETUP interrupt
1: OUT interrupt
Token interrupt flag
0: No request
1: Token request
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
USB interrupt control register
(USBICON: address 002016)
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 30 of 55
REJ09B0178-0300
Fig. 31 Structure of serial I/O1-related registers (3)
b
7
b
0
U
S
B
t
r
a
n
s
m
i
t
d
a
t
a
b
y
t
e
n
u
m
b
e
r
s
e
t
r
e
g
i
s
t
e
r
1
(
E
P
1
B
Y
T
E
:
a
d
d
r
e
s
s
0
0
2
2
1
6
)
S
e
t
a
n
u
m
b
e
r
o
f
d
a
t
a
b
y
t
e
f
o
r
t
r
a
n
s
m
i
t
t
i
n
g
w
i
t
h
e
n
d
p
o
i
n
t
1
.
C
P
U
r
e
a
d
:
E
n
a
b
l
e
d
C
P
U
w
r
i
t
e
:
S
e
t
/
C
l
e
a
r
H
a
r
d
w
a
r
e
r
e
a
d
:
U
s
e
d
H
a
r
d
w
a
r
e
w
r
i
t
e
:
N
o
t
u
s
e
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
b
7
b
0
U
S
B
t
r
a
n
s
m
i
t
d
a
t
a
b
y
t
e
n
u
m
b
e
r
s
e
t
r
e
g
i
s
t
e
r
0
(
E
P
0
B
Y
T
E
:
a
d
d
r
e
s
s
0
0
2
1
1
6
)
S
e
t
a
n
u
m
b
e
r
o
f
d
a
t
a
b
y
t
e
f
o
r
t
r
a
n
s
m
i
t
t
i
n
g
w
i
t
h
e
n
d
p
o
i
n
t
0
.
C
P
U
r
e
a
d
:
E
n
a
b
l
e
d
C
P
U
w
r
i
t
e
:
S
e
t
/
C
l
e
a
r
H
a
r
d
w
a
r
e
r
e
a
d
:
U
s
e
d
H
a
r
d
w
a
r
e
w
r
i
t
e
:
N
o
t
u
s
e
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
b
7
b
0
USB address register
(USBA: address 0025
16
)
S
e
t
a
n
a
d
d
r
e
s
s
a
l
l
o
c
a
t
e
d
b
y
t
h
e
U
S
B
h
o
s
t
.
C
P
U
r
e
a
d
:
D
i
s
a
b
l
e
d
C
P
U
w
r
i
t
e
:
S
e
t
/
C
l
e
a
r
H
a
r
d
w
a
r
e
r
e
a
d
:
U
s
e
d
H
a
r
d
w
a
r
e
w
r
i
t
e
:
N
o
t
u
s
e
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
1
”
w
h
e
n
r
e
a
d
)
USB PID control register 1
(EP1PID: address 0024
16
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
1
”
w
h
e
n
r
e
a
d
)
E
n
d
p
o
i
n
t
1
P
I
D
s
e
l
e
c
t
i
o
n
f
l
a
g
1
x
:
I
N
t
o
k
e
n
i
n
t
e
r
r
u
p
t
o
f
D
A
T
A
0
/
1
i
s
v
a
l
i
d
0
1
:
S
T
A
L
L
h
a
n
d
s
h
a
k
e
i
s
v
a
l
i
d
f
o
r
I
N
t
o
k
e
n
0
0
:
N
A
K
h
a
n
d
s
h
a
k
e
i
s
v
a
l
i
d
f
o
r
I
N
t
o
k
e
n
b7 b0
x: any data
b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
b
7
b
0
USB PID control register 0
(EP0PID: address 0023
16
)
Not used (return “1” when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NAK handshake is valid for IN token
xxx1: STALL handshake is val id for OUT token (Note)
xx10: ACK handshake is valid for OUT token
xx00: NAK handshake is valid for OUT token
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
x: any data
Note: In the status stage of the control read transfer, when PID
o
f
d
a
t
a
p
a
c
k
e
t
=
D
A
T
A
0
(
i
n
c
o
r
r
e
c
t
P
I
D
)
,
t
h
i
s
b
i
t
i
s
s
e
t
f
o
r
c
i
b
l
y
b
y
h
a
r
d
w
a
r
e
a
n
d
S
T
A
L
L
h
a
n
d
s
h
a
k
e
i
s
v
a
l
i
d
.
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 31 of 55
REJ09B0178-0300
Fig. 32 Structure of serial I/O1-related registers (4)
USB sequence bit initialization register
(INISQ1: address 0026
16
)
A sequence bit of endpoint 1 is initialized.
CPU read: Disabled
CPU write: Dummy
Hardware read: Not used
Hardware write: Not used
b7 b0
b7 b0
b7 b0
b7 b0
USB control register
(USBCON: address 0027
16
)
Not used (return “1” when read)
USBVREFOUT output valid flag
0: Output off
1: Output on
Remote wake up request flag
0: No request
1: Remote wake up request
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set
Hardware read: Used
Hardware write: Clear
UART status register
(UARTSTS: address 0019
16
)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
Receive buffer full flag
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
0: No error
1: Overrun error
Parity error flag
0: No error
1: Parity error
Framing error flag
0: No error
1: Framing error
Summing error flag
0: No error
1: Summing error
Not used (returns “1” when read)
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
Baud rate generator
(BRG: address 001C
16
)
This register is valid only when selecting the UART mode.
A baud rate value is set.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 32 of 55
REJ09B0178-0300
Fig. 33 Structure of serial I/O1-related registers (5)
UART control register
(UARTCON: address 001B16)
Character length selection bit
0: 8 bits
1: 7 bits
Parity enable bit
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit
0: Even parity
1: Odd parity
Stop bit length selection bit
0: 1 stop bit
1: 2 stop bits
P-channel output disable bit
0: CMOS output
1: N-channel open-drain output
Not used (returns “1” when read)
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7 b0
b7 b0 Serial I/O1 control register
(SIO1CON: address 001A16)
BRG count source selection bit
0: f(XIN)
1: f(XIN)/4
Not used (returns “1” when read)
Continuous transmit valid bit
0: Continuous transmit invalid
1: Continuous transmit valid
Transmit interrupt source selection bit
0: Interrupt when transmit buffer has
emptied
1: Interrupt when transmit shift
operation is completed
Transmit enable bit
0: Transmit disabled
1: Transmit enabled
Receive enable bit
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bits
00: I/O port
01: Not available
10: UART mode
11: USB mode
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 33 of 55
REJ09B0178-0300
Note on using USB mode
Handling of SE0 signal in program (at receiving)
7534 group has the border line to detect as USB RESET or EOP
(End of Packet) on the width of SE0 (Single Ended 0).
A response apposite to a state of the device is expected.
The name of the following short words which is used in table 5 shows
as follow.
•TKNE: Token interrupt enable (bit 6 of address 2016)
•RSME: Resume interrupt enable (bit 5 of address 2016)
•RSTE: USB reset interrupt enable (bit 4 of address 2016)
•Spec: A response of the device requested by Low-Speed USB2.0
specification
•SIE: Hardware operation in 7534 group
•F/W: Recommendation process in the program
•FEOPE: False EOP error flag (bit 2 of address 1916)
•RxPID: Token interrupt flag (bit 7 of address 1F16)
Spec
SIE
F/W
Reset or resume
Reset interrupt
request
Reset interrupt
processing
Resume interrupt
processing
Table 7 Relation of the width of SE0 and the state of the device
Width of SE0
0 µs
0.5 µs
0.5 µs
2.5 µs
2.5 µs
2.67 µs
2.67 µs
Spec
SIE
F/W
Spec
SIE
F/W
Spec
SIE
F/W
Spec
SIE
F/W
Idle state
TKNE = X
RSME = 0
RSTE =1
Ignore
Keep counting suspend
timer
Not acknowledge
Keep alive
Initialize suspend timer
count value
Not acknowledge
Keep alive or Reset
may determine as keep
alive and Reset interrupt
Keep alive in case of no
interrupt request
Reset processing in case
of interrupt request
Reset
Reset interrupt request
Reset processing
End of Token in transaction
TKNE = 1
RSME = 0
RSTE =1
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
time out. FEOPE flag is
set.)
Not acknowledge
EOP
Token interrupt request
Token interrupt processing
execute
EOP or Reset
may determine as EOP and
Reset interrupt
RxPID = 1> Token interrupt
processing
RxPID = 0> Reset interrupt
processing
Reset
Reset interrupt request
Reset processing
End of data or handshake
in transaction
TKNE = 0
RSME = 0
RSTE = 0 or 1
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
timeup. FEOPE flag is
set.)
Wait for the next EOP flag
EOP
Set EOP flag
After checking the set of
EOP flag, go to the next
processing
EOP or Reset
may determine as EOP
and Reset interrupt
Continue the processing
in case of no interrupt
request
Reset processing in case
of interrupt request
Reset
Reset interrupt request
Reset processing
Suspend state
TKNE = 0
RSME = 1
RSTE = 0
State of device
• Function of USBPID control register 0 (address 002316)
Bit 4 (STALL handshake control for OUT token) of this register is forcibly set by SIE under the special condition shown below.
Set condition; when PID of data packet = DATA0 (incorrect PID) in the status stage of the control read transfer.
• SYNC field at reception
Normally, the SYNC field consists of “KJKJKJKK” (8 bits). However, as for SIE of the 7534 Group, when the low-order 6 bits are “KJKJKK”, it is
determined as SYNC.
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 34 of 55
REJ09B0178-0300
●Serial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
• For receiving, set “0” to bit 3.
• When receiving, bit 7 is cleared by writing dummy data to serial I/
O2 register after shift is completed.
• Bit 7 is set earlier a half cycle of shift clock than completion of shift
operation. Accordingly, when checking shift completion by using
this bit, the setting is as follows:
(1) check that this bit is set to “1”,
(2) wait a half cycle of shift clock,
(3) read/write to serial I/O2 register. Fig. 34 Structure of serial I/O2 control registers
Fig. 35 Block diagram of serial I/O2
Serial I/O2 control register
(SIO2CON: address 0030
16
)
S
DATA
pin selection bit (Note)
0 : I/O port/S
DATA
input
1 : S
DATA
output
Internal synchronous clock selection bits
000 : f(X
IN
)/8
001 : f(X
IN
)/16
010 : f(X
IN
)/32
011 : f(X
IN
)/64
110 : f(X
IN
)/128
111 : f(X
IN
)/256
b7 b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK
pin selection bit
0 : External clock (S
CLK
is an input)
1 : Internal clock (S
CLK
is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note : When using it as an S
DATA
input, set the port P1
3
direction register to “0”.
“1”
“0”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
XIN
Data bus
Serial I/O2
interrupt request
SDATA pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
SCLK pin selection bit
Internal synchronous
clock selection bits
Divider
P12/SCLK
P13/SDATA
P12 latch
SCLK pin
selection bit
SCLK
P13 latch
SDATA pin selection bit
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 35 of 55
REJ09B0178-0300
D0
Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA pin is set to the input mode,
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
SDATA at serial I/O2
input receive
SDATA at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
D1D2D3D4D5D6D7
the SDATA pin is in a high impedance state after the data transfer is completed.
Serial I/O2 operation
By writing to the serial I/O2 register(address 003116) the serial I/O2
counter is set to “7”.
After writing, the SDATA pin outputs data every time the transfer clock
shifts from a high to a low level. And, as the transfer clock shifts from
a low to a high, the SDATA pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set.
Also, the SDATA pin is in a high impedance state after the data trans-
fer is complete. Refer to Figure 36.
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the SDATA pin is not in a high impedance state on the completion
of data transfer.
Fig. 36 Serial I/O2 timing (LSB first)
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 36 of 55
REJ09B0178-0300
A/D Converter
The functional blocks of the A/D converter are described below.
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/D
conversion.
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion
bit. The value of this bit remains at “0” during A/D conversion, and
changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0” except during an A/
D conversion.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between VSS
and VREF by 1024 by a resistor ladder, and outputs the divided volt-
ages. Since the generator is disconnected from VREF pin and VSS
pin, current is not flowing into the resistor ladder.
[Channel Selector]
The channel selector selects one of ports P27/AN7 to P20/AN0, and
inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD interrupt
request bit to “1”. Because the comparator is constructed linked to a
capacitor, set f(XIN) to 500 kHz or more during A/D conversion.
Fig. 37 Structure of A/D control register
Fig. 38 Structure of A/D conversion register
Fig. 39 Block diagram of A/D converter
A
/
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
41
6)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
b
7
b
0
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : P26/AN6
111 : P27/AN7
A
/
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
d
d
r
e
s
s
0
0
3
41
6
)
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
A
/
D
c
o
n
t
r
o
l
c
i
r
c
u
i
t
R
e
s
i
s
t
o
r
l
a
d
d
e
r
VSS
Comparator
A/D interrupt request
b7 b0
D
a
t
a
b
u
s
3
1
0
P
20/
A
N0
P
21/
A
N1
P
22/
A
N2
P23/AN3
P
24/
A
N4
P
25/
A
N5
P
26/
A
N6
P
27/
A
N7
A/D conversion register (low-order)
(
A
d
d
r
e
s
s
0
0
3
61
6)
(Address 003516)
A/D conversion register (high-order)
VREF
Read 8-bit (Read out only address 0035
16
)
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
(Address 0035
16
)
Read 10-bit (read out in order address 0036
16
, 0035
16
)
b7 b0
b9 b8
(Address 0036
16
)
b7 b0
b7 b6 b5 b4 b3 b2 b1 b0
(Address 0035
16
)
High-order 6-bit of address 0036
16
returns “0” when read.
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 37 of 55
REJ09B0178-0300
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an 8-
bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register
(address 003916) is not set after reset. Writing an optional value to
the watchdog timer control register (address 003916) causes the
watchdog timer to start to count down. When the watchdog timer H
underflows, an internal reset occurs. Accordingly, it is programmed
that the watchdog timer control register (address 003916) can be set
before an underflow occurs.
When the watchdog timer control register (address 003916) is read,
the values of the high-order 6-bit of the watchdog timer H, STP in-
struction disable bit and watchdog timer H count source selection bit
are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address
003916), the watchdog timer H is set to “FF16” and the watchdog
timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal.
The detection time is 174.763 ms at f(XIN)=6 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 683 µs at f(XIN)=6 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can be
disabled by bit 6 of the watchdog timer control register (address
003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal
reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Fig. 40 Block diagram of watchdog timer
Fig. 41 Structure of watchdog timer control register
X
IN
Data bus
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP Instruction Disable Bit
Watchdog timer H (8)
Write “FF
16
” to the
watchdog timer
control register
Internal reset
RESET
Watchdog timer L (8)
STP Instruction
Write “FF
16
” to the
watchdog timer
control register
Watchdog timer control register(address 003916)
WDTCON
Watchdog timer H (read-only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
b7 b0
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 38 of 55
REJ09B0178-0300
Reset Circuit
The microcomputer is put into a reset status by holding the RESET
pin at the “L” level for 15 µs or more when the power source voltage
is 4.1 to 5.5 V and XIN is in stable oscillation.
After that, this reset status is released by returning the RESET pin to
the “H” level. The program starts from the address having the con-
tents of address FFFD16 as high-order address and the contents of
address FFFC16 as low-order address.
Note that the reset input voltage should be 0.82 V or less when the
power source voltage passes 4.1 V.
Fig. 42 Example of reset circuit
Fig. 43 Timing diagram at reset
(Note)
0.2 VCC
0 V
0 V
Poweron
VCCRESET
VCC
RESET
Power source
voltage
detection circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage Vcc = 4.1 V
D
a
t
a
A
d
d
r
e
s
s
8
-
1
3
c
l
o
c
k
c
y
c
l
e
s
Reset address from the
vector table
1
:
A
n
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
a
p
p
l
i
e
s
a
b
o
u
t
2
5
0
k
H
z
f
r
e
q
u
e
n
c
y
a
s
c
l
o
c
k
f
a
t
a
v
e
r
a
g
e
o
f
V
c
c
=
5
V
.
2
:
T
h
e
m
a
r
k
“
?
”
m
e
a
n
s
t
h
a
t
t
h
e
a
d
d
r
e
s
s
i
s
c
h
a
n
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e
a
b
l
e
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e
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e
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d
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o
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e
p
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v
i
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u
s
s
t
a
t
e
.
3
:
T
h
e
s
e
a
r
e
a
l
l
i
n
t
e
r
n
a
l
s
i
g
n
a
l
s
e
x
c
e
p
t
R
E
S
E
T
Notes
φ
RESET
RESET
OUT
SYNC
?
?
FFFC F
F
F
D
AD
H
,AD
L
?
?
?
?
?
A
D
L
A
D
H
?
?
?
Clock from on-chip
oscillator
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 39 of 55
REJ09B0178-0300
Fig. 44 Internal status of microcomputer at reset
Serial I/O1 control register
UART control register
(
8
)
(
9
)
Prescaler 12
Timer 1
Timer 2
Timer X mode register
Prescaler X
Timer X
Timer count source set register
Serial I/O2 control register
A/D control register
MISRG
Watchdog timer control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt control register 1
Processor status register
Program counter
(
2
1
)
(22)
(23)
(
2
4
)
(
2
5
)
(26)
(27)
(
2
8
)
(
2
9
)
(
3
0
)
(31)
(
3
2
)
(
3
3
)
(
3
4
)
(35)
(
3
6
)
(
3
7
)
(
6
)
USB/UART status register
(
7
)
USB data toggle synchronization register
(
1
0
)
USB interrupt source discrimination register 1
(
1
1
)
USB interrupt source discrimination register 2
(
1
2
)
USB interrupt control register
(13)
USB transmit data byte number set register 0
(
1
4
)
USB transmit data byte number set register 1
(15)
USBPID control register 0
(
1
6
)
USBPID control register 1
(
1
7
)
USB address register
(
1
8
)
USB sequence bit initialization register
(19)
USB control register
(20)
001A
16
001B
16
02
16
11100000
Contents of address FFFC
16
(PC
H
)
(PC
L
)
FF
16
01
16
00
16
00
16
FF
16
FF
16
00
16
00
16
10
16
00
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
0030
16
0034
16
0038
16
0039
16
003A
16
003B
16
003C
16
003E
16
(PS)
N
o
t
e
X
:
U
n
d
e
f
i
n
e
d
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
D
1
6
00111111
00
16
00
16
00
16
10000000
X
X
X
X
X1XX
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
(
1
)
(
2
)
(
3
)
(4)
(
5
)
Register contents
00
16
00
16
0001
16
0003
16
0005
16
0007
16
0009
16
X
00000
Address
0019
16 10000001
001D
16 01111111
001E
16 01111111
001F
16 01110011
0020
16 00000111
0021
16
0022
16
0023
16 00000111
0024
16 00111111
0025
16 10000000
0026
16 11111111
0027
16 00111111
00
16
00
16
Pull-up control register
FF
16
0016
16
X
X
X
00
X
X
X
00
16
00
HARDWARE
7534 Group FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 40 of 55
REJ09B0178-0300
Fig. 45 External circuit of ceramic resonator
Fig. 46 External clock input circuit
Fig. 47 Structure of MISRG
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between XIN and XOUT since a feed-back resistor exists on-chip. (An
external feed-back resistor may be needed depending on conditions.)
●Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set to
“0116” and prescaler 12 is set to “FF16” when the oscillation
stabilization time set bit after release of the STP instruction is “0”.
On the other hand, timer 1 and prescaler 12 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used.
f(XIN)/16 is forcibly connected to the input of prescaler 12.
When an external interrupt is accepted, oscillation is restarted but
the internal clock φ remains at “H” until timer 1 underflows. As soon
as timer 1 underflows, the internal clock φ is supplied. This is
because when a ceramic oscillator is used, some time is required
until a start of oscillation.
In case oscillation is restarted by reset, no wait time is generated.
______
So apply an “L” level to the RESET pin while oscillation becomes
stable.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts
if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or WIT
state, interrupt enable bits must be set to “1” before the STP or
WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will start
counting clock which is XIN divided by 16, so set the timer 1 inter-
rupt enable bit to “0” before the STP instruction is executed.
Note
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Clock mode
Operation is started by an on-chip oscillator after releasing reset.
A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the
CPU mode register after releasing it.
XIN XOUT
External oscillation
circuit
VCC
VSS
Open
MISRG(Address 003816)
b7 b0
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF16”
in prescaler 12 automatically
1: Not set automatically
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
XIN
COUT
CIN
XO
U
T
R
d
(N
o
t
e)
N
o
t
e
:
I
n
s
e
r
t
a
d
a
m
p
i
n
g
r
e
s
i
s
t
o
r
i
f
r
e
q
u
i
r
e
d
.
T
h
e
r
e
s
i
s
t
a
n
c
e
w
i
l
l
v
a
r
y
d
e
p
e
n
d
i
n
g
o
n
t
h
e
o
s
c
i
l
l
a
t
o
r
a
n
d
t
h
e
o
s
c
i
l
l
a
t
i
o
n
d
r
i
v
e
c
a
p
a
c
i
t
y
s
e
t
t
i
n
g
.
U
s
e
t
h
e
v
a
l
u
e
r
e
c
o
m
m
e
n
d
e
d
b
y
t
h
e
m
a
k
e
r
o
f
t
h
e
o
s
c
i
l
l
a
t
o
r
.
A
l
s
o
,
i
f
t
h
e
o
s
c
i
l
l
a
t
o
r
m
a
n
u
f
a
c
t
u
r
e
r
'
s
d
a
t
a
s
h
e
e
t
s
p
e
c
i
f
i
e
s
t
h
a
t
a
f
e
e
d
b
a
c
k
r
e
s
i
s
t
o
r
b
e
a
d
d
e
d
e
x
t
e
r
n
a
l
t
o
t
h
e
c
h
i
p
t
h
o
u
g
h
a
f
e
e
d
b
a
c
k
r
e
s
i
s
t
o
r
e
x
i
s
t
s
o
n
-
c
h
i
p
,
i
n
s
e
r
t
a
f
e
e
d
b
a
c
k
r
e
s
i
s
t
o
r
b
e
t
w
e
e
n
X
I
N
a
n
d
XO
U
T
f
o
l
l
o
w
i
n
g
t
h
e
i
n
s
t
r
u
c
t
i
o
n
.
7534 Group
HARDWARE
FUNCTIONAL DESCRIPTION
Rev.3.00 Oct 23, 2006 page 41 of 55
REJ09B0178-0300
Fig. 48 Block diagram of system clock generating circuit (for ceramic resonator)
S
R
QS
R
Q
1
/
2
R
d
R
S
Q
R
f
1/4 1
/
2
W
I
T
i
n
s
t
r
u
c
t
i
o
nS
T
P
i
n
s
t
r
u
c
t
i
o
n
T
i
m
i
n
g
φ
(
I
n
t
e
r
n
a
l
c
l
o
c
k
)
S
T
P
i
n
s
t
r
u
c
t
i
o
n
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Reset
Interrupt disable flag l
H
i
g
h
-
s
p
e
e
d
m
o
d
e
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
Prescaler 12 Timer 1
Clock division ratio selection bit
Doubl e- s pe ed mo de
On-chip osc illa tor mode
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
(N
o
t
e
1)
Note 1: On-chip oscillator is used only for starting.
2: Although a feed-back resistor exists on-chip, an external feed-back
resistor may be needed depending on conditions.
X
OUT
X
I
N
1/8
M
i
d
d
l
e
-
s
p
e
e
d
,
H
i
g
h
-
s
p
e
e
d
,
d
o
u
b
l
e
-
s
p
e
e
d
m
o
d
e
Clock division ratio selection bit
On-c hi p osc i lla to
r
mode
(N
o
t
e
2)
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 42 of 55
REJ09B0178-0300
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the pre-
vious contents. For executing the instruction for the changed con-
tents, execute one instruction before executing the BBC or BBS in-
struction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag D to
“1”, then execute the ADC instruction or SBC instruction. In this
case, execute SEC instruction, CLC instruction or CLD instruction
after executing one instruction before the ADC instruction or SBC
instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency division
ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer X.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using di-
rection register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
• As for the 36-pin version, set "1" to each bit 6 of the port P3 direc-
tion register and the port P3 register.
• As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
A/D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A/D conversion.
Do not execute the STP instruction during A/D conversion.
Watchdog Timer
The internal reset may not be generated correctly in the middle-speed
mode, depending on the underflow timing of the watchdog timer.
When using the watchdog timer, operate the MCU in any mode other
than the middle-speed mode (i.e., high-speed, low-speed or double-
speed mode).
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned
in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the
XIN in double-speed mode, twice the XIN cycle in high-speed
mode and 8 times the XIN cycle in middle-speed mode.
Note on stack page
When 1 page is used as stack area by the stack page selection bit,
the area which can be used as stack depends on RAM size. Espe-
cially, be careful that the RAM area varies in Mask ROM version,
One Time PROM version and Emulator MCU.
NOTES ON USE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be lo-
cated too far from the pins to be connected, a ceramic or electrolytic
capacitor of 1.0 µF is recommended.
Handling of USBVREFOUT Pin
In order to prevent the instability of the USBVREFOUT output due to
external noise, connect a capacitor as bypass capacitor between
USBVREFOUT pin and GND pin (VSS pin). Besides, connect the ca-
pacitor to as close as possible. For bypass capacitor, a ceramic or
electrolytic capacitor of 0.22 µF is recommended.
USB Communication
• In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initial-
ization by software or USB reset by the host to prevent USB com-
munication from being terminated unexpectedly, for example due
to external causes such as noise.
• When USB suspend mode with TTL level on P10, P12, P13 input
level selection bit (bit 3 of address 1716) set to “1”, suspend current
as ICC might be greater than 300 µA as a spec.
[Countermeasure]
There are two countermeasures by software to avoid it as follows.
(1) Change from TTL input level to CMOS input level for P10, P12,
P13 port input.
(2) Change from TTL input level to CMOS input level before STP
instruction in suspend routine;
then after RESUME or Remote wake up interrupt, return to TTL
input level from CMOS input level. That is shown in Figure 49.
NOTES ON PROGRAMMING/NOTES ON USE
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 43 of 55
REJ09B0178-0300
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a
low-ohmic resistance, since it has the multiplexed function to be a
programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss pin
and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational inter-
ference even if it is connected via a resistor.
Electric Characteristic Differences Among
Mask ROM and One TIme PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM and One
Time PROM version MCUs due to the differences in the manufac-
turing processes.
When manufacturing an application system with One Time PROM
version and then switching to use of the mask ROM version, per-
form sufficient evaluations for the commercial samples of the
mask ROM version.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
S
U
S
P
E
N
D
R
o
u
t
i
n
e
R
E
S
U
M
E
R
o
u
t
i
n
e
S
T
P
Configuration to CMOS input
level for P1
0
, P1
2
, P1
3
input level.
Remote wake up Routine
P
1
P
3
C
x
x
x
x
x
0
x
x
2
C
o
n
f
i
g
u
r
a
t
i
o
n
t
o
C
M
O
S
i
n
p
u
t
l
e
v
e
l
f
o
r
P
1
0
,
P
1
2
,
P
1
3
i
n
p
u
t
l
e
v
e
l
.
P
1
P
3
C
x
x
x
x
x
1
x
x
2
C
o
n
f
i
g
u
r
a
t
i
o
n
t
o
T
T
L
i
n
p
u
t
l
e
v
e
l
f
o
r
P
1
0
,
P
1
2
,
P
1
3
i
n
p
u
t
l
e
v
e
l
.
P1P3C xxxxx1xx
2
C
o
n
f
i
g
u
r
a
t
i
o
n
t
o
T
T
L
i
n
p
u
t
l
e
v
e
l
f
o
r
P
1
0
,
P
1
2
,
P
1
3
i
n
p
u
t
l
e
v
e
l
.
C
o
n
f
i
g
u
r
a
t
i
o
n
t
o
T
T
L
i
n
p
u
t
l
e
v
e
l
f
o
r
P
1
0
,
P
1
2
,
P
1
3
i
n
p
u
t
l
e
v
e
l
.
Configuration to TTL input level
for P1
0
, P1
2
, P1
3
input level.
Fig. 49 Countermeasure (2) by software
Note on A/D Converter
Method to stabilize A/D Converter is described below.
(a) A/D conversion accuracy could be affected for Bus Powered*1
USB devices, while the communicating.
Figure 50 shows the method to stabilize A/D conversion accu-
racy, inserting a capacitor between Vref and VSS.
*1: Power supplied by USB VCC BUS.
(b) It is recommended for A/D accuracy to avoid converting while
USB communication, and use average value of several con-
verted values.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form
(three identical copies)
* For the mask ROM confirmation and the mark specifications,
refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
Fig. 50 Method to stabilize A/D conversion accuracy
A
N
0
t
o
A
N
7
Vc
c
C
N
Vs
s
1
µF
0
.
0
1
t
o
1
µF
V
r
e
f
Vs
s
1
t
o
1
0
kΩ
0
.
1
t
o
1
µF:
R
e
c
o
m
m
e
n
d
s
f
o
r
A
/
D
a
c
c
u
r
a
c
y
0.22 µF
7
5
3
4
G
r
o
u
p
1
.
5
kΩ
U
S
B
V
R
E
F
O
U
T
D
-
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 44 of 55
REJ09B0178-0300
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer us-
ing a special programming adapter. Set the address of PROM pro-
grammer in the user ROM area.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 51 is recommended to verify programming.
Package
PLQP0032GB-A
PRSP0036GA-A
PRDP0042BA-A
Name of Programming Adapter
PCA7435GPG03
PCA7435FP, PCA7435FPG02
PCA7435SP, PCA7435SPG02
Table 8 Special programming adapter
Fig. 51 Programming and testing of One Time PROM version
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution:
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 45 of 55
REJ09B0178-0300
Interrupt
7534 group permits interrupts on the 14 sources
for 42-pin version, 13 sources for 36-pin version
and 12 sources for 32-pin version. It is vector
interrupts with a fixed priority system. Accordingly,
when two or more interrupt requests occur during
the same sampling, the higher-priority interrupt is
accepted first. This priority is determined by
hardware, but variety of priority processing can be
performed by software, using an interrupt enable
bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt
priority, refer to “Table 9.”
Table 9 Interrupt sources, vector addresses and interrupt priority
FUNCTIONAL DESCRIPTION SUPPLEMENT
Remarks
Non-maskable
Valid in UART mode
Valid in USB mode
Valid in UART mode
Valid in USB mode
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
selectable)
Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: The INT1 interrupt does not exist in the 36-pin and 32-pin version.
4: The INT0 interrupt does not exist in the 32-pin version.
Vector addresses (Note 1)
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Priority
1
2
3
4
5
6
7
8
9
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of UART data receive
At detection of IN token
At completion of UART transmit shift or
when transmit buffer is empty
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
At detection of either rising or falling edge
of INT1 input
At detection of either rising or falling edge
of INT0 input
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR0 input
At completion of A/D conversion
At BRK instruction execution
Interrupt source
Reset (Note 2)
UART receive
USB IN token
UART transmit
USB SETUP/OUT token
Reset/Suspend/Resume
INT1 (Note 3)
INT0 (Note 4)
Timer X
Key-on wake-up
Timer 1
Timer 2
Serial I/O2
CNTR0
A/D conversion
BRK instruction
FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 46 of 55
REJ09B0178-0300
Timing After Interrupt
The interrupt processing routine begins with the
machine cycle following the completion of the
instruction that is currently in execution.
Figure 52 shows a timing chart after an interrupt
occurs, and Figure 53 shows the time up to execution
of the interrupt processing routine.
Fig. 52 Timing chart after an interrupt occurs
Fig. 53 Time up to execution of the interrupt processing routine
: CPU operation code fetch cycle
: Vector address of each interrupt
: Jump destination address of each interrupt
: “0016” or “0116”
SYNC
BL, BH
AL, AH
SPS
Data bus Not used PCHPCLPS ALAH
Address bus S
, SPS S-2, SPSS-1, SPS
PC BLBHAL, AH
SYNC
RD
WR
φ
Generation of interrupt request
Main routine Interrupt processing routine
7 to 14 cycles
(At performing 6.0 MHz, in double-speed mode,
1.17 µs to 2.34 µs)
2 cycles 5 cycles
Start of interrupt processing
0 to 7 cycles
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
FUNCTIONAL DESCRIPTION SUPPLEMENT
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 47 of 55
REJ09B0178-0300
A/D Converter
A/D conversion is started by setting AD conversion
completion bit to “0.” During A/D conversion, internal
operations are performed as follows.
1. After the start of A/D conversion, A/D conversion
register goes to “0016.”
2. The highest-order bit of A/D conversion register
is set to “1,” and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the
highest-order bit of A/D conversion register be-
comes “1.” When Vref > VIN, the highest-order
bit becomes “0.”
By repeating the above operations up to the lowest-
order bit of the A/D conversion register, an analog
value converts into a digital value.
A/D conversion completes at 122 clock cycles (20.34
µs at f(XIN) = 6.0 MHz) after it is started, and the
result of the conversion is stored into the A/D
conversion register.
Concurrently with the completion of A/D conversion,
A/D conversion interrupt request occurs, so that
the AD conversion interrupt request bit is set to
“1.”
Relative formula for a reference voltage VREF of A/D converter and Vref
When n = 0 Vref = 0
When n = 1 to 1023 Vref = ✕ n
n : the value of A/D converter (decimal numeral)
VREF
1024
✽1–✽10: A result of the first to tenth comparison
Table 10 Change of A/D conversion register during A/D conversion
At start of conversion
First comparison
Second comparison
Third comparison
After completion of
tenth comparison
100000
1000000
10000000
00000 000
VREF
2VREF
4
VREF ±
2
28
4
VREF VREF VREF
±±
A result of A/D conversion
✽1
✽1✽2
✽✽ ✽✽✽✽✽✽
12345678
Change of A/D conversion register Value of comparison voltage (Vref)
00
0
00
00
00
✽9✽10 21024
4
VREF VREF VREF
±±± •••
•
•
•
•
•
•
•
•
•
FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 48 of 55
REJ09B0178-0300
Figures 54 shows A/D conversion equivalent circuit,
and Figure 55 shows A/D conversion timing chart.
Fig. 54 A/D conversion equivalent circuit
Fig. 55 A/D conversion timing chart
ANi (i=0 to 7: 42-pin version, 36-pin version
i=0 to 5: 32-pin version)
C1
12 pF(Typical)
Notes 1: This is a parasitic diode.
2: Only the selected analog input pin is turned on.
C2
1.5 pF(Typical)
Chopper Amp.
A/D control circuit
Typical voltage
generation circuit
Switch tree,
ladder resistor
1.5 kΩ(Typical)
VSS VSS
VCC
VSS VREF
R
(Note 1)
SW1
(Note 2)
(Note 1)
W
r
i
t
e
s
i
g
n
a
l
f
o
r
A
/
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
AD conversion completion bit
S
a
m
p
l
i
n
g
c
l
o
c
k
122 X
IN
cycles
X
I
N
FUNCTIONAL DESCRIPTION SUPPLEMENT
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 49 of 55
REJ09B0178-0300
Stop mode
System enters the stop mode by executing the STP instruction. In the stop mode, the f(XIN) oscillation is
stopped, and the internal clock φ is stopped. Accordlingly, CPU and the peripheral devices are stopped.
(1) Stop mode state
Table 11 shows the state at stop mode.
Table 11 Stop mode state
Parameter
Oscillation
CPU
I/O port
Timer
UART
A/D conversion
Serial I/O2
USB
State
Stop
Stop
State retained at STP instruction
execution
At selecting internal count source:
Stop
At selecting external count source:
Operating (only Timer X)
Stop
Stop
At selecting internal synchronous
clock: Stop
At selecting external synchronous
clock: Operating
Stop (suspend state)
State
Stop
State retained
State retained (Timer 1 and
prescaler 12 excepted)
State retained
• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register
Parameter
Watchdog timer
RAM
SFR
CPU register
(2) Stop mode release
Stop mode is released by reset input or interrupt occurrence. The interrupt sources which can be
used for return from stop mode are shown below.
• INT0
• INT1
• CNTR0
• Timer (Timer X) when using external clock
• Serial I/O2 when using external clock
• Key-on wakeup
• USB function (resume, reset)
When the above interrupt sources are used for return from stop mode, execute the STP instruction
after the following are set in order to enable the using interrupts.
➀ Clear the timer 1 interrupt enable bit to “0” (ICON1, bit 4)
➁ Clear the timer 2 interrupt enable bit to “0” (ICON1, bit 5)
➂ Clear the timer 1 interrupt request bit to “0” (IREQ1, bit 4)
➃ Clear the timer 2 interrupt request bit to “0” (IREQ1, bit 5)
➄ Clear the interupt request bit of the interrupt using for return to “0”
➅ Set the interupt enable bit of the interrupt using for return to “1”
➆ Clear the interrupt disable flag (I) to “0”
FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 50 of 55
REJ09B0178-0300
Wait mode
System enters the wait mode by executing the WIT instruction. In the wait mode, the oscillation is operating,
but the internal clock φ is stopped. Accordlingly, CPU is stopped, but the peripheral devices are operating.
(1) Wait mode state
Table 12 shows the state at wait mode.
Table 12 Wait mode state
Parameter
Oscillation
CPU
I/O port
Timer
UART
A/D conversion
Serial I/O2
USB
State
Stop
Stop
State at WIT instruction execution
retained
At selecting internal count source:
Operating
At selecting external count source:
Operating
Operating
Operating (Conversion is
continued if the WIT instruction
is executed during conversion)
At selecting internal synchronous
clock: Operating
At selecting external synchronous
clock: Operating
Operating
State
Operating
State retained
State retained (Timer 1, timer 2 and
prescaler 12 excepted)
State retained
• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register
Parameter
Watchdog timer
RAM
SFR
CPU register
(2) Wait mode release
Wait mode is released by reset input or interrupt occurrence. In the wait mode, since the oscillation
is continued, the instruction is executed after the system is released from the wait mode. The
interrupt sources which can be used for return from wait mode are shown below.
• INT0
• INT1
• CNTR0
• Timer
• Serial I/O2
• A/D conversion
• Key-on wakeup
• USB function
• UART
When the above interrupt sources are used for return from wait mode, execute the WIT instruction
after the following are set in order to enable the using interrupts.
➀ Clear the interupt request bit of the interrupt using for return to “0”
➁ Set the interupt enable bit of the interrupt using for return to “1”
➂ Clear the interrupt disable flag (I) to “0”
FUNCTIONAL DESCRIPTION SUPPLEMENT
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 51 of 55
REJ09B0178-0300
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
The 7534 Group has three package types, and each of the number
of I/O ports are different. Accordingly, when the pins which have the
function except a port function are eliminated, be careful that the
functions are also eliminated.
Table 14 Differences among 32-pin, 36-pin and 42-pin
I/O port
Port P1
Port P2
Port P3
Port P4
42-pin SDIP
P10–P16 (7-bit structure)
P20–P27 (8-bit structure)
(A/D converter 8-channel)
P30–P37 (8-bit structure)
(INT0, INT1 available)
P40, P41 (2-bit structure)
36-pin SSOP
P10–P14 (5-bit structure)
P20–P27 (8-bit structure)
(A/D converter 8-channel)
P30–P35, P37 (7-bit structure)
(INT0 available)
No port
32-pin LQFP
P10–P14 (5-bit structure)
P20–P25 (6-bit structure)
(A/D converter 6-channel)
P30–P34 (5-bit structure)
(INT function not available)
No port
DESCRIPTION OF IMPROVED USB FUNCTION
FOR 7534 GROUP
Table 13 Description of improved USB function for 7534 Group
No.
1
2
3
4
5
Parameter
Response at Control transfer
D+/D- transceiver circuit
Power dissipation at Suspend
STALL in Status stage
6-bit decode of SYNC field
7532/7536 Group
Not deal with the host which performs the Control
transfer in parallel to plural device.
USB function can be used only at the condition of
CL = 150 pF to 350 pF.
Rating is Max. 300 µA not including the output cur-
rent of USBVREFOUT.
ACK is returned once to OUT (DATA0) to be valid
in Status stage.
SYNC is detected only when 8-bit full code (8016)
is complete.
7534 Group
Connectable to the host which performs the Con-
trol transfer in parallel to plural device.
Deal with the following Low-Speed USB2.0 speci-
fication.
CL = 200 pF to 450 pF,
Trise and Tfall: 75 ns to 300 ns,
Tr/Tf: 80 % to 125 %,
Cross over Voltage: 1.3 V to 2.0 V.
Rating is Max. 300 µA including the output current
of USBVREFOUT, by low-power dissipation of D+/
D- input circuit and 3.3 V-regulator.
STALL is set automaticcally by hardware when
OUT (DATA0) is received in Status stage.
SYNC is detected only the low-order 6 bits even if
the high-order 2 bits are corrupted.
DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP/
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 52 of 55
REJ09B0178-0300
Table 15 Differences among 32-pin, 36-pin and 42-pin (SFR)
42-pin SDIP
Bit 7 not available
All bits available
All bits available
Bits 2 to 7 not available
Bit 6 definition:
“P35, P36 pull-up control”
Bit 7 definition:
“P37 pull-up control”
Bit 0 definition:
“P37/INT0 input level selection”
Bit 1 definition:
“P36/INT1 input level selection”
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
Bit 0 definition
“INT0 interrupt edge selection”
Bit 1 definition
“INT1 interrupt edge selection”
Bit 4 definition
“Serial I/O1, INT1 interrupt selection”
Bit 1 definition
“UART transmission, USB (except IN),
INT1”
Bit 2 definition
“INT0”
Bit 1 definition
“UART transmission, USB (except IN),
INT1”
Bit 2 definition
“INT0”
36-pin SSOP
Bits 5 to 7 not available
All bits available
Bit 6 not available
All bits not available
Bit 6 definition:
“P35 pull-up control”
Bit 7 definition:
“P37 pull-up control”
Bit 0 definition:
“P37/INT0 input level selection”
Bit 1 not available
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
Bit 0 definition
“INT0 interrupt edge selection”
Bits 1 and 4 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 definition
“INT0”
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 definition
“INT0”
32-pin LQFP
Bits 5 to 7 not available
Bits 6 and 7 not available
Bits 5 to 7 not available
All bits not available
Bits 6 and 7 not available
Bits 0 and 1 not available
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 101”
Bits 0, 1 and 4 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 not available
Additionally, there are differences of SFR usage and functional defi-
nitions.
Register (Address)
Port P1/Direction
(0216/0316)
Port P2/Direction
(0416/0516)
Port P3/Direction
(0616/0716)
Port P4/Direction
(0816/0916)
Pull-up control
(1616)
Port P1P3 control
(1716)
A/DControl
(3416)
Interrupt edge
selection
(3A16)
Interrupt request
(3C16)
Interrupt control
(3E16)
DIFFERENCES AMONG 32-PIN, 36-PIN AND 42-PIN
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 53 of 55
REJ09B0178-0300
Fig. 56 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
Outline PRSP0036GA-A
1
0
1
2
3
4
6
7
8
9
1
1
1
2
1
4
1
5
1
6
5
1
3
1
7
1
8
3
6
3
5
3
4
3
3
31
3
0
2
6
2
5
2
4
2
3
2
2
21
2
0
1
9
3
2
2
7
2
9
2
8
P
00
CNVSS
XOUT
XIN
VSS
P01
P
02
P
03
P04
P
30(
L
E
D0)
V
c
c
VR
E
F
P
05
P
10/
RXD
/
D
-
P
26/
A
N6
P27/AN7
P
11/
TXD
/
D
+
P
12/
SC
L
K
P13/SDAT
A
P
23/
A
N3
P
22/
A
N2
P
21/
A
N1
P20/AN0
P
31(
L
E
D1)
P
37/
I
N
T0
P24/AN4
P25/AN5
P06
P
07
USBVREFOUT
RESET
M
3
7
5
3
4
M
4
-
X
X
X
F
P
M
3
7
5
3
4
E
8
F
P
P
14/
C
N
T
R0
P35(LED5)
P
34(
L
E
D4)
P
33(
L
E
D3)
P
32(
L
E
D2)
1.5kΩ
R
e
a
s
o
n
o
f
➀
i
s
t
o
r
e
d
u
c
e
t
h
e
e
f
f
e
c
t
b
y
s
w
i
t
c
i
n
g
n
o
i
s
e
o
f
m
i
c
r
o
c
o
m
p
u
t
e
r
t
o
t
h
e
a
n
a
l
o
g
c
i
r
c
u
i
t
g
e
n
e
r
a
t
i
n
g
U
S
B
VR
E
F
O
U
T
o
u
t
p
u
t
.
U
s
e
t
h
e
b
i
g
g
e
r
c
a
p
a
c
i
t
o
r
a
n
d
c
o
n
n
e
c
t
t
o
d
e
v
i
c
e
a
t
t
h
e
s
h
o
r
t
e
s
t
d
i
s
t
a
n
c
e
.
R
e
a
s
o
n
o
f
➁
i
s
t
o
p
r
e
v
e
n
t
t
h
e
i
n
s
t
a
b
i
l
i
t
y
o
f
t
h
e
U
S
B
VR
E
F
O
U
T
o
u
t
p
u
t
d
u
e
t
o
e
x
t
e
r
n
a
l
n
o
i
s
e
.
Connect a capacitor to a device as
clo s e as pos s ible. For the capacitor ,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
➁
C
o
n
n
e
c
t
a
b
y
p
a
s
s
c
a
p
a
c
i
t
o
r
t
o
a
d
e
v
i
c
e
a
s
c
l
o
s
e
a
s
p
o
s
s
i
b
l
e
.
F
o
r
t
h
e
c
a
p
a
c
i
t
o
r
,
a
c
e
r
a
m
i
c
c
a
p
a
c
i
t
o
r
o
r
a
n
e
l
e
c
t
r
o
l
y
t
i
c
c
a
p
a
c
i
t
o
r
o
f
1
.
0
µF
i
s
r
e
c
o
m
m
e
n
d
e
d
.
➀
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
HARDWARE
7534 Group
Rev.3.00 Oct 23, 2006 page 54 of 55
REJ09B0178-0300
Fig. 57 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP, M37534E4GP
O
u
t
l
i
n
e
P
L
Q
P
0
0
3
2
G
B
-
A
P
0
7
P
10/
RXD
/
D
-
P
11/
TXD
/
D
+
P
12/
SC
L
K
P
13/
SD
A
T
A
P
14/
C
N
T
R
0
P
20/A
N
0
P
2
1
/A
N1
3
2
3
1
30
2
9
2
8
27
26
25
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
P3
1
(LED
1
)
P3
0
(LED
0
)
V
SS
X
OUT
X
IN
9
10
11
12
13
14
15
16
2
8
7
6
5
3
1
4
V
C
C
C
N
V
S
S
R
E
S
E
T
P
2
2
/
A
N
2
P
0
5
2
0
1
7
1
8
1
9
2
1
2
4
P
0
2
P
0
4
P
0
3
P
0
6
2
3
2
2
P
0
1
P
0
0
U
S
B
V
R
E
F
O
U
T
M
3
7
5
3
4
M
4
-
X
X
X
G
P
M
3
7
5
3
4
E
4
G
P
P
2
3
/
A
N
3
P
2
4
/
A
N
4
P
2
5
/
A
N
5
V
R
E
F
1
.
5
kΩ
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit gen er ating US B V REFOUT output. Use the bigger capacitor and
con nec t to device at the shortest dis tance.
Reason of ➁ is to prev ent the instab ility of the USBVREFOUT output due to
exter nal noise.
➁
➀
Connect a capacitor to a device as
clo s e as pos s ible. For the ca pac itor ,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
Connect a bypass capac ito r to a de v ic e
as clo s e as pos s ible. For the ca pac ito r,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is rec ommended.
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
7534 Group
HARDWARE
Rev.3.00 Oct 23, 2006 page 55 of 55
REJ09B0178-0300
Fig. 58 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS
O
u
t
l
i
n
e
P
R
D
P
0
0
4
2
B
A
-
A
1
0
1
2
3
4
6
7
8
9
11
1
2
1
4
1
5
1
6
5
1
3
1
7
1
8
3
6
3
5
3
4
3
3
31
3
0
2
6
2
5
2
4
2
3
2
2
3
2
2
7
2
9
2
8
1
9
2
0
21
4
2
41
4
0
3
9
3
7
3
8
P
00
C
N
VS
S
XO
U
T
XI
N
VS
S
P
01
P
02
P
03
P
04
P
30(
L
E
D0)
V
c
c
VR
E
F
P
05
P
12/
SC
L
K
P
25/
A
N5
P
26/
A
N6
P
13/
SD
A
T
A
P
14/
C
N
T
R0
P
22/
A
N2
N
C
P
21/
A
N1
P
20/
A
N0
P
31(
L
E
D1)
P
23/
A
N3
P
24/
A
N4
P
06
P
07
P
37/
I
N
T0
R
E
S
E
T
M
3
7
5
3
4
E
8
S
P
M
3
7
5
3
4
M
4
-
X
X
X
S
P
M
3
7
5
3
4
R
S
S
P
35(
L
E
D5)
P
34(
L
E
D4)
P
33(
L
E
D3)
P
32(
L
E
D2)
U
S
B
VR
E
F
O
U
T
P
10/
RXD
/
D
-
P
11/
TXD
/
D
+
P
27/
A
N7
1
.
5
kΩ
R
e
a
s
o
n
o
f
➀
i
s
t
o
r
e
d
u
c
e
t
h
e
e
f
f
e
c
t
b
y
s
w
i
t
c
i
n
g
n
o
i
s
e
o
f
m
i
c
r
o
c
o
m
p
u
t
e
r
t
o
t
h
e
a
n
a
l
o
g
c
i
r
c
u
i
t
g
e
n
e
r
a
t
i
n
g
U
S
B
VR
E
F
O
U
T
o
u
t
p
u
t
.
U
s
e
t
h
e
b
i
g
g
e
r
c
a
p
a
c
i
t
o
r
a
n
d
c
o
n
n
e
c
t
t
o
d
e
v
i
c
e
a
t
t
h
e
s
h
o
r
t
e
s
t
d
i
s
t
a
n
c
e
.
R
e
a
s
o
n
o
f
➁
i
s
t
o
p
r
e
v
e
n
t
t
h
e
i
n
s
t
a
b
i
l
i
t
y
o
f
t
h
e
U
S
B
VR
E
F
O
U
T
o
u
t
p
u
t
d
u
e
t
o
e
x
t
e
r
n
a
l
n
o
i
s
e
.
➁
➀
P
16
P
15
P
40
P
41P
36(
L
E
D6)
/
I
N
T1
C
o
n
n
e
c
t
a
c
a
p
a
c
i
t
o
r
t
o
a
d
e
v
i
c
e
a
s
c
l
o
s
e
a
s
p
o
s
s
i
b
l
e
.
F
o
r
t
h
e
c
a
p
a
c
i
t
o
r
,
a
c
e
r
a
m
i
c
c
a
p
a
c
i
t
o
r
o
r
a
n
e
l
e
c
t
r
o
l
y
t
i
c
c
a
p
a
c
i
t
o
r
o
f
0
.
2
2
µF
i
s
r
e
c
o
m
m
e
n
d
e
d
.
C
o
n
n
e
c
t
a
b
y
p
a
s
s
c
a
p
a
c
i
t
o
r
t
o
a
d
e
v
i
c
e
a
s
c
l
o
s
e
a
s
p
o
s
s
i
b
l
e
.
F
o
r
t
h
e
c
a
p
a
c
i
t
o
r
,
a
c
e
r
a
m
i
c
c
a
p
a
c
i
t
o
r
o
r
a
n
e
l
e
c
t
r
o
l
y
t
i
c
c
a
p
a
c
i
t
o
r
o
f
1
.
0
µF
i
s
r
e
c
o
m
m
e
n
d
e
d
.
DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Timer
2.3 Serial I/O
2.4 USB
2.5 A/D converter
2.6 Reset
APPLICATION
7534 Group 2.1 I/O port
Rev.3.00 Oct 23, 2006 page 2 of 78
REJ09B0178-0300
2.1 I/O port
This paragraph explains the registers setting method and the notes relevant to the I/O ports.
2.1.1 Memory map
Fig. 2.1.1 Memory map of registers relevant to I/O port
2.1.2 Relevant registers
Fig. 2.1.2 Structure of Port Pi (i = 0 to 4)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
0008
16
0009
16
Port P4 (P4)
Port P4 direction register (P4D)
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
B Function At reset RW
0
1
2
3
4
5
6
7
Name
Port Pi
0
Port Pi
1
Port Pi
2
Port Pi
3
Port Pi
4
Port Pi
5
Port Pi
6
Port Pi
7
In output mode
Write
Read
●
Port latch
In input mode
Write : Port latch
Read : Value of pins
●
Port Pi (Pi) (i = 0 to 4) [Address : 00
16
, 02
16
, 04
16
, 06
16
, 08
16
]
?
?
?
?
?
?
?
?
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1
7
, P4
2
–P4
7
• 36-pin version: Ports P1
5
–P1
7
, P3
6
, P4
0
–P4
7
• 32-pin version: Ports P1
5
–P1
7
, P2
6
, P2
7
, P3
5
–P3
7
, P4
0
–P4
7
7534 Group
APPLICATION
2.1 I/O port
Rev.3.00 Oct 23, 2006 page 3 of 78
REJ09B0178-0300
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 4)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
Port Pi
direction register 0
0
0
0
0
0
0
0
Port Pi direction register (PiD) (i = 0 to 4) [Address : 01
16
, 03
16
, 05
16
, 07
16
, 09
16
]
0 : Port Pi
0
input mode
1 : Port Pi
0
output mode
0 : Port Pi
1
input mode
1 : Port Pi
1
output mode
0 : Port Pi
2
input mode
1 : Port Pi
2
output mode
0 : Port Pi
3
input mode
1 : Port Pi
3
output mode
0 : Port Pi
4
input mode
1 : Port Pi
4
output mode
0 : Port Pi
5
input mode
1 : Port Pi
5
output mode
0 : Port Pi
6
input mode
1 : Port Pi
6
output mode
0 : Port Pi
7
input mode
1 : Port Pi
7
output mode
✕
✕
✕
✕
✕
✕
✕
✕
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1
7
, P4
2
–P4
7
• 36-pin version: Ports P1
5
–P1
7
, P3
6
, P4
0
–P4
7
• 32-pin version: Ports P1
5
–P1
7
, P2
6
, P2
7
, P3
5
–P3
7
, P4
0
–P4
7
Fig. 2.1.4 Structure of Pull-up control register
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
P0
0
pull-up control bit
1
1
1
1
1
1
1
1
Pull-up control register (PULL) [Address : 16
16
]
0 : Pull-up Off
1 : Pull-up On
Notes 1: Pins set to output are disconnected from the pull-up control.
2: • 36-pin version: P36 is not existed.
• 32-pin version: Not used.
3: 32-pin version: Not used.
P0
1
pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P0
2
, P0
3
pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P0
4
– P0
7
pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P3
0
– P3
3
pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P3
4
pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P3
5
, P3
6
pull-up control bit
(Note 2)0 : Pull-up Off
1 : Pull-up On
P3
7
pull-up control bit
(Note 3)0 : Pull-up Off
1 : Pull-up On
APPLICATION
7534 Group 2.1 I/O port
Rev.3.00 Oct 23, 2006 page 4 of 78
REJ09B0178-0300
Fig. 2.1.5 Structure of P1P3 control register
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name
P3
7
/INT
0
input level selection
bit (Note 1)0
0
0
0
0
0
0
0
Port P1P3 control register (P1P3C) [Address : 17
16
]
0 : CMOS level
1 : TTL level
P3
6
/INT
1
input level selection
bit (Note 2)
0 : CMOS level
1 : TTL level
P1
0
, P1
2
,P1
3
input level
selection bit 0 : CMOS level
1 : TTL level
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
✕
✕
✕
Notes 1: For the 32-pin version, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
2: For the 32-pin and 36-pin versions, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
Fig. 2.1.6 Structure of Interrupt edge selection register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
INT0 interrupt edge
selection bit (Note 1)
INT1 interrupt edge
selection bit (Note 2)
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
Serial I/O1 or INT1 interrupt
selection bit
Timer X or key-on wake up
interrupt selection bit
Timer 2 or serial I/O2 interrupt
selection bit
CNTR0 or AD converter
interrupt selection bit
0 : Serial I/O1
1 : INT1
0 : Timer X
1 : Key-on wake up
0 : Timer 2
1 : Serial I/O2
0 : CNTR0
1 : AD converter
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
7534 Group
APPLICATION
2.1 I/O port
Rev.3.00 Oct 23, 2006 page 5 of 78
REJ09B0178-0300
Fig. 2.1.7 Structure of Interrupt request register 1
CNTR
0
or AD converter
interrupt request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C
16
]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
UART receive/USBIN token
interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 or serial I/O2 interrupt
request bit
✽: These bits can be cleared to “0” by program, but cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
INT
0
interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
✽
✽
✽
✽
✽
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt
request bit (Note 1)
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16]
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”. ✕
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt
enable bit
CNTR0 or AD converter
interrupt enable bit
INT0 interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT1 interrupt enable
bit (Note 1)
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
Fig. 2.1.8 Structure of Interrupt control register 1
APPLICATION
7534 Group 2.1 I/O port
Rev.3.00 Oct 23, 2006 page 6 of 78
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2.1.3 Application example of key-on wake up
Outline: The built-in pull-up resistor is used.
Fig. 2.1.9 Relevant registers setting
Fig. 2.1.10 Application circuit example
Interrupt edge selection register (address 3A
16
)
INTEDGE 1
IREQ1
Pull-up control register (address 16
16
)
PULL 11
P0
0
– P0
3
pull-up on
1
b0
b7
b0
b7
b0
b7
ICON1 b0
b7
1
Timer X or key-on wake up interrupt selection
: Key-on wake up selected
Interrupt control register 1 (address 3E
16
)
Timer X or key-on wake up interrupt: Enabled
Interrupt request register 1 (address 3C
16
)
Timer X or key-on wake up interrupt request bit
0
7534 group
P0i (i: 0 – 3)
Key ON
P03
P02
P01
P00
7534 Group
APPLICATION
2.1 I/O port
Rev.3.00 Oct 23, 2006 page 7 of 78
REJ09B0178-0300
Fig. 2.1.11 Control procedure
2.1.4 Handling of unused pins
Table 2.1.1 Handling of unused pins
Pins/Ports name
P0, P1, P2, P3, P4
VREF
XOUT
Handling
•Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to
10 kΩ.
•Set to the output mode and open at “L” or “H” level.
•Connect to Vss (GND).
•Open, only when using an external clock
RESET
XXXXX1112
...
PULL (address 1616)•P03 – P00 pull-up On
1
0
1
WIT
Key ON
...
RTI
.......
...
Initialization
Power down procedure
...
INTEDGE(address 3A16), bit5
IREQ1 (address 3C16), bit3
ICON1 (address 3E16), bit3
Process continuation
Interrupt process of
Key-on wake up
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
•Key-on wake up selected
•Clear the key-on wake up interrupt request bit to “0”
•Key-on wake up interrupt enabled
APPLICATION
7534 Group 2.1 I/O port
Rev.3.00 Oct 23, 2006 page 8 of 78
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2.1.5 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
•When setting as an output port : Prevent current from flowing out to external.
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
*2 bit managing instructions : SEB, and CLB instructions
7534 Group
APPLICATION
2.1 I/O port
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2.1.6 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. As for pins
whose potential affects to operation modes such as pins CNVSS, INT or others, select the VCC pin
or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 10 of 78
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2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
Fig. 2.2.1 Memory map of registers relevant to timers
2.2.2 Relevant registers
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X
002816
002916
002A16
002B16
002C16
002D16
002E16
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer X mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Timer count source set register (TCSS)
003C16
003E16
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
003A16 Interrupt edge selection register (INTEDGE)
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
Prescaler 12 (PRE12) [Address : 28 16]
Prescaler X (PREX) [Address : 2C 16]
•Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres-
ponding prescaler is read out.
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 11 of 78
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Fig. 2.2.3 Structure of Timer 1
Fig. 2.2.4 Structure of Timer 2
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
Timer 1 (T1) [Address : 29
16
]
•Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
latch at the same time.
•When this register is read out, the timer 1’s count value is read
out.
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
Timer 2 (T2) [Address : 2A16]
•Set a count value of timer 2.
•The value set in this register is written to both timer 2 and timer 2
latch at the same time.
•When this register is read out, the timer 2’s count value is read
out.
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 12 of 78
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Fig. 2.2.5 Structure of Timer X
Timer X
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
Timer X (TX) [Address : 2D16]
•Set a count value of timer X.
•The value set in this register is written to both timer X and timer X
latch at the same time.
•When this register is read out, the timer X’s count value is read
out.
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 13 of 78
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Fig. 2.2.6 Structure of Timer X mode register
Timer X operation modes
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
CNTR0 active edge switch bit (bit 2 of address 2B16) contents
“0” CNTR0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR0 interrupt request occurrence: Rising edge
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
CNTR0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR0 interrupt request occurrence: Rising edge
“0” Timer X: Rising edge count
CNTR0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR0 interrupt request occurrence: Rising edge
“0” Timer X: “H” level width measurement
CNTR0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR0 interrupt request occurrence: Rising edge
Table 2.2.1 CNTR0 active edge switch bit function
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
2
3
4
5
6
7
Name
0
0
0
0
Timer X mode register (TM) [Address : 2B 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
✕
Timer X mode register
0
0
0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement
mode
b1 b0
10
Timer X operating mode bits
CNTR0 active edge switch bit The function depends on the
operating mode.
(Refer to Table 2.2.1)
Timer X count stop bit 0 : Count start
1 : Count stop ✕
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 14 of 78
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Fig. 2.2.7 Structure of Timer count source set register
Fig. 2.2.8 Structure of Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
Timer count source set register (TCSS) [Address : 2E 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
✕
✕
✕
Timer count source set register
Timer X count source
selection bit (Note)0 : f(XIN) / 16
1 : f(XIN) / 2
0
0
0
✕
✕
✕
✕
Note: To switch the timer X count source selection bit, stop the timer X count
operation before do that.
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
INT0 interrupt edge
selection bit (Note 1)
INT1 interrupt edge
selection bit (Note 2)
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
Serial I/O1 or INT1 interrupt
selection bit
Timer X or key-on wake up
interrupt selection bit
Timer 2 or serial I/O2 interrupt
selection bit
CNTR0 or AD converter
interrupt selection bit
0 : Serial I/O1
1 : INT1
0 : Timer X
1 : Key-on wake up
0 : Timer 2
1 : Serial I/O2
0 : CNTR0
1 : AD converter
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 15 of 78
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Fig. 2.2.9 Structure of Interrupt request register 1
Fig. 2.2.10 Structure of Interrupt control register 1
CNTR0 or AD converter
interrupt request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C
16]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
UART receive/USBIN token
interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 or serial I/O2 interrupt
request bit
✽: These bits can be cleared to “0” by program, but cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
INT0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
✽
✽
✽
✽
✽
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT1 interrupt
request bit (Note 1)
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”. ✕
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt
enable bit
CNTR
0
or AD converter
interrupt enable bit
INT
0
interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt enable
bit (Note 1)
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 16 of 78
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2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 100 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X)
The output level of the CNTR0 pin is inverted each time the timer underflows (in the pulse output
mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote-control carrier waveforms
[Function 4] Count of External pulses (Timer X)
External pulses input to the CNTR0 pin are counted as the timer count source (in the event counter
mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X)
The “H” or “L” level width of external pulses input to CNTR0 pin is measured (in the pulse width
measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse✽: Pulse used for detecting the motor speed to control the motor speed.
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 17 of 78
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(2) Timer application example 1: Clock function (measurement of 100 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 100 ms intervals.
Specifications: •The clock f(XIN) = 6.00 MHz is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 100 ms intervals.
Figure 2.2.11 shows the timers connection and setting of division ratios; Figure 2.2.12 shows the
relevant registers setting; Figure 2.2.13 shows the control procedure.
Fig. 2.2.11 Timers connection and setting of division ratios
f(XIN) = 6.00 MHz
100 ms
1/16 1/147 1/256 1/10
1 second
Dividing by 4 with software
Timer X count source
selection bit Prescaler X Timer X Timer X interrupt
request bit
0 or 1
0 : No interrupt request issued
1 : Interrupt request issued
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 18 of 78
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Fig. 2.2.12 Relevant registers setting
ICON1
Timer X interrupt: Enabled
1
IREQ1
TM 001
PREX 146
TX 255
b0b7
b0b7
b0
b7
b0b7
b0
b7
INTEDGE 0
b0
b7
TCSS 0
Timer X count source : f(X
IN
)/16
b0
b7
0
Timer count source set register (address 2E
16
)
Timer X or key-on wake up interrupt selection
: Timer X
Interrupt edge selection register (address 3A
16
)
Timer X mode register (address 2B
16
)
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2C
16
)
Timer X (address 2D
16
)Set “division ratio – 1”
Interrupt control register 1 (address 3E
16
)
Interrupt request register 1 (address 3C
16
)
Timer X interrupt request
(becomes “1” at 100 ms intervals)
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 19 of 78
REJ09B0178-0300
Fig. 2.2.13 Control procedure
RESET
Initialization
SEI
INTEDGE
TM
IREQ1
ICON1
TCSS
PREX
TX
TM
CLI
0
0
1
..... ..... .....
0
147 – 1
256 – 1
Main processing
TM
PREX
TX
IREQ1
TM
.....
1
147– 1
256 – 1
0
0
Clock stop ?
N
Y
RTI
(address 2B
16
), bit3
(address 2C
16
)
(address 2D
16
)
(address 3C
16
), bit3
(address 2B
16
), bit3
(address 3A
16
), bit5
(address 2B
16
)
(address 3C
16
), bit3
(address 3E
16
), bit3
CLT (Note 2)
CLD (Note 3)
Push registers to stack
(address 2E
16
), bit0
(address 2C
16
)
(address 2D
16
)
(address 2B
16
), bit3 0
.....
<Procedure for completion of clock set>
(Note 1)
Timer X interrupt process routine
Clock count up (1/10 second to year)
Pop registers
00001000
2
•All interrupts disabled
•Timer X interrupt selected
•Timer X operating mode : Timer mode
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
•Timer X count source : f(X
IN
/16)
•Set “division ratio – 1” to Prescaler X and Timer X
•Timer X count start
•Interrupts enabled
•Reset Timer to restart count from 0 second after completion
of clock set
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Judge whether clock stops
•Clock count up
•Pop registers pushed to stack
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 20 of 78
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(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 6.00 MHz into about 2 kHz
(1995 Hz), is output from the P14/CNTR0 pin.
•The level of the P14/CNTR0 pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.2.14 shows a peripheral circuit example, and Figure 2.2.15 shows the timers connection and
setting of division ratios. Figures 2.2.16 shows the relevant registers setting, and Figure 2.2.17
shows the control procedure.
Fig. 2.2.14 Peripheral circuit example
Fig. 2.2.15 Timers connection and setting of division ratios
7534 Group
P14/CNTR0
PiPiPi.....
250 µs
CNTR
0
output
The “H” level is output while a piezoelectric buzzer output stops.
250 µs
Set a division ratio so that the
underflow output period of the timer X
can be 250 µs.
1/16 1/94 1/2 CNTR
0
1f(X
IN
) = 6.00 MHz
Timer X count source
selection bit Prescaler X Timer X Fixed
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 21 of 78
REJ09B0178-0300
Fig. 2.2.16 Relevant registers setting
TM
TX 93
1001
PREX 0
b0b7
b0b7
b0b7
TCSS 0
b0
b7
ICON1 0
b0
b7
Timer X interrupt: Disabled
Timer X count source : f(X
IN
)/16
Timer count source set register (address 2E 16)
Timer X mode register (address 2B16)
Timer X operating mode: Pulse output mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2C16)
Timer X (address 2D16)
Set “division ratio – 1”
Interrupt control register 1 (address 3E 16)
CNTR
0
active edge switch: Output starting at “H” level
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 22 of 78
REJ09B0178-0300
Fig. 2.2.17 Control procedure
RESET
P1
P1D
TCSS
ICON1
TM
TX
PREX
1
..... ..... .....
0
0
000010012
94 – 1
1 – 1
.....
Output unit
TM (address 2B16), bit3 0
(address 0216), bit4
(address 0316)
(address 2E16), bit0
(address 3E16), bit3
(address 2B16)
(address 2D16)
(address 2C16)
TM (address 2B16), bit3 1
TX (address 2D16) 94 – 1
Initialization ● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
XXX1XXXX2
Main processing
Piezoelectric buzzer request ? Yes
Start piezoelectric buzzer output
Stop piezoelectric buzzer output
No
•Timer X count source : f(XIN)/16
•Timer X interrupt disabled
•Stop CNTR0 output; Stop piezoelectric buzzer output
•Set “division ratio – 1” to Timer X and Prescaler X
•Process piezoelectric buzzer request, generated during
main processing, in output unit
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 23 of 78
REJ09B0178-0300
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P14/CNTR0 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P14/CNTR0 pin and counted by the timer X.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 – 215 = 255 (initial value of counter) – 28 to 40 (the number of valid count)
Figure 2.2.18 shows the judgment method of valid/invalid of input pulses; Figure 2.2.19 shows the
relevant registers setting; Figure 2.2.20 shows the control procedure.
Fig. 2.2.18 Judgment method of valid/invalid of input pulses
Input pulse
2 ms
71.4 µs= 28 counts
71.4 µs or more
(14 kHz or less) 71.4 µs
(14 kHz) 50 µs
(20 kHz) 50 µs or less
(20 kHz or more)
Invalid Valid Invalid
2 ms
50 µs= 40 counts
• • • • • • • • • • • • • • •
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 24 of 78
REJ09B0178-0300
Fig. 2.2.19 Relevant registers setting
TM
PRE12 93
T1
101 1
PREX
TX
7
0
255
ICON1 0
IREQ1 0
b0b7
b0b7
b0b7
b0b7
b0b7
b0b7
b0b7
INTEDGE 0
b0
b7
1
Timer X interrupt: Disabled
Timer X mode register (address 2B
16
)
Timer X operating mode: Event counter mode
Timer X count: Stop
Clear to “0” when starting count
Prescaler 12 (address 28
16
)
Timer X (address 2D
16
)
Set “division ratio – 1”
Interrupt control register 1 (address 3E
16
)
CNTR
0
active edge switch: Falling edge count
Timer X or key-on wake up interrupt selection
: Timer X
Interrupt edge selection register (address 3A
16
)
Prescaler X (address 2C
16
)
Timer 1 (address 29
16
)
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C
16
)
Judgment of Timer X interrupt
request bit
( “1” of this bit when reading the
count value indicates the 256 or
more pulses input in the condition
of Timer X = 255)
Set 255 just before counting pulses
(After a certain time has passed, the number of input
pulses is decreased from this value.)
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 25 of 78
REJ09B0178-0300
Fig. 2.2.20 Control procedure
RESET
SEI
INTEDGE
TM
PRE12
T1
PREX
TX
ICON1
TM
CLI
0
..... .....
0
IREQ1(address 3C
16
), bit3 ?
0
1
RTI
.....
TX (address 2D
16
)
(A)
214 < (A) < 228
0
Fpulse 1
Fpulse
TX (address 2D
16
)
IREQ1 (address 3C
16
), bit3 256 – 1
0
(address 3A
16
), bit5
(address 2B
16
)
(address 28
16
)
(address 29
16
)
(address 2C
16
)
(address 2D
16
)
(address 3E
16
)
(address 2B
16
), bit3
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
•All interrupts disabled
•Timer X interrupt selected
•Timer X operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR
0
pin.)
•Set division ratio so that Timer 1 interrupt will occur at
2 ms intervals.
•Timer X count start
•Interrupts enabled
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Pop registers pushed to stack
•Initialize the counter value
•Clear Timer X interrupt request bit
Initialization
00001110
2
94 – 1
8 – 1
1 – 1
256 – 1
0XX10XXX
2
•Timer 1 interrupt enabled
•Timer X interrupt disabled
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
•Process as out of range when the count value is 256 or more
•Read the count value
•Store the count value into Accumulator (A)
In range
Out of range
•Compare the read value with
reference value
•Store the comparison result to
flag Fpulse
Process judgment result
Pop registers
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 26 of 78
REJ09B0178-0300
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P14/CNTR0 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the CNTR0 interrupt.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P14/CNTR0 pin.
<Example>
When the clock frequency is 6.00 MHz, the count source is 2.7 µs, which is obtained by dividing
the clock frequency by 16. Measurement can be made up to 174 ms in the range of FFFF16 to
000016.
Figure 2.2.21 shows the timers connection and setting of division ratio; Figure 2.2.22 shows the
relevant registers setting; Figure 2.2.23 shows the control procedure.
Fig. 2.2.21 Timers connection and setting of division ratios
174 ms
1/16 1/256 1/256
f(XIN) = 6.00 MHz
Timer X count source
selection bit Prescaler X Timer X Timer X interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 or 1
7534 Group
APPLICATION
2.2 Timer
Rev.3.00 Oct 23, 2006 page 27 of 78
REJ09B0178-0300
Fig. 2.2.22 Relevant registers setting
TM
PREX 255
TX
011 1
255
ICON1
IREQ1
1
0
b0b7
b0b7
b0b7
b0b7
b0b7
INTEDGE 0
b0
b7
0
1
0
Timer X interrupt: Enabled
Timer X mode register (address 2B
16
)
Timer X operating mode: Pulse width measurement mode
Timer X count: Stop
Clear to “0” when starting count
Prescaler X (address 2C
16
)
Timer X (address 2D
16
)
Set “division ratio – 1”
Interrupt control register 1 (address 3E
16
)
CNTR
0
active edge switch: “H” level width measurement
Timer X or key-on wake up interrupt selection
: Timer X
Interrupt edge selection register (address 3A
16
)
CNTR
0
interrupt: Enabled
Interrupt request register 1 (address 3C
16
)
CNTR
0
or AD converter interrupt source selection
: CNTR
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
CNTR
0
interrupt request
APPLICATION
7534 Group 2.2 Timer
Rev.3.00 Oct 23, 2006 page 28 of 78
REJ09B0178-0300
Fig. 2.2.23 Control procedure
RESET
SEI
INTEDGE
TM
PREX
TX
IREQ1
ICON1
TM
CLI
0
0
..... .....
0
.....
RTI
RTI
(address 3A
16
), bit5
, bit7
(address 2B
16
)
(address 2C
16
)
(address 2D
16
)
(address 3C
16
), bit3
, bit6
(address 3E
16
), bit3
, bit6
PREX
Inverted (A)
(A)
Low-order 8-bit result of
pulse width measurement
(A)
High-order 8-bit result of
pulse width measurement
PREX (address 2C
16
)
TX (address 2D
16
)
(address 2B
16
), bit3
256 – 1
256 – 1
0
0
1
1
00001011
2
TX
Inverted (A)
256 – 1
256 – 1
•All interrupts disabled
•Timer X or key-on wake up interrupt selection : Timer X
•CNTR
0
or AD converter interrupt source selection : CNTR
0
•Timer X operating mode : Pulse width measurement mode
(Measure “H” level of pulses input from CNTR
0
pin.)
•Set division ratio so that Timer X interrupt will occur at
174 ms intervals.
•Clear Timer X interrupt request bit
•Clear CNTR
0
interrupt request bit
•Timer X interrupt enabled
•CNTR
0
interrupt enabled
•Timer X count start
•Interrupts enabled
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Pop registers pushed to stack
Pop registers
Initialization
Timer X interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Process errors •Error occurs
CNTR
0
interrupt process routine
•Set division ratio so that Timer X interrupt will occur at
174 ms intervals.
•Read the count value and store it to RAM
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 29 of 78
REJ09B0178-0300
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
Fig. 2.3.1 Memory map of registers relevant to serial I/O
2.3.2 Relevant registers
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Transmit/Receive buffer register (TB/RB) [Address : 1816]
The transmission data is written to or the receive data is read out
from this buffer register.
• At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
001816
001916
001A16
001B16
001C16
003A16
003C16
Transmit/Receive buffer register (TB/RB)
UART status register (UARTSTS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
Interrupt request register 1 (IREQ1)
003E16 Interrupt control register 1 (ICON1)
003016 Serial I/O2 control register (SIO2CON)
003116 Serial I/O2 register (SIO2)
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 30 of 78
REJ09B0178-0300
Fig. 2.3.3 Structure of UART status register
Fig. 2.3.4 Structure of Serial I/O1 control register
UART status register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 1
0
0
0
0
0
0
1
UART status register (UARTSTS) [Address : 19 16]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
✕
✕
✕
✕
✕
✕
✕
✕
Transmit buffer empty flag
(TBE)
0 : (OE) ∪ (PE) ∪ (FE) = 0
1 : (OE) ∪ (PE) ∪ (FE) = 1
Overrun error flag (OE)
0 : Buffer full
1 : Buffer empty
Receive buffer full flag (RBF)
Transmit shift register shift
completion flag (TSC)
Parity error flag (PE)
Framing error flag (FE)
Summing error flag (SE)
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
0 : No error
1 : Framing error
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
1
0
0
0
0
0
0
Serial I/O1 control register (SIO1CON) [Address : 1A 16]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”. ✕
0 : f(X
IN
)
1 : f(X
IN
)/4
BRG count source
selection bit (CSS)
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
Transmit interrupt
source selection bit (TIC)
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O1 enable bit
(SIOE)
Continuous transmit valid bit 0 : Continuous transmit invalid
1 : Continuous transmit valid
0 : Interrupt when transmit buffer
has emptied
1 : Interrupt when transmit shift
operation is completed
0 0 : I/O port
0 1 : Not available
1 0 : UART mode
1 1 : USB mode
b7 b6
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 31 of 78
REJ09B0178-0300
Fig. 2.3.5 Structure of UART control register
Fig. 2.3.6 Structure of Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
1
UART control register (UARTCON) [Address : 1B 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”. ✕
✕
✕
UART control register
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Stop bit length selection
bit (STPS)
Parity selection bit
(PARS)
In output mode
0 : CMOS output
1 : N-channel open-drain
output
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : 1 stop bit
1 : 2 stop bits
0 : Even parity
1 : Odd parity
P1
1
/TxD P-channel
output disable bit
(POFF)
1
1
0
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Baud rate generator (BRG) [Address : 1C 16]
Set a count value of baud rate generator.
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 32 of 78
REJ09B0178-0300
Fig. 2.3.7 Structure of Serial I/O2 control register
Fig. 2.3.8 Structure of Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
Serial I/O2 control register (SIO2CON) [Address : 30 16]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
✕
Serial I/O2 control register
0
0
Note: When using it as a SDATA input, set the port P13 direction register bit to “0”.
0 : LSB first
1 : MSB first
0 0 0 : f(XIN)/8
0 0 1 : f(XIN)/16
0 1 0 : f(XIN)/32
0 1 1 : f(XIN)/64
1 1 0 : f(XIN)/128
1 1 1 : f(XIN)/256
Internal synchronous
clock selection bits
Transfer direction selection bit
b2 b1 b0
SDATA pin selection bit
(Note)0 : I/O port / SDATA input
1 : SDATA output
SCLK pin selection bit 0 : External clock (SCLK is input)
1 : Internal clock (SCLK is output)
Transmit / receive shift
completion flag 0 : shift in progress
1 : shift completed
0
0
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Serial I/O2 register (SIO2) [Address : 31 16]
A shift register for serial transmission and reception.
• At transmitting : Set a transmission data.
• At receiving : A reception data is stored.
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 33 of 78
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Fig. 2.3.9 Structure of Interrupt edge selection register
Fig. 2.3.10 Structure of Interrupt request register 1
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
6
7
Name 0
0
0
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
INT0 interrupt edge
selection bit (Note 1)
INT1 interrupt edge
selection bit (Note 2)
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
Serial I/O1 or INT1 interrupt
selection bit
Timer X or key-on wake up
interrupt selection bit
Timer 2 or serial I/O2 interrupt
selection bit
CNTR0 or AD converter
interrupt selection bit
0 : Serial I/O1
1 : INT1
0 : Timer X
1 : Key-on wake up
0 : Timer 2
1 : Serial I/O2
0 : CNTR0
1 : AD converter
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
05
CNTR
0
or AD converter
interrupt request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
4
5
6
7
Name 0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C
16
]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
UART receive/USBIN token
interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 or serial I/O2 interrupt
request bit
✽: These bits can be cleared to “0” by program, but cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
INT
0
interrupt request bit
(Note 2)0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
✽
✽
✽
✽
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt
request bit (Note 1)
0
✽
3Timer X or key-on wake up
interrupt request bit
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 34 of 78
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Fig. 2.3.11 Structure of Interrupt control register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
4
5
6
7
Name 0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”. ✕
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt
enable bit
CNTR
0
or AD converter
interrupt enable bit
INT
0
interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt enable
bit (Note 1)
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
30
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 35 of 78
REJ09B0178-0300
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.12 shows connection examples with a peripheral IC equipped with the CS pin.
Each case uses the clock synchronous serial I/O mode.
Fig. 2.3.12 Serial I/O connection examples (1)
Port
SCLK
SDATA
CS
CLK
DATA
(1) Only transmission
Peripheral IC
(OSD controller, etc.)
7534 Group
(2) Transmission and Reception
CS
CLK
IN
OUT
7534 Group
(3) Connection of plural IC
CS
CLK
CS
CLK
IN
OUT
Peripheral IC ]
(E2PROM, etc.)
7534 Group Peripheral IC1 ]
IN
OUT
Peripheral IC2 ]
✽ : Use the peripheral IC of which OUT pin has an
N-channel open-drain output structure and which
enters a high-impedance state while receiving
data.
Note: “Port” means an output port controlled by
software.
Port
SCLK
SDATA
Port
SCLK
SDATA
Port
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 36 of 78
REJ09B0178-0300
Fig. 2.3.13 Serial I/O connection examples (2)
(2) Connection with microcomputer
Figure 2.3.13 shows connection examples with another microcomputer.
S
CLK
S
DATA
CLK
IN
OUT
(1) Selecting internal clock
S
CLK
S
DATA
CLK
IN
OUT
7534 Group Microcomputer
T
X
D
R
X
D
R
X
D
T
X
D
(2) Selecting external clock
7534 Group Microcomputer
(3) In UART using serial I/O1
7534 Group Microcomputer
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 37 of 78
REJ09B0178-0300
2.3.4 Serial I/O transfer data format
The clock synchronous or the clock asynchronous (UART) can be selected as the serial I/O.
Figure 2.3.14 shows the serial I/O transfer data format.
Fig. 2.3.14 Serial I/O transfer data format
1ST-8DATA-1SP
ST LSB
Serial I/O1 UART
Clock
synchronous
Serial I/O
1ST-7DATA-1SP
ST LSB
1ST-8DATA-1PAR-1SP
ST LSB
1ST-7DATA-1PAR-1SP
ST LSB
1ST-8DATA-2SP
ST LSB
1ST-7DATA-2SP
ST LSB
1ST-8DATA-1PAR-2SP
ST LSB
1ST-7DATA-1PAR-2SP
ST LSB
MSB SP
MSB SP
MSB PAR SP
MSB PAR SP
MSB 2SP
MSB 2SP
MSB PAR 2SP
MSB PAR 2SP
LSB first ST : Start bit
SP : Stop bit
PAR : Parity bit
Serial I/O2 MSB first
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 38 of 78
REJ09B0178-0300
2.3.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O. Port P00
is used for communication control and outputs the quasi-SRDY signal.
The following explain an example using the serial I/O2. Figure 2.3.15 shows a connection diagram,
and Figure 2.3.16 shows a timing chart.
Fig. 2.3.15 Connection diagram
Specifications :•The Serial I/O2, clock synchronous serial I/O, is used.
•Synchronous clock frequency : 94 kHz; f(XIN) = 6 MHz divided by 64
•Transfer direction : LSB first
•The reception side outputs the quasi-SRDY signal at 2 ms intervals which the timer
generates, and 2-byte data is transferred from the transmission side to the reception
side.
Fig. 2.3.16 Timing chart
Transmission side
P37/INT0
SCLK
SDATA
7534 Group
P00
SCLK
SDATA
Reception side
7534 Group
S
RDY
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
2 ms
S
DATA
S
CLK
. . . .
. . . .
. . . .
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 39 of 78
REJ09B0178-0300
Figures 2.3.17 and 2.3.19 show the registers setting relevant to the serial I/O2 and Figure 2.3.18
shows the transmission data setting of the serial I/O2.
Interrupt control register 1 (address 3E16)
ICON1
Serial I/O2 interrupt : Disabled
0
Interrupt request register 1 (address 3C16)
IREQ1
Serial I/O2 interrupt request
Confirm transmission completion of one-byte unit
using this bit.
“1” : Shift of transmission completed
0
Serial I/O2 control register (address 3016)
SIO2CON
Internal synchronous clock : f(XIN)/64
SDATA pin : SDATA output
LSB first
Internal clock
001111
b0
b7
b0
b7
b0
b7
Interrupt edge selection register (address 3A16)
INTEDGE 1
b0
b7
0
INT0 interrupt edge : Falling edge active
0
INT0 interrupt : Disabled
0
INT0 interrupt request
Timer 2 or serial I/O2 interrupt selection : Serial I/O2
Fig. 2.3.17 Registers setting relevant to transmission side
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 40 of 78
REJ09B0178-0300
Fig. 2.3.18 Transmission data setting of serial I/O2
SIO2
b7 b0
Serial I/O2 register (address 3116)
Set transmission data
After confirming completion of the preceding
transmission, bit 5 of the interrupt request register 1 = “1”;
write data.
Fig. 2.3.19 Registers setting relevant to reception side
Serial I/O2 control register (address 30
16
)
SIO2CON
Internal synchronous clock : f(X
IN
)/64
LSB first
External clock
001010
Transmit/receive shift completion flag
b0
b7
S
DATA
pin : Input port/S
DATA
input
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 41 of 78
REJ09B0178-0300
Fig. 2.3.20 Control procedure of transmission side
Figure 2.3.20 shows a control procedure of transmission side, and Figure 2.3.21 shows a control
procedure of reception side.
RESET
XXXX11XX
2
...
SIO2 (address 31
16
)The first byte of
transmission data
IREQ1 (address 3C
16
), bit2 ?
1
0
P1D
SIO2CON
INTEDGE
ICON1
IREQ1 (address 3C
16
), bit2 0
(address 03
16
)
(address 30
16
)
(address 3A
16
)
(address 3E
16
)
...
IREQ1 (address 3C
16
), bit5 0
IREQ1 (address 3C
16
), bit5 ?
1
0
SIO2 (address 31
16
)
IREQ1 (address 3C
16
), bit5 0
IREQ1 (address 3C
16
), bit5 ?
1
0
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
01001011
2
X1XXXXX0
2
0X0XX0XX
2
The second byte of
transmission data
•Serial I/O2 setting
•INT
0
falling, Serial I/O2 selected
•INT
0
interrupt, serial I/O2 interrupt disabled
•Detection of INT
0
falling edge
•Transmission data write
(One-byte transmission starts.)
•Judgment of completion of one-byte
transmission
•Transmission data write
(One-byte transmission starts.)
•Judgment of completion of one-byte
transmission
Note: When the internal clock is selected and the direction
register of P1
3
/S
DATA
pin is set to the input mode,
the S
DATA
pin is in a high impedance state
after the data transfer is completed.
(Note)
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 42 of 78
REJ09B0178-0300
Fig. 2.3.21 Control procedure of reception side
RESET
000000112
XXXX00XX2
...
SIO2 (address 3116)
2 ms pass ?
Y
N
P0D
P0
SIO2CON
P1D
P0 (address 0016), bit0 0
(address 0116), bit0
(address 0016), bit0
(address 3016)
(address 0316)
...
P0 (address 0016), bit0 1
SIO2CON (address 3016), bit7 ?
1
0
SIO2CON (address 3016), bit7 ?
1
0
Wait for half cycle of clock
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
•Quasi-SRDY signal “H”
•Serial I/O2 setting
•Judgment of completion of one-byte reception
Initialization
1
1
Dummy data
Read out received data from SIO2
SIO2 (address 3116) Dummy data
Wait for half cycle of shift clock
Read out received data from SIO2
•Generation of a 2 ms interval using Timer
•Quasi-SRDY signal output
•Transmit/receive shift completion flag cleared
•Transmit/receive shift completion flag cleared
•Judgment of completion of one-byte reception
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 43 of 78
REJ09B0178-0300
(2) Communication using asynchronous serial I/O, UART (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock asynchronous serial I/O. Port P00
is used for communication control.
Figure 2.3.22 shows a connection diagram, and Figure 2.3.23 shows a timing chart.
Fig. 2.3.22 Connection diagram
Specifications :•The Serial I/O1, asynchronous serial I/O, is used.
•Transfer bit rate : 9600 bps; f(XIN) = 4.9152 MHz divided by 512
•Communication control using port P00; Port P00 output level is controlled by software.
•2-byte data is transferred from the transmission side to the reception side at 10 ms
intervals which the timer generates
Fig. 2.3.23 Timing chart
P00
TxD
P00
RXD
Transmission side
7534 Group
Reception side
7534 Group
P0
0
10 ms
D0D1D2D3D4D5D6D7
ST SP(2) D0D1D2D3D4D5D6D7
ST SP(2) D0
ST
T
X
D
• • • • •
• • • • •
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 44 of 78
REJ09B0178-0300
Table 2.3.1 shows a setting example of the baud rate generator (BRG) and transfer bit rate values;
Figure 2.3.24 shows the registers setting relevant to transmission side; Figure 2.3.25 shows the
registers setting relevant to reception side
Table 2.3.1 Setting example of baud rate generator (BRG) and transfer bit rate values
BRG count source
(Note 1)
f(XIN) / 4
f(XIN) / 4
f(XIN) / 4
f(XIN) / 4
f(XIN) / 4
f(XIN) / 4
f(XIN) / 4
f(XIN) / 4
f(XIN)
f(XIN)
f(XIN)
BRG set value
255 (FF16)
127 (7F16)
63 (3F16)
31 (1F16)
15 (0F16)
7 (0716)
3 (0316)
1 (0116)
3 (0316)
1 (0116)
0 (0016)
Transfer bit rate (bps) (Note 2)
At f(XIN) = 4.9152 MHz
300
600
1200
2400
4800
9600
19200
38400
76800
153600
307200
At f(XIN) = 6 MHz
366.2109375
732.421875
1464.84375
2929.6875
5859.375
11718.75
23437.5
46875
93750
187500
375000
Notes 1: Select the BRG count source with bit 0 of the serial I/O1 control register (address 1A16).
2: Equation of transfer bit rate:
Transfer bit rate (bps) = f(XIN)
(BRG set value + 1) ✕ 16 ✕ m✽
m✽: m = 1 in the case of bit 0 of the serial I/O1 control
register (address 001A16) = “0”
m = 4 in the case of bit 0 of the serial I/O1 control
register (address 001A16) = “1”
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 45 of 78
REJ09B0178-0300
Fig. 2.3.24 Registers setting relevant to transmission side
UART status register (address 19
16
)
UARTSTS
Transmission side
Baud rate generator (address 1C
16
)
BRG 7
Serial I/O1 control register (addreess 1A
16
)
SIO1CON
BRG count source : f(X
IN
)/4
101 10
UART control register (address 1B
16
)
UARTCON 0
01 0
f(X
IN
)
b0b7
b0b7
b0
b7
b0b7
0
Transmit buffer empty flag
•Confirm that the data has been transferred from
the transmit buffer register to the transmit shift register.
•When this flag is “1”, it is possible to write the next
transmission data into the transmit buffer register.
Transmit shift register shift completion flag
Confirm transmission completion of one-byte
unit using this flag.
“1” : Shift of transmission completed
Continuous transmit invalid
Transmit enabled
Receive disabled
UART mode
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
TxD : CMOS output
Transfer bit rate ✕ 16 ✕ m
✽
✽m = 1 in the case of bit 0 of SIO1CON (address 001A
16
) = “0”
m = 4 in the case of bit 0 of SIO1CON (address 001A
16
) = “1”
Set – 1
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 46 of 78
REJ09B0178-0300
Fig. 2.3.25 Registers setting relevant to reception side
UARTSTS
BRG 7
SIO1CON 10110
UARTCON 0
10
b0
b7
b0b7
b0
b7
b0
b7
0
Reception side
UART status register (address 1916)
Receive buffer full flag
Confirm reception completion of one-byte unit
using this flag.
“1” : At completing reception
“0” : At readting out Receive buffer register
Overrun error flag
“1” : When data is ready into Receive shift
register while Receive buffer register
contains the data
Parity error flag
“1” : When a parity error occurs in the parity
checking enabled
Framing error flag
“1” : When stop bits cannot be detected at the
specified timing
Summing error flag
“1” : When any one of overrun, parity, and framing
errors occurs
Baud rate generator (address 1C16)
Serial I/O1 control register (addreess 1A16)
BRG count source : f(XIN)/4
UART control register (address 1B16)
f(XIN)
Continuous transmit invalid
Transmit disabled
Receive enabled
UART mode
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
Transfer bit rate ✕ 16 ✕ m✽
✽m = 1 in the case of bit 0 of SIO1CON (address 001A 16) = “0”
m = 4 in the case of bit 0 of SIO1CON (address 001A 16) = “1”
Set – 1
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 47 of 78
REJ09B0178-0300
Fig. 2.3.26 Control procedure of transmission side
Figure 2.3.26 shows a control procedure of transmission side, and Figure 2.3.27 shows a control
procedure of reception side.
RESET
P0 (address 00
16
), bit0 1
10 ms pass ?
Y
N
1
0
1
0
SIO1CON
UARTCON
BRG
P0
P0D
10010001
2
00001000
2
8 – 1
XXXXXXX1
2
.....
TB/RB (address 18
16
)
P0 (address 00
16
), bit0 0
UARTSTS (address 19
16
), bit0 ?
1
0
(address 1A
16
)
(address 1B
16
)
(address 1C
16
)
(address 00
16
), bit0
(address 01
16
)
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
•Serial I/O1 setting
•Transmission data write
This write causes Transmit buffer empty
flag to be cleared to “0”.
0
The first byte of
transmission data
TB/RB (address 18
16
)The second byte of
transmission data
UARTSTS (address 19
16
), bit0 ?
UARTSTS (address 19
16
), bit2 ?
•Setting of port P0
0
for communication control
•Generating of a 10 ms interval using Timer
•Communication start
•Confirmation of transfer from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
•Transmission data write
This write causes Transmit buffer empty
flag to be cleared to “0”.
•Confirmation of transfer from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
•Confirmation of Transmit shift register’s shift
completion
(Transmit shift register shift completion flag)
•Communication completion
APPLICATION
7534 Group 2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 48 of 78
REJ09B0178-0300
Fig. 2.3.27 Control procedure of reception side
RESET
UARTSTS (address 19
16
), bit1 ?
1
0
0
1
SIO1CON
UARTCON
BRG
P0D
10100001
2
00001000
2
8 – 1
XXXXXXX0
2
.....
1
0
0
1
P0 (address 00
16
), bit0 ?
0
1
SIO1CON (address 1A
16
) 11XXXXXX
2
(address 1A
16
)
(address 1B
16
)
(address 1C
16
)
(address 01
16
)
10100001
2
00XXXXXX
2
● ✕: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
•Serial I/O1 setting
•Data receception of the first byte
This read causes Receive buffer full flag
to be cleared to “0”.
•Setting of port P0
0
for communication control
Read out received data from
RB (address 18
16
)
UARTSTS (address 19
16
), bit6 ?
Read out received data from
RB (address 18
16
)
UARTSTS (address 19
16
), bit1 ?
UARTSTS (address 19
16
), bit6 ?
SIO1CON (address 1A
16
)
SIO1CON (address 1A
16
)
•Confirmation of reception completion
(Receive buffer full flag)
•Error flag check
•Data receception of the second
byte
This read causes Receive
buffer full flag to be cleared to
“0”.
•Confirmation of reception
completion
(Receive buffer full flag)
•Error flag check
Error process
•Serial I/O1 cleared
•Serial I/O1 disabled
•Serial I/O1 enabled
Countermeasure for a bit slip
(Serial I/O1 clear procedure)
7534 Group
APPLICATION
2.3 Serial I/O
Rev.3.00 Oct 23, 2006 page 49 of 78
REJ09B0178-0300
2.3.6 Notes on serial I/O
(1) Handling of clear the serial I/O1
When serial I/O1 is set again or the transmit/receive operation is stopped/restarted while serial I/O1
is operating, clear the serial I/O1 as shown in Figure 2.3.28.
Fig. 2.3.28 Sequence of clearing serial I/O
→Set again (Note)
○○ ○○
• Serial I/O1 enabled
• Serial I/O1 cleared
• Serial I/O1 disabled
• Serial I/O1 register set again
• Serial I/O1 enabled
Handling of clear the serial I/O1
Note: When the contents of register is not changed, setting again is not necessary.
SIO1CON (address 1A16) bit 7, bit 6 ← 102
SIO1CON (address 1A16) bit 7, bit 6 ← 112
SIO1CON (address 1A16) bit 7, bit 6 ← 002
UARTCON (address 1B16)
BRG (address 1C16)
SIO1CON (address 1A16) ← 10✕✕✕✕✕✕2
Set again (Note)
(2) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) Writing transmit data
When an external clock is used as the synchronous clock for the clock synchronous serial I/O, write
the transmit data to the transmit buffer register (serial I/O shift register) at “H” of the transfer clock
input level.
(4) Serial I/O2 transmit/receive shift completion flag
•The transmit/receive shift completion flag (bit 7) of the serial I/O2 control register is set to “1” after
completing transmit/receive shift. In order to set this flag to “0”, write data (dummy data at reception)
to the serial I/O2 register by program.
•Bit 7 of the serial I/O2 control register is set to “1” a half cycle (of the shift clock) earlier than
completion of shift operation. Accordingly, when using this bit to confirm shift completion, a half
cycle or more of the shift clock must pass after confirming that this bit is set to “1”, before performing
read/write to the serial I/O2 register.
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 50 of 78
REJ09B0178-0300
2.4 USB
This paragraph explains operational outline, the registers relevant to the USB, the registers setting method,
the application example for communication and notes on use.
2.4.1 Outline of USB
7534 Group has USB functions in compliance with the Low-Speed USB2.0 specification which are connection
standard with PC peripherals.
In this section, the outline of USB communication function and the USB function of 7534 Group are
described.
(1) Transfer type
In present PC, 2 or more standards used for the connection with peripherals exist (RS-232C and
Centronics, etc.).
USB tries to unite all those communication standards.
The standard of USB has the host side (PC,Hub) which controls connected peripherals and the
connected peripherals side (device).
The following 3 types of communication standards exist depending on the data amount treated on
the peripherals side.
• Hi-Speed function: H.S.
USB operation at 480Mbps.
• Full-Speed function: F.S.
USB operation at 12Mbps.
• Low-Speed function: L.S.
USB operation at 1.5Mbps.
This communication standard depends on the kind of peripherals.
The transfer type for each peripheral is decided.
Table 2.4.1 shows the transfer types of USB.
Table 2.4.1 Transfer types of USB
Transfer type
Control
Interrupt
Bulk
Isochronous
L.S./F.S./H.S.
L.S./F.S./H.S.
L.S./F.S./H.S.
F.S./H.S.
F.S./H.S.
Operation
This is used when setting up and for all devices common.
This is used when transferring a small amount of data in real time.
This is used when transferring a large amount of data in no real time.
This is used when transferring a large amount of data in real time.
L.S.: Low-Speed function, F.S.: Full-Speed function, H.S.: Hi-Speed function
The 7534 Group has USB Low-Speed function, and the control transfer and interrupt transfer can be
used in Table 2.4.1
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 51 of 78
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(2) Communication sequence
The control transfer and the interrupt transfer have a different communication sequence, respectively.
The control transfer is used when setting up all devices common and communicates combining 3
types of stages in one processing.
The communication starts first in Setup Stage, and Data Stage of the content is executed, and then,
one processing of the communication sequence is completed by executing Status Stage.
Data can be set from host to device through this sequence (=Control Write), and the result can be
read out to host from device (=Control Read).
Use endpoint (ENDP) “0” in the control transfer.
The interrupt transfer is used when transferring a small amount of data in real time.
There is no stage unlike the control transfer.
Only when the host requests data (Token=IN), the device can transmit data.
Use the endpoint in the interrupt transfer excluding “0” (“1” is set for the 7534 Group).
Figure 2.4.1 shows the communication sequence of USB.
Fig. 2.4.1 Communication sequence of USB
Stage
Setup
Token = IN
Data
Status
Data 1 transaction
Handshake
Control Transfer: ENDP (endpoint) = 0
Token = SETUP
Data Handshake
Token = OUT Data Handshake
● Control Read
1 transaction
1 or more transaction
Stage
Setup
Token = IN
Data
Status
Data 1 transaction
Handshake
Token = SETUP
Data Handshake
Token = OUT Data Handshake
1 transaction
1 or more transaction
● Control Write
Interrupt Transfer: ENDP = 1
Token = IN Data Handshake
Stage
Setup
Token = IN
Status
Data 1 transaction
Handshake
Token = SETUP
Data Handshake 1 transaction
● No-data Control
Note: The shaded parts show the case when the device transmits data to the host.
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 52 of 78
REJ09B0178-0300
(3) Packet type
The host side controls all the communications in USB.
Basically, the host gives the device the instruction of the communication processing which the host
side executes (= Token), executes data transmit/receive (= Data), and indicates the completion of the
communication is shown at the end (= Handshake).
These communication processings are executed in order by each one unit which has the data
structure (= Packet format), and one processing (= Transaction) is completed.
The content of processing can be identified according to PID (Packet IDentifier field) which is one
unit of data (Field) which composes each packet.
Not only the content of processing, but also the data structure in the packet can be identified by this PID.
Table 2.4.2 shows the packet type of USB.
Table 2.4.2 Packet types of USB
Packet type
SOF (Start of Frame)
Token
Data
Handshake
Transmitter
Host
Host
Host/Device
Host/Device
Operation
Packet indicating the top of frame (1 ms) including all transfer types
Packet indicating the processing to execute
Packet indicating the transmit/receive data for processing shown by token
Packet indicating the result of communication processing
Fig. 2.4.2 Data structure of USB packet
In 7534 Group, the PID, ADDR, ENDP and DATA of packet structure data in Figure 2.4.2 can be
controlled by software.
In 7534 Group, the token, data, and the handshake of packet types in Table 2.4.2 can be controlled
by software.
(4) Packet structure
As for the packet type of USB, the data and the structure are different by PID.
Each packet includes the following data shown with PID for which the control is required by 7534
Group;
• token: the receiver to communicate (ADDR) and transfer type (ENDP)
• data: execution (DATA) of the processing ordered by the token
• handshake: the completion of the communication
Figure 2.4.2 shows the data structure of the packet.
SOF
(Start Of Frame) SYNC
8bits 8bits
PID 11bits
Frame Number 5bits
CRC5
Token
2bits
EOP
SYNC
8bits 8bits
PID 7bits
ADDR 5bits
CRC5 2bits
EOP
4bits
ENDP
Data SYNC
8bits 8bits
PID 8bits ✕ 0 to 8bytes
DATA 16bits
CRC16 2bits
EOP
Handshake SYNC
8bits 8bits
PID 2bits
EOP
Packet type
Notes 1: The shaded parts show the data which requires processing by software in 7534 Group.
2: The DATA number of data PID shows the number in L.S.
3: Determination of “Start Of Frame” is not executed because the processing is not required.
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 53 of 78
REJ09B0178-0300
(5) Data structure
Data which composes the communication of USB transmits and receives data that the structure
number of bits is different as shown in Figure 2.4.2 continuously by the LSB first.
Basically, the contents except SYNC which is synchronizing signal and EOP which is the completion
signal are treated as data.
Accordingly, the difference of the number of bits can be detected by forecasting and determining the
following data from the content of PID.
Table 2.4.3 shows the content of data which composes the packet.
Table 2.4.3 Data structure of USB packet
Data name
Synchronize
Packet IDentifier
Frame Number
Address
Endpoint
Data
Token CRCs
Data CRCs
End Of Packet
Symbol
Sync
PID
–
ADDR
ENDP
DATA
CRC5
CRC16
EOP
Operation
Synchronized signal to communicate
Data indicating processing of packet
Data to control the frame during communication by time
Data to confirm the transmit destination of packet
and notify from transmitter
Data indicating transfer type used by device
Data to be used when the processing specified by
PID is executed
Data to check error when PID is token and SOF
Data to check error when PID is DATA
Data indicating the completion of packet
Structure
8 bits
8 bits
11 bits
7 bits
4 bits
8 bits ✕ 0 to 8 bytes
5 bits
16 bits
2 bits
Note: The DATA numbers in L.S. are shown in this table.
PID is classified into 3 kinds in the structure data of Table 2.4.3.
Token is used to give the device the instruction of communication processing, and report on the
processing of the following stages. It is only a host to be able to issue the token.
Data is used to transmit and receive data which is the content of the instruction of the token, and
execute the processing in the stage. It is a host to be able to issue the data when the token is SETUP
and OUT, and it is a device when the token is IN.
Handshake indicates the completion of the communication at the end.
It is a host to be able to issue the handshake when the token is IN, and it is a host when the token
is SETUP and OUT.
Table 2.4.4 shows PID.
Table 2.4.4 PID
Packet
type
Token
Data
Handshake
Special
PID name
SETUP
IN
OUT
SOF
DATA0
DATA1
ACK
NAK
STALL
PRE
Processing
The processing is reported by host to device
Data transmit is requested from host to device
Data receive is requested from host to device
Top of frame is indicated by host to device
The state that sequence bit of transmit/receive data is even is indicated
The state that sequence bit of transmit/receive data is odd is indicated
Normal completion of communication is reported
The state that device is waiting for communication is reported
Completion error of communication is reported
Communication to the L.S. device which has low-priority is enabled
Bit structure
(bits 3 to 0)
11012
10012
00012
01012
00112
10112
00102
10102
11102
11002
In 7534 Group, data except SOF and PRE of PID can be controlled by software.
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 54 of 78
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(6) USB special signal
The host side has function to control the state of the device side, and the device side has the function
to transmit the state to the host side and other devices on USB communications line by the signal
besides the above-mentioned data transfer.
Usually, the transfer confirmation [Keep alive, Idle: only for L.S.] is performed on the USB communication
line regardless of data transmit/receive. The contents of transfer confirmation are as follows;
• host confirms the connection of device on the communication line
• device confirms the normal data transfer of host.
The confirmation transfer is transmitted by host side for each frame (1ms/frame) which is the basic
time unit of the USB transfer.
When the host stops all the device, the host informs device of the stop of functions by suspending
the confirmation transfer for 3 ms or more.
The signal to stop the function is called “Suspend”.
The stopped device can be returned by 2 methods.
The return is performed basically when there is a change in the device in the stopped state.
One is a method (change on communications line) to return to a normal state by restarting the data
communication which is suspended before suspend.
The signal to return is called “Resume”.
The other is a method (change on the device) to return to a normal state by the change in an external
input of the device.
The host can inform all the other connected devices of the return of the device by the change in an
external input by outputting K state signal of 1 to 15 ms.
The signal to activate for other devices is called “Remote wake up”.
When the SE0 signal of 2.5 µs or more is input on communications line regardless of the state of
the stop/start of the function of the device side, the packet, and the stage processing, the device
makes all states concerning the USB function initial state.
The signal to initialize is called “Reset”.
Table 2.4.5 shows a special signal of USB.
Table 2.4.5 Special signal of USB
Signal type
Suspend
Resume
Reset
Remote wake up
Operation
Stop of all device function
Return of device function
Initialization of USB setting
Report of return to other devices
Signal format
No data transfer for 3 ms
K state input/reset input in the suspend state
SE0 input for 2.5 µs or more
K state output for 1 to 15 ms
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 55 of 78
REJ09B0178-0300
(7) USB interface
In 7534 Group, the USB interface divides one communications line by 2 depending on the contents
of data.
Figure 2.4.3 shows the interface of USB.
Fig. 2.4.4 USB (L.S.) connection example
Fig. 2.4.3 USB (L.S.) interface
(8) System configuration of USB
In the system configuration used with the low-speed communication device of USB, the host side can
recognize the connection of the low-speed communication device by pull-up the D-pin with the
voltage of 3.0 to 3.6 V and the resistor of 1.5 kΩ of communications lines.
Figure 2.4.4 shows the example of connecting USB (L.S.).
7534 Group
Low-Speed Function
C
o
n
t
r
o
l
t
r
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f
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r
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:
S
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T
U
P
,
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N
,
O
U
T
T
o
k
e
n
:
I
N
Host system
(PC, Hub)
Note: Transfer direction shows the DATA transmission direction of PID.
7
5
3
4
G
r
o
u
p
H
o
s
t
s
y
s
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-
/
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10
U
S
B
V
R
E
F
O
U
T
VC
C
VS
S
Note: Use the USB connector and USB cable specified to the USB specifications.
U
S
B
c
a
b
l
e
(
f
o
r
L
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n
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M
e
t
e
r
s
m
a
x
.
D- pull-up resistor
(1.5kΩ)
USB connector
D
+
/
P
11
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 56 of 78
REJ09B0178-0300
Fig. 2.4.5 Memory map of registers relevant to USB
0018
16
0019
16
001A
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
003C
16
003E
16
Transmit/Receive buffer register (TB/RB)
USB status register (USBSTS)
Serial I/O1 control register (SIO1CON)
USB data toggle synchronization register ( TRSYNC)
USB interrupt source discrimination register 1 (USBIR1)
USB interrupt source discrimination register 2 (USBIR2)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
USB interrupt control register (USBICON)
USB transmit data byte number set register 0 (EP0BYTE)
USB transmit data byte number set register 1 (EP1BYTE)
USBPID control register 0 (EP0PID)
USBPID control register 1 (EP1PID)
USB address register (USBA)
USB sequence bit initialization register (INISQ1)
USB control register (USBCON)
2.4.2 Memory map
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 57 of 78
REJ09B0178-0300
Bit name Function
Remarks
CPU
RD CPU
WR H/W
RD H/W
WR
CPU RD: Read from CPU
Enable: Read enabled
CPU WR: Write from CPU
Set/Clear: Write “0”, “1” enabled
Set: Write only “1” enabled
Clear: Write only “0” enabled
Dummy: Initializing by dummy write enabled
H/W RD: Read by hardware
Use: used by hardware (data is no change)
H/W WR: Write by hardware
Set/Clear: Write “0”, “1” is executed by hardware
Set: Write only “1” is executed by hardware
Clear: Write only “0” is executed by hardware
Shaded area: no R/W function
b7 b6 b5 b4 b3 b2 b1 b0
0, 1 or ✕
✕: Initial value undfined.
Register name: (Symbol): [Address]
Initial value Symbol of bit name
2.4.3 Relevant registers
In this section, the contents of control are described as follows;
• Transmit/Receive buffer
• Setting to enable/disable of each function including USB communication and interrupts
• Determination of USB communication error occurrence
• Setting to stage and handshake by unit of endpoint
• Auto-determination of self-address of USB device
Figure 2.4.6 shows the description of the register structure, and Figure 2.4.7 to Figure 2.4.10 show the
register structures relevant to USB.
Fig. 2.4.6 Description of the register structure
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 58 of 78
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Fig. 2.4.7 Register structures relevant to USB (1)
TB
RB
RxRDY SUME BSTFE PIDE CRCE FEOPE EOP TxRDY
EOP detection flag 0: Not detected
1: Detect
False EOP error flag 0: No error
1: False EOP error
CRC error flag 0: No error
1: CRC error
Setting condition of this flag to “1” is as follows;
• PID of DATA0 or DATA1 cannot be detected at data phase after OUT or SETUP
token
• ACK PID cannot be received at handshake phase during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when bit stuffing error occurs at data phase or handshake phase.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when any error of FEOPE, CRCE, PIDE, or BSTFE occurs.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when data is transferred from shift register to buffer by hardware.
This bit is cleared to “0” by reading from buffer.
Set/
Clear
Ena-
ble
0
Transmit buffer register (TB) [Address 18
16
]
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Initial value ✕✕✕✕✕✕✕✕
Receive buffer register (RB) [Address 18
16
]
0000000
Initial value
00000001
Initial value
USB status register (USBSTS) [Address 19
16
]
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Set/
Clear
Set/
Clear
Set
Set
Set
Set
Set
Set
Clear
Clear
Clear
Clear
Clear
Clear
Set/
Clear Use
–After setting data to address 0018
16
,
the data is transferred to the transmit
shift register automatically.
Receive buffer register can be read out
by reading data from address 0018
16
.
Transmit buffer empty flag (TxRDY) is cleared by writing data to this register.
Receive buffer full flag (RxRDY) is cleared by reading this register.
Transmit buffer
empty flag 0: Buffer full
1: Buffer empty
PID error flag 0: No error
1: PID error
Bit stuffing error flag 0: No error
1: Bit stuffing error
Summing error flag 0: No error
1: Summing error
Receive buffer full
flag 0: Buffer empty
1: Buffer full
This bit is set to “1” when data is transferred from buffer to shift register by hardware.
This bit is cleared to “0” by writing to buffer.
Setting condition of this flag to “1” is as follows;
• Normal EOP detected by hardware
• False EOP flag (FEOPE) set
• Time is out with EOP not detected at data phase or handshake phase
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when the phase is not completed normally.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when the CRC error occurs at the same timing of EOP detection
flag.
This bit is to “0” cleared by writing dummy to this register.
–
7534 Group
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Rev.3.00 Oct 23, 2006 page 59 of 78
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Fig. 2.4.8 Register structures relevant to USB (2)
SQTGL
Endpoint
determination flag 0: Endpoint 0 interrupt
1: Endpoint 1 interrupt
This flag is set to “1” when IN token interrupt of endpoint 1 occurs.
This flag is cleared to “0” when IN token interrupt of endpoint 0 occurs.
Writing to this bit is invalid. Do not write “1” to bits 0 to 6.
RxEP
Suspend request flag 0: No request
1: Suspend request
Suspend request is set to “1” when system enters to state J for 3 ms or more.
Suspend request is cleared to “0” by writing dummy to this register.
RxPID OPID RSTRQ SPRQ
USB reset request
flag 0: No request
1: Reset request
USB reset request is set to “1” when the SE0 signal is input for 2.5 µs or more.
USB reset request is cleared to “0” when the SE0 signal is stopped.
Token PID
determination flag 0: SETUP interrupt
1: OUT interrupt
This flag is set to “1” during no SETUP transaction.
This flag is cleared to “0” when PID of SETUP is detected.
Token interrupt flag 0: No interrup
1: OUT/SETUP token interrupt
This flag is set to “1” when OUT or SETUP interrupt occurs.
This flag is cleared to “0” after the end of transaction.
Endpoint 1 enable 0: Endpoint 1 invalid
1: Endpoint 1 valid
USBE TKNE EP1ERSME
USB reset interrupt
enable 0:USB reset invalid
1:USB reset valid
This flag is invalid in suspend mode (USB reset is always valid in suspend mode).
Resume interrupt
enable 0: Resumue invalid
1: Resume valid
Token interrupt
enable 0:Token invalid
1:Token valid
RSTE
USB enable flag 0:USB invalid
1:USB valid
The internal state can be initialized by clearing this flag to “0”.
The initial values of registers are as follows;
• USB status register [address 1916] = (0116)
• USB data toggle synchronization register [address 1D 16] = (7F16)
• USB interrupt source discrimination register 1 [address 1E 16] = (7F16)
• Bits 7, 6 and 2 of USB interrupt source discrimination register 2 [address 1F 16]
= (00xxx0xx2)
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
USB interrupt source discrimination register 2 (USBIR2) [Address 1F
16
]
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
USB data toggle synchronization register (TRSYNC) [Address 1D
16
]
0Initial value
0Initial value
0Initial value 0 01
0Initial value 0 0 0 0
USB interrupt source discrimination register 1 (USBIR1) [Address 1E
16
]
USB interrupt control register (USBICON) [Address 20
16
]
Ena-
ble Clear Set
Ena-
ble Set/
Clear
Ena-
ble SetClear
Ena-
ble
Ena-
ble
Ena-
ble Set/
Clear
Set/
Clear
Set/
Clear
Ena-
ble Set/
Clear
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Set/
Clear
Set/
Clear
Set/
Clear
Set/
Clear
Use
Use
Use
Use
Use
Sequence bit toggle
flag 0: No toggle
1: Sequence toggle
Setting condition of this flag to “1” is as follows;
• Setting of handshake for OUT token in EP0PID is ACK, toggle of data PID is
performed normally, and errors do not occur at data phase during OUT and
SETUP transaction.
• When ACK is received during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
APPLICATION
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Rev.3.00 Oct 23, 2006 page 60 of 78
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Fig. 2.4.9 Register structures relevant to USB (3)
–Set the number of data byte for
transmitting with endpoint 0
EP0BYTE
0
Endpoint 0 enable
flag 0: Endpoint 0 invalid
1: Endpoint 0 valid
Unexpected IN or OUT transaction can be ignored by clearing this flag to “0”.
(SETUP transaction cannot be ignored, it is always valid.)
DPID0 0000
SPID0I APID0 SPID0O EP0E
Endpoint 0 PID selection
flag (OUT STALL)
DPID0 and SPID0I are used to control the response for IN token.
DPID0 is used with the token interrupt enable flag (TKNE).
DPID0 is cleared to “0” automatically by hardware when ACK is received.
SPID0O and APID0 are used to control the response for OUT token.
When DPID0 is changed during token packet, the changed value is valid after end
of token.
–Set the number of data byte for
transmitting with endpoint 1
EP1BYTE
Endpoint 0 PID selection
flag (OUT ACK)
Endpoint 0 PID selection
flag (IN STALL)
Endpoint 0 PID selection
flag (IN DATA0/1)
0
DPID1 0
SPID1
1✕: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NAK handshake is valid for IN token
DPID1 and SPID1 are used to control the response for IN token.
DPID1 is used with the token interrupt enable flag (TKNE).
DPID1 is cleared to “0” automatically by hardware when ACK is received.
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
Initial value
1✕✕✕: IN token interrupt of DATA 0/1 is valid
01✕✕: STALL handshake is valid for IN token
00✕✕: NAK handshake is valid for IN token
✕✕✕1: STALL handshake is valid for OUT
token
✕✕10: ACK handshake is valid for OUT token
✕✕00: NAK handshake is valid for OUT token
Initial value
Initial value
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
✕: it can be set to 0 or 1.
✕: it can be set to 0 or 1.
USB transmit data byte number set register 0 (EP0BYTE) [Address 21
16
]
Initial value
0000 0000
0000 0000
USB transmit data byte number set register 1 (EP1BYTE) [Address 22
16
]
USB PID control register 0 (EP0PID) [Address 23
16
]
USB PID control register 1 (EP1PID) [Address 24
16
]
Ena-
ble Set/
Clear Use
Ena-
ble Set/
Clear Use
Ena-
ble Set/
Clear Use
Set/
Clear Use
Set/
Clear Use
Set/
Clear Use
Set/
Clear Use Clear
Set/
Clear Use
Set/
Clear Use Clear
Endpoint 1 PID selection
flag (IN STALL)
Endpoint 1 PID selection
flag (IN DATA0/1)
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
7534 Group
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Rev.3.00 Oct 23, 2006 page 61 of 78
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Fig. 2.4.10 Register structures relevant to USB (4)
USBA
0000000
As sequence bit of endpoint 1 is
initialized.
INISQ1
Dummy
MOD1 MOD0
00: I/O port
01:Not available
10:UART mode
11:USB mode
Sequence is initialized by writing dummy.
00: Output off
1: Output on
WKUP UVOE
Remote wake up
request flag 0: No request
1:Remote wake up request
Remote wake up request (K output) can be set by setting this flag to “1”.
This flag is cleaed to “0” automatically after 10 ms from remote wake up request.
Clear
USBVREFOUT output
valid flag
PE TE TIC CTE CSS
Note: Only bits 6 and 7 of SIO1CON are described in this figure because only these bits are used for USB.
0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
USB control register (USBCON) [Address 27 16]
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
CPU
RD CPU
WR H/W
RD H/W
WR
Serial I/O1 mode
selection bit
Serial I/O1 mode
selection bit
USB address register (USBA) [Address 25 16]
Initial value
–
–
Initial value
USB sequence bit initialization register (INISQ1) [Address 26 16]
✕✕✕✕✕✕✕✕
Initial value
Serial I/O1 control register (SIO1CON) [Address 1A 16]
Initial value 00 Set/
Clear Use
Set/
Clear Use
Set Use
Set/
Clear Use
Set/
Clear Use
Set an address allocated by the
USB host
APPLICATION
7534 Group 2.4 USB
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Fig. 2.4.11 Control method of control sequence
2.4.4 USB application example
In this section, the application examples when using the USB communication are described using examples
of the timing chart and register setting.
(1) Example of processing each control sequence
In 7534 Group, the control and the determination of the control sequence are executed by software.
The content of processing is executed in the setup stage, transmitting and receiving the data stage
of the content are executed, and the completion of the sequence is shown in the status stage.
Note that the contents of the control and the determination are different even in the software of 7534
Group, because the following processing is different respectively depending on the content of the
setup stage.
In the control transfer, the processing since the data stage is determined when receiving the setup
stage, the execution of the transmit and receive processing and the number of data bytes are
controlled, the status stage at the end is executed, and the sequence is completed.
Only the control of each packet is performed because there is no stage in the interrupt transfer.
Figure 2.4.11 shows the control method of control sequence.
Setup Stage Status Stage
1. Control Read
SETUP
OUT STALL
(SPID0O)
2. Control Write
Endpoint 0 valid
DATA0 IN DATA1
Data Stage
IN DATA0 IN DATA1 IN DATA0 OUT DATA1
OUT ACK
(APID0)
IN STALL
(SPID0I)
IN DATA0/1
(DPID0)
OUT token:STALL, IN token:DATA0/1 OUT token:ACK, IN token:STALL
Setup Stage Status Stage
SETUP DATA0 OUT DATA1
Data Stage
OUT DATA0 OUT DATA1 OUT DATA0 IN DATA1
OUT token:ACK, IN token:STALL OUT token:STALL, IN token:DATA0/1
Endpoint 0 enable flag
(EP0E)
Endpoint 0 PID selection flag
Sequence bit toggle flag
(SQTGL)
OUT STALL
(SPID0O)
OUT ACK
(APID0)
IN STALL
(SPID0I)
IN DATA0/1
(DPID0)
Endpoint 0 enable flag
(EP0E)
Endpoint 0 PID selection flag
Sequence bit toggle flag
(SQTGL)
Endpoint 0 valid
Endpoint 0 invalid
Endpoint 0 invalid
SETUP, no error IN, ACK receive
(4 transaction) OUT, no error
SETUP, no error OUT, no error
(4 transaction) IN, ACK receive
Notes 1: Only token and DATA0/1 of PID are shown in this figure.
2: In this example, data stage is 4 transaction.
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 63 of 78
REJ09B0178-0300
Fig. 2.4.12 Timing chart of the transaction according to each token
(2) Example of processing each transaction
In 7534 Group, the control and the determination of the packet are executed by software.
First, the content of the received token is determined, transmit and receive data according to it are
executed, the completion of the transaction is shown by the handshake.
Note that the contents of the control and the determination are different even of the software so that
processing is different depending on the content of the token.
Figure 2.4.12 shows timing chart of the transaction according to each token.
Token
CRC5 EOP
Data Handshake
1. SETUP token transaction
SETUP ADDR ENDP CRC16SYNC
OUT token interrupt
(Interrupt processing)
EOP detection flag
(EOP)
Summing error flag
(SUME)
Receive buffer full flag
(RxRDY)
Token PID determination flag
(OPID)
Token interrupt flag
(RxPID)
2. OUT token transaction
3. IN token transaction
SETUP PID detected SETUP interrupt occurs
Data received/read (2 bytes)
CRC error occurs
(CRCE) PID error occurs
(PIDE)
SYNC DATA0 DATAa DATAb EOP SYNC ACK EOP
False EOP error occurs
(FEOPE)
EOP detected
(Data)
Token
CRC5 EOP
Data Handshake
OUT ADDR ENDP CRC16SYNC
OUT PID detected OUT interrupt occurs
Data received/read (2 bytes)
CRC error occurs
(CRCE) PID error occurs
(PIDE)
SYNC DATA0/1 DATAa DATAb EOP SYNC ACK EOP
EOP detected
(Data) EOP detected
(Handshake)
Token
CRC5 EOP
Data Handshake
IN ADDR ENDP CRC16SYNC SYNC DATA0/1 DATAa DATAb EOP SYNC ACK EOP
CRC error occurs
(CRCE) PID error occurs
(PIDE)
IN interrupt occurs
Data written and transmitted (2 bytes)
EOP detected
(Data) EOP detected
(Handshake)
EOP detected
(Token) EOP detected
(Handshake)
False EOP error
occurs (FEOPE)
False EOP error
occurs (FEOPE) False EOP error occurs
(FEOPE)
False EOP error occurs
(FEOPE)
EOP detected
(Token)
EOP detected
(Token)
OUT token interrupt
(Interrupt processing)
Summing error flag
(SUME)
Receive buffer full flag
(RxRDY)
Token PID determination flag
(OPID)
Token interrupt flag
(RxPID)
EOP detection flag
(EOP)
IN token interrupt
(Interrupt processing)
EOP detection flag
(EOP)
Summing error flag
(SUME)
Transmit buffer empty flag
(TxRDY)
Endpoint determination flag
(RxEP)
False EOP error occurs
(FEOPE)
Notes 1: The data number of PID = DATA0/1 is 2 bytes in this example.
2: Endpoint (ENDP) is 0 in this example.
3: The dot line on SUME shows the timing of each error occur.
CRC error occurs
(CRCE)
CRC error occurs
(CRCE)
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 64 of 78
REJ09B0178-0300
(3) Interrupt processing
In 7534 Group, the interrupt related to the USB communication processes 7 sources 2 jump destination.
Accordingly, determine the interrupt source and execute the processing after executing the interrupt
processing.
Moreover, control the USB function and the interrupt source which has been enabled before interrupt
is enabled.
The interrupt jump destination and the source are shown as follows.
IN token interrupt: IN token (endpoint 0) and IN token (endpoint 1)
OUT token interrupt: OUT token, SETUP token, Reset, Suspend, and Resume
The determination (processing at the OUT token in figure) by the interrupt and the setting of a related
register when using the interrupt of the OUT token is shown in Figure 2.4.13. The determination
(processing at the IN token (endpoint 0) in figure) by the interrupt and the setting a related register
when using the interrupt of the IN token in Figure 2.4.14.
In the OUT token interrupt, read data of OUT token and SETUP token at the timing shown in Figures
2.4.15 and 2.4.16. Also, in the IN token interrupt, write data to IN token (endpoint 0) and IN token
(endpoint 1) at the timing shown in Figure 2.4.17.
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 65 of 78
REJ09B0178-0300
Fig. 2.4.13 USB interrupt processing example (OUT token)
OUT token interrupt
Main processing
Set USB communication
Set OUT token enabled
RTI
Interrupt source = Reset/
Supend/Resume processing ?
OUT token ?
Communication error occur ?
Data receive executed
Data toggle ?
Notes 1: In this figure, only USB in interrupt processing is described.
Note that the storing stack, etc. is not described.
2: Data shown by ? in program description expresses determination
or data setting.
[Flow chart] [Program description]
SIO1CON 11✕✕✕✕✕✕
2
Set hardware (I/O port) to USB mode
USBICON 1✕✕✕✕✕✕✕
2
Set internal state to USB enabled
USBICON ✕1✕✕✕✕✕✕
2
Set token interrupt to be valid
EP0PID ✕✕✕✕1✕✕✕
2
Set endpoint 0 to be valid
USBIR2 ?✕✕✕✕✕✕✕
2
Interrupt by token if ? = “1”
USBIR2 ✕?✕✕✕✕✕✕
2
Interrupt by OUT token if ? = “1”
USBSTS ✕?????✕✕
2
No error if all ? = “0”
Error/No error can be determined by SUME of bit 6
RB ????????
2
Read receive data
(Max. 8 bytes in 1 interrupt
processing)
TRSYNC ?✕✕✕✕✕✕✕
2
Toggle normally if ? = “1”
IREQ1
ICON1
Set OUT token interrupt
enabled ✕✕✕✕✕✕0✕
2
✕✕✕✕✕✕1✕
2
Initialize OUT token interrupt request
Set OUT token interrupt enable
(
()
)
No Reset/Supend/Resume
processing
Reset/Supend/
Resume processing
OUT
SETUP
No
Yes
No
Yes
USBA ✕0000000
2
Initial USB address = “0”
()
*B *A Set handshake In normal receive, handshake is set to ACK (*A).
When communication error or data doggle error occur, handshake is
set to NAK or STALL according to the contents (*B).
To Reset/Supend/
Resume processing
To Setup processing
*D *C Store this receive data
●✕: Not used here.
Set it to “0” or “1” arbitrary.
In normal receive, data is stored (*C).
When communication error or data doggle error occur, received data
in this time is canceled (*D).
USBCON ✕1✕✕✕✕✕✕
2
Use USBV
REFOUT
pin
USBIR2 ✕✕✕✕?✕✕✕
2
Interrupt by reset if ? = “1”
USBIR2 ✕✕✕✕✕?✕✕
2
Interrupt by suspend if ? = “1”
USBICON ✕✕?✕✕✕✕✕
2
Interrupt by resume if ? = “1”
Note: Set RSME to “1” only in suspend processing
Interrupt source = token ?
Token
No token
RTI
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 66 of 78
REJ09B0178-0300
Fig. 2.4.14 USB interrupt processing example (IN token)
RTI
SIO1CON 11✕✕✕✕✕✕ 2
USBICON ✕1✕✕✕✕✕✕ 2
EP0PID ✕✕✕✕1✕✕✕ 2
USBICON ✕✕✕✕1✕✕✕2
USBIR1 ?✕✕✕✕✕✕✕ 2Endpoint 0 interrupt occurs if ? = “0”
USBSTS ✕?????✕✕ 2
TB ???????? 2
EP0BYTE ???????? 2
()
TRSYNC ?✕✕✕✕✕✕✕ 2
IREQ1
ICON1 ✕✕✕✕✕✕✕0 2
✕✕✕✕✕✕✕1 2
(
()
)
0
1
No
Yes
No
Yes
USBA ✕0000000 2
()
EP0BYTE ✕✕✕✕???? 2Set the number of transmit data byte
Write transmit data
(Max. 8 bytes in 1 interrupt processing)
*B *A
Main processing
[Flow chart] [Program description]
●✕: Not used here.
Set it to “0” or “1” arbitrary.
Set USB communication
Set IN token enabled
Set I/O port to USB mode
USBICON 1✕✕✕✕✕✕✕
2Set internal state to USB enabled
USBCON ✕1✕✕✕✕✕✕ 2Use USBVREFOUT pin
Set token interrupt to be valid
Set endpoint 0 to be valid
Set IN token interrupt
enabled Initialize IN token interrupt request
Set IN token interrupt enable
Initial USB address = “0”
Set endpoint 1 to be valid
Communication error occur ?
Data transmit executed
Data toggle ?
No error if all ? = “0”
Error/No error can be determined
by SUME of bit 6
Set the number of transmit data
in this stage
Toggle normally if ? = “1”
In normal tramsmit, the next transmit data is set (*A).
When communication error or data doggle error occur,
transmit is executed again (*B).
Store next transmit data
Endpoint = 0 or 1 ?
To endpoint processing
IN token interrupt
Notes 1: In this figure, only USB in interrupt processing is described.
Note that the storing stack, etc. is not described.
2: IN token interrupt processing of only endpoint 0 is shown in this example.
3: Data shown by ? in program description expresses determination or data setting.
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 67 of 78
REJ09B0178-0300
Fig. 2.4.15 Data read timing of SETUP token
Fig. 2.4.16 Data read timing of OUT token
Fig. 2.4.17 Data read timing of IN token (endpoint 0) and IN token (endpoint 1) token
SYNC PID ADDR
ENDP
CRC EOP SYNC PID Data X Data Y CRC16
SETUP token interrupt occurs Read Data 0
EOP
34 bit times = 22.7 µs = 136 cycle
Notes 1: In this case, Data: 2 bytes, Cycle: 6 MHz.
2: Max. 14 cycles are required until the interrupt occurs.
SYNC PID ADDR ENDP CRC EOP SYNC PID Data X Data Y CRC16 EOP
34 bit times = 22.7 µs = 136 cycle
OUT token interrupt occurs Read Data 0
Notes 1: In this case, Data: 2 bytes, Cycle: 6 MHz.
2: Max. 14 cycles are required until the interrupt occurs.
SYNC PID ADDR ENDP CRC
EOP
SYNC PID Data X CRC16
EOP
22.5 bit times = 15 µs = 90 cycle
IN token interrupt occurs Read Data 0
Notes 1: In this case, Data: 1 byte, Cycle: 6 MHz.
2: Max. 14 cycles are required until the interrupt occurs.
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 68 of 78
REJ09B0178-0300
Fig. 2.4.18 Timing chart of each signal
(4) Processing to special signal
In 7534 Group, control the USB function to the signal shown in Table 2.4.5 by software.
At USB reset, initialize the registers relevant to USB described in the above section 2.4.3.
Also, at Suspend, execute the STP instruction after the interrupt is enabled.
Set an external interrupt which is the return condition from the stopped state before STP instruction.
The enable of resume is included in this condition.
The generation of these signals can be recognized by the interrupt request.
The interrupt to a special signal is all included in the OUT token interrupt.
IN token interrupt: IN token (endpoint 0) and IN token (endpoint 1)
OUT token interrupt: OUT token, SETUP token, Reset, Suspend, and Resume
The remote wake up function is used to output signals when to output as USB function is required
for the return from the stopped state by an external input.
Figure 2.4.18 shows timing chart of each signal.
Notes 1: In this example, USB reset interrupt enable flag (RSTE) = “1” (enabled).
2: The remote wake up request flag (WKUP) is not set to “1” when host does not request
the remote wake up signal output.
3: External input interrupts: key on wake up, INT
0
, INT
1
and CNTR
0
interrupt.
Remote wake up request
flag
(WKUP)
Remote wake up signal output
(10 ms)
Reset signal input
(2.5 µs or more)
Suspend interrupt occurs
STP instruction executed
Remote wake up signal output request
Reset interrupt occursExternal input interrupt occurs
2. External interrupt return from SUSPEND
OUT token interrupt
(Interrupt processing)
Suspend request flag
(SPRQ)
Resume interrupt enable
(RSME)
USB reset request flag
(RSTRQ)
D-pin state
Keep alive
(1 ms interval) No change of
communication line
(3 ms or more)
Microcomputer
operation
Reset signal input
(2.5 µs or more)
Suspend interrupt occurs
STP instruction executed
Reset interrupt occursResume interrupt occurs
1. Resume interrupt return from Suspend
OUT token interrupt
(Interrupt processing)
Suspend request flag
(SPRQ)
Resume interrupt enable
(RSME)
USB reset request flag
(RSTRQ)
D-pin state
Microcomputer
operation
Keep alive
(1 ms interval) No change of
communication line
(3 ms or more)
7534 Group
APPLICATION
2.4 USB
Rev.3.00 Oct 23, 2006 page 69 of 78
REJ09B0178-0300
Fig. 2.4.20 Processing for width of SE0 signal
2.4.5 Notes concerning USB
(1) Determination of interrupt condition in OUT token interrupt processing
Determine the occurrence of the reset/suspend/resume interrupt from other interrupt conditions in the
order as shown in Figure 2.4.19 when they occur in the OUT token interrupt processing.
Fig. 2.4.19 Example for determination of resume interrupt
(2) Clear of suspend request flag
When the request of the suspend interrupt occurs, the suspend request flag is set to “1”. After the
suspend state is fixed, the state of this flag is retained during fixed time (13 µs).
The purpose of this is to retain the internal state until the count source to measure the time (3 ms)
until suspend is fixed is updated.
Accordingly, the state might not change even if this flag is cleared to “0” immediately after the
suspend request flag is “1” is determined.
Clear this flag to “0” after the wait of 13 µs or 79 machine cycle (f(XIN) =6 MHz time) after this flag is “1”.
(3) Determination of SE0 signal
In 7534 Group, USB reset and EOP can be distinguished according to the width of the SE0 signal.
However, there is the time zone which corresponds any on the dividing line of the time of the width of the signal.
Moreover, the control in a present state is required because there is a difference in processing by
the state of the device.
Accordingly, select the processing method in software by the state of the device.
Figure 2.4.20 shows processing to the width of the signal according to the situation.
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0 µs
Idle state
EOP(RxPID=1)
Signal ignored
0.50 µs 2.50 µs 2.67 µs
D-pin state
TKNE, RSME, RSTE
Token phase state
Data/Handshake
phase state
Suspend state
Signal ignored(FEOPE=1)
✕
1
0
0
0
0
0
0
1
1
1
0/1 Signal ignored(FEOPE=1)
Keep Alive Keep Alive/Reset(RSTRQ=1) Reset(RSTRQ=1)
Reset(RSTRQ=1)/Resume(RSTRQ=0)
Reset(RSTRQ=1)
Reset(RSTRQ=1)
EOP(RxPID=1)/Reset(RxPID=0)
Note: Each active state represents the processing is required in “H” state.
EOP(EOP=1) EOP(RSTRQ=0)/Reset(RSTRQ=1)
APPLICATION
7534 Group 2.4 USB
Rev.3.00 Oct 23, 2006 page 70 of 78
REJ09B0178-0300
(4) USB communication
In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.
(5) USB suspend current
When USB suspend mode with TTL level on P10, P12, P13 input level selection bit (bit 3 of address
1716) set to “1”, suspend current as ICC might be greater than 300 µA as a spec.
[Countermeasure]
There are two countermeasures by software to avoid it as follows.
(1) Change from TTL input level to CMOS input level for P10, P12, P13 port input.
(2) Change from TTL input level to CMOS input level before STP instruction in suspend routine;
then after RESUME or Remote wake up interrupt, return to TTL input level from CMOS input
level. That is shown in Figure 2.4.21.
Fig. 2.4.21 Countermeasure (2) by software
SUSPEND Ro utin e
R
E
S
U
M
E
R
o
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e
STP
Configur ation to CMO S input
lev e l fo r P10, P12, P13 input level.
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x
x
x
x
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0
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x
2
Configur ation to CMO S
inp u t level fo r P10, P12, P13
inp u t level.
P1P3C xxxxx1xx
2
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for P10, P12, P13 input level.
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7534 Group
APPLICATION
2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 71 of 78
REJ09B0178-0300
2.5 A/D converter
This paragraph explains the registers setting method and the notes relevant to the A/D converter.
2.5.1 Memory map
Fig. 2.5.1 Memory map of registers relevant to A/D converter
2.5.2 Relevant registers
Fig. 2.5.2 Structure of A/D control register
0
0
3
41
6
003516
0
0
3
61
6
003C16
A
/
D
c
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g
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(
A
D
C
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)
A/D conversion register (low-order); (ADL)
A
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Int er r upt edge sele c tion regist er ( INTEDGE)
b7 b6 b5 b4 b3 b2 b1 b0
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4
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✕
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1
:
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1
0
1
0
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P
2
2
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A
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2
0
1
1
:
P
2
3
/
A
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3
1
0
0
:
P
2
4
/
A
N
4
1
0
1
:
P
2
5
/
A
N
5
1
1
0
:
P
2
6
/
A
N
6
(N
o
t
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1
1
1
:
P
2
7
/
A
N
7
(
N
o
t
e
)
Analog input pin selection bits
b
2
b
1
b
0
0
0
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
✕
✕
N
o
t
e
:
P
2
6
/
A
N
6
,
P
2
7
/
A
N
7
c
a
n
b
e
s
e
l
e
c
t
e
d
i
n
t
h
e
3
6
-
p
i
n
a
n
d
4
2
-
p
i
n
v
e
r
s
i
o
n
s
.
✽:
T
h
i
s
b
i
t
c
a
n
b
e
c
l
e
a
r
e
d
t
o
“
0
”
b
y
p
r
o
g
r
a
m
,
b
u
t
c
a
n
n
o
t
b
e
s
e
t
t
o
“
1
”
.
✽
APPLICATION
7534 Group 2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 72 of 78
REJ09B0178-0300
Fig. 2.5.3 Structure of A/D conversion register (high-order)
Fig. 2.5.4 Structure of A/D conversion register (low-order)
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
b
7b
6b
5b
4b3b
2b
1b
0
BFunction
A
t reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
A/D conversion register (high-order) (ADH) [Address : 3616]
The read-only register in which the A/D conversion’s results are
stored. ✕
✕
✕
✕
✕
✕
✕
✕
< 10-bit read>
b
7b9 b0
b8
N
o
t
h
i
n
g
i
s
a
l
l
o
c
a
t
e
d
f
o
r
t
h
e
s
e
b
i
t
s
.
T
h
e
s
e
a
r
e
w
r
i
t
e
d
i
s
a
b
l
e
d
b
i
t
s
.
W
h
e
n
t
h
e
s
e
b
i
t
s
a
r
e
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
s
a
r
e
“
0
”
.
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
A
t reset RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
A/D conversion register (low-order) (ADL) [Address : 35
16
]
The read-only register in which the A/D conversion’s results are
stored. ✕
✕
✕
✕
✕
✕
✕
✕
< 8-bit read>
b
7b
8b
7b
6b5b4b3b0
b2b
9
< 10-bit read>
b
7b6 b5 b4 b3 b2 b1 b0
b0b7
7534 Group
APPLICATION
2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 73 of 78
REJ09B0178-0300
Fig. 2.5.5 Structure of Interrupt edge selection register
Fig. 2.5.6 Structure of Interrupt request register 1
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
6
7
Name 0
0
0
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
INT0 interrupt edge
selection bit (Note 1)
INT1 interrupt edge
selection bit (Note 2)
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
Serial I/O1 or INT1 interrupt
selection bit
Timer X or key-on wake up
interrupt selection bit
Timer 2 or serial I/O2 interrupt
selection bit
CNTR0 or AD converter
interrupt selection bit
0 : Serial I/O1
1 : INT1
0 : Timer X
1 : Key-on wake up
0 : Timer 2
1 : Serial I/O2
0 : CNTR0
1 : AD converter
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
05
CNTR
0
or AD converter
interrupt request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
4
5
6
7
Name 0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C
16
]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
UART receive/USBIN token
interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 or serial I/O2 interrupt
request bit
✽: These bits can be cleared to “0” by program, but cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
INT
0
interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
✽
✽
✽
✽
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt
request bit (Note 1)
30✽
APPLICATION
7534 Group 2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 74 of 78
REJ09B0178-0300
Fig. 2.5.7 Structure of Interrupt control register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”. ✕
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt
enable bit
CNTR
0
or AD converter
interrupt enable bit
INT
0
interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt enable
bit (Note 1)
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
0
7534 Group
APPLICATION
2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 75 of 78
REJ09B0178-0300
2.5.3 A/D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage from a sensor is converted to digital values.
Figure 2.5.8 shows a connection diagram, and Figure 2.5.9 shows the relevant registers setting.
Fig. 2.5.8 Connection diagram
Specifications :•The analog input voltage from a sensor is converted to digital values.
•P20/AN0 pin is used as an analog input pin.
Fig. 2.5.9 Relevant registers setting
P2
0
/AN
0
7534 Group
Sensor
A/D control register (address 34
16
)
A
D
C
O
N
0
Analog input pin : P2
0
/AN
0
selected
A
/
D
c
o
n
v
e
r
s
i
o
n
s
t
a
r
t
000
b
0
b
7
A/D conversion register (high-order); (address 36
16
)
A
D
H
A
D
L
b
0
b
7
b
0
b
7
(
R
e
a
d
-
o
n
l
y
)
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
;
(
a
d
d
r
e
s
s
3
5
1
6
)
(Read-only)
A result of A/D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 0036
16
before address 0035
16
;
when reading 8-bit data, read address 0035
16
only.
APPLICATION
7534 Group 2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 76 of 78
REJ09B0178-0300
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.5.9. Figure 2.5.10 shows the control procedure for 8-bit read, and
Figure 2.5.11 shows the control procedure for 10-bit read.
A
D
C
O
N
(
a
d
d
r
e
s
s
3
4
1
6
)
,
b
i
t
0
–
b
i
t
2
A
D
C
O
N
(
a
d
d
r
e
s
s
3
4
1
6
)
,
b
i
t
40
0
0
2
0
R
e
a
d
o
u
t
A
D
L
(
a
d
d
r
e
s
s
3
5
1
6
)
A
D
C
O
N
(
a
d
d
r
e
s
s
3
4
1
6
)
,
b
i
t
4
?
1
0
•
P
2
0
/
A
N
0
p
i
n
s
e
l
e
c
t
e
d
a
s
a
n
a
l
o
g
i
n
p
u
t
p
i
n
•
A
/
D
c
o
n
v
e
r
s
i
o
n
s
t
a
r
t
•
J
u
d
g
m
e
n
t
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
•
R
e
a
d
o
u
t
o
f
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
ADCO N (address 34
16
), bit0 – bit2
ADCO N (address 34
16
), bit4 0
0
0
2
0
R
e
a
d
o
u
t
A
D
H
(
a
d
d
r
e
s
s
3
6
1
6
)
A
D
C
O
N
(
a
d
d
r
e
s
s
3
4
1
6
)
,
b
i
t
4
?
1
0
•
P
2
0
/
A
N
0
p
i
n
s
e
l
e
c
t
e
d
a
s
a
n
a
l
o
g
i
n
p
u
t
p
i
n
•
A
/
D
c
o
n
v
e
r
s
i
o
n
s
t
a
r
t
•
J
u
d
g
m
e
n
t
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
•
R
e
a
d
o
u
t
o
f
h
i
g
h
-
o
r
d
e
r
d
i
g
i
t
(
b
9
,
b
8
)
o
f
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
Read out ADL (address 35
16
)•
R
e
a
d
o
u
t
o
f
l
o
w
-
o
r
d
e
r
d
i
g
i
t
(
b
7
–
b
0
)
o
f
c
o
n
v
e
r
s
i
o
n
r
e
s
u
l
t
Fig. 2.5.10 Control procedure for 8-bit read
Fig. 2.5.11 Control procedure for 10-bit read
7534 Group
APPLICATION
2.5 A/D converter
Rev.3.00 Oct 23, 2006 page 77 of 78
REJ09B0178-0300
2.5.4 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01µF to 1µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion/comparison precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more
• Do not execute the STP instruction
(3) Method to stabilize A/D Converter
Method to stabilize A/D Converter is described below.
(a) A/D conversion accuracy could be affected for Bus Powered*1 USB devices, while the communicating.
Figure 2.5.12 shows the method to stabilize A/D conversion accuracy, inserting a capacitor between
Vref and VSS.
*1: Power supplied by USB VCC BUS.
Fig. 2.5.12 Method to stabilize A/D conversion accuracy
AN
0
to AN
7
V
cc
C
N
V
s
s
1 µF
0
.
0
1
t
o
1
µF
V
r
e
f
V
ss
1
t
o
1
0
kΩ
0
.
1
t
o
1
µF:
R
e
c
o
m
m
e
n
d
s
f
o
r
A
/
D
a
c
c
u
r
a
c
y
0
.
2
2
µF
7534 Group
1.5 kΩ
U
S
B
V
R
E
F
O
U
T
D-
(b) It is recommended for A/D accuracy to avoid converting while USB communication, and use
average value of several converted values.
APPLICATION
7534 Group 2.6 Reset
Rev.3.00 Oct 23, 2006 page 78 of 78
REJ09B0178-0300
2.6 Reset
2.6.1 Connection example of reset IC
Figure 2.6.1 shows the system example to switch to the RAM back-up mode when detecting the falling of
system power source by the INT interrupt.
V
CC
RESET
1
5
RESET
INT
Cd
V
CC
1
V
CC
2
V1 GND
2
6
3
7
System power
source
+ 5 V
M62009L,M62009P,M62009FP
47534 Group
+
INT
V
SS
Fig. 2.6.1 Example of poweron reset circuit
2.6.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Typical characteristics
3.3 Notes on use
3.4
Countermeasures against noise
3.5 List of registers
3.6 Package outline
3.7 List of instruction code
3.8 Machine instructions
3.9 SFR memory map
3.10 Pin configurations
APPENDIX
7534 Group 3.1 Electrical characteristics
Rev.3.00 Oct 23, 2006 page 2 of 70
REJ09B0178-0300
Table 3.1.1 Absolute maximum ratings
–0.3 to 7.0
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to 13
–0.3 to VCC + 0.3
1000 (Note 3)
–20 to 85
–40 to 125
Power source voltage
Input voltage P00–P07, P10–P16, P20–P27, P30–
P37, VREF, P40, P41
Input voltage RESET, XIN
Input voltage CNVSS (Note 1)
Output voltage P00–P07, P10–P16, P20–P27, P30–
P37, XOUT, USBVREFOUT, P40, P41
Power dissipation (Note 2)
Operating temperature
Storage temperature
V
V
V
V
V
mW
°C
°C
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
ConditionsSymbol Ratings Unit
Parameter
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Notes 1: It is a rating only for the One Time PROM version. Connect to VSS for mask ROM version.
2: The rating value depends on packages.
3: This is the value for the 42-pin version.
The value of the 36-pin version is 300 mW.
The value of the 32-pin version is 200 mW.
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
7534 Group
APPENDIX
3.1 Electrical characteristics
Rev.3.00 Oct 23, 2006 page 3 of 70
REJ09B0178-0300
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions
(VCC = 4.1 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter Unit
Power source voltage
Limits
f(XIN) =
6 MHz
VCC
VSS
VREF
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured a term of 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured a term of 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5.5
VCC
VCC
VCC
VCC
3.6
0.3 VCC
0.8
0.2 VCC
0.8
0.16VCC
–80
80
60
–40
40
30
–10
10
30
–5
5
15
6
Max.
Power source voltage
Analog reference voltage
“H” input voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“H” input voltage (TTL input level selected) P10, P12, P13, P36, P37
“H” input voltage RESET, XIN
“H” input voltage D+, D-
“L” input voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” input voltage (TTL input level selected) P10, P12, P13, P36, P37
“L” input voltage RESET, CNVSS
“L” input voltage D+, D-
“L” input voltage XIN
“H” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” total peak output current (Note 1) P30–P36
“H” total average output current (Note 1) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” total average output current (Note 1) P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” total average output current (Note 1) P30–P36
“H” peak output current (Note 2) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” peak output current (Note 2) P00–P07, P10–P16, P20–P27,
P37 , P40, P41
“L” peak output current (Note 2) P30–P36
“H” average output current (Note 3) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” average output current (Note 3) P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” average output current (Note 3) P30–P36
Oscillation frequency (Note 4) VCC = 4.1 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Typ.
5.0
0
4.1
2.0
0.8 VCC
2.0
0.8 VCC
2.0
0
0
0
0
0
Min.
APPENDIX
7534 Group 3.1 Electrical characteristics
Rev.3.00 Oct 23, 2006 page 4 of 70
REJ09B0178-0300
3.1.3 Electrical characteristics
Table 3.1.3 Electrical characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits
IOH = –5 mA
VCC = 4.1 to 5.5 V
IOH = –1.0 mA
VCC = 4.1 to 5.5 V
VCC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, D-
Pull-up through 1.5kΩ
±5 % by USBVREFOUT
for D- (Ta = 0 to 70 °C)
IOL = 5 mA
VCC = 4.1 to 5.5 V
IOL = 1.5 mA
VCC = 4.1 to 5.5 V
VCC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, D-
Pull-up through 1.5kΩ
±5 % by USBVREFOUT
for D-(Ta = 0 to 70 °C)
IOL = 15 mA
VCC = 4.1 to 5.5 V
IOL = 1.5 mA
VCC = 4.1 to 5.5 V
VI = VCC
(Pin floating. Pull-up
transistors “off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull-up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
(Pull-up transistors“on”)
Test conditions
VCC–1.5
VCC–1.0
2.8
“H” output voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41 (Note 1)
“H” output voltage D+, D-
“L” output voltage P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” output voltage D+, D-
“L” output voltage P30–P36
Hysteresis D+, D-
Hysteresis CNTR0, INT0, INT1 (Note 2),
P00–P07(Note 3)
Hysteresis RXD, SCLK, SDATA (Note 2)
Hysteresis RESET
“H” input current P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“H” input current RESET
“H” input current XIN
“L” input current P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” input current RESET, CNVSS
“L” input current XIN
“L” input current P00–P07, P30–P37
RAM hold voltage
V
V
VOH
VOH 3.6 V
VOL
0.3
1.5 V
V
0.3 V
2.0
0.3 V
V
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIL
IIH
IIL
IIL
IIL
VRAM When clock stopped
0.5
0.5
0.4 V
V
V
4
–4
–0.2
5.0
5.0
–5.0
–5.0
–0.5
µA
µA
µA
µA
µA
µA
mA
2.0 5.5 V
Note 1:P11 is measured when the P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2:RXD, SCLK, SDATA, INT0 and INT1 have hystereses only when bits 0, 1 and 2 of the port P1P3 control register are set to “0” (CMOS
level).
3:It is available only when operating key-on wake-up.
Unit
VT+–VT– 0.15 V
7534 Group
APPENDIX
3.1 Electrical characteristics
Rev.3.00 Oct 23, 2006 page 5 of 70
REJ09B0178-0300
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source input current
A/D port input current
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
VCC = 4.1 to 5.5 V
Ta = 25 °C
VCC = 4.1 to 5.5 V
Ta = 25 °C
0520
LSB
LSB
Bits
±0.9
±3
10
3.1.4 A/D converter characteristics
Table 3.1.5 A/D Converter characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
mV
5105
50
30
5115 5125 mV
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
VREF = 5.0 V
122
200
55
150
tc(XIN)
kΩ
5.0 µA
µA
VREF = 3.0 V 120
70
VCC = VREF = 5.12 V
VCC = VREF = 5.12 V
Fig. 3.1.1 Power source current measurement circuit in USB
mode at oscillation stop
Table 3.1.4 Electrical characteristics (2) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
ICC Power source current 6
1.6
0.8
0.1
10 mA
mA
mA
Double-speed mode, f(XIN) = 6 MHz,
Output transistors “off”
f(XIN) = 6 MHz, (in WIT state)
Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 6 MHz, VCC = 5 V
All oscillation stopped (in STP state)
Output transistors “off”
VCC = 4.4 V to 5.25 V
Oscillation stopped in USB mode
USB (SUSPEND), (pull-up resistor
output included) (Fig. 3.1.1)
Ta = 25 °C
Ta = 85 °C 1.0
10 µA
µA
Ta = 0 to 70 °C 300 µA
Min. Typ. Max.
Symbol Parameter Limits
Test conditions Unit
3.2
V
CC
I
CC
V
CC
V
SS
USBV
REFOUT
D-
1.5 kΩ
15 kΩ
I
OUT
I
OUT
is included to this ratings.
APPENDIX
7534 Group 3.1 Electrical characteristics
Rev.3.00 Oct 23, 2006 page 6 of 70
REJ09B0178-0300
3.1.5 Timing requirements
Table 3.1.6 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SDATA–SCLK)
th(SCLK–SDATA)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1 input “H” pulse width
CNTR0, INT0, INT1 input “L” pulse width
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
15
166
70
70
200
80
80
1000
400
400
200
200
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.1.6 Switching characteristics
Table 3.1.7 Switching characteristics (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
tWH(SCLK)
tWL(SCLK)
td(SCLK–SDATA)
tv(SCLK–SDATA)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
tr(D+), tr(D-)
tf(D+), tf(D-)
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
USB output rising time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
4.4 to 5.25 V
USB output falling time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
4.4 to 5.25 V
10
10
150
150
75
75
Notes: XOUT pin is excluded.
Fig. 3.1.2 Output switching characteristics measurement circuit
tC(SCLK)/2–30
tC(SCLK)/2–30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140
30
30
30
30
300
300
100 pF
Measured
output pin
CMOS output
7534 Group
APPENDIX
3.1 Electrical characteristics
Rev.3.00 Oct 23, 2006 page 7 of 70
REJ09B0178-0300
Fig. 3.1.3 Timing chart
0.2VCC
td(SCLK-SDATA)
tf
0.2VCC
0.8VCC
0.8VCC
tr
tsu(SDATA-SCLK)th(SCLK-SDATA)
tv(SCLK-SDATA)
tC(SCLK)
tWL(SCLK) tWH(SCLK)
SDATA(at receive)
SCLK
0.2VCC
tWL(XIN)
0.8VCC
tWH(XIN)tC(XIN)
XIN
0.2VCC 0.8VCC
tW(RESET)
RESET
0.2VCC
tWL(CNTR)
0.8VCC
tWH(CNTR)
tC(CNTR)
0.2VCC
tWL(INT)
0.8VCC
tWH(INT)
SDATA(at transmit)
INT0/INT1
CNTR0
0.1V0H
D+, D-
tf
0.9V0H
tr
APPENDIX
7534 Group 3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 8 of 70
REJ09B0178-0300
0.0
0.5
1.0
1.5
2.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
3.2 Typical characteristics
3.2.1 Power source current characteristic example (ICC-VCC characteristic)
Fig. 3.2.1 ICC-VCC characteristic example (in double-speed mode)
Fig. 3.2.2 ICC-VCC characteristic example (at WIT instruction execution)
Measuring condition: Typical sample, Ta = 25 °C, ceramic oscillation, when operating system in double-speed
mode (A/D conversion not executed)
f(XIN) = 6 MHz
Power source voltage VCC [V]
Power source current I
CC
[mA]
Measuring condition: Typical sample, Ta = 25 °C, ceramic oscillation, At WIT instruction execution (at wait)
f(XIN)=6 MHz
Power source voltage VCC [V]
Power source current I
CC
[mA]
7534 Group
APPENDIX
3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 9 of 70
REJ09B0178-0300
0
5
10
15
20
25
30
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.0
0.3
0.6
0.9
1.2
1.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Fig. 3.2.3 ICC-VCC characteristic example (At STP instruction execution, Ta = 25 °C)
Fig. 3.2.4 ICC-VCC characteristic example (At STP instruction execution, Ta = 85 °C)
Measuring condition: At STP instruction execution (at stop), Typical sample, Ta = 25 °C
Power source voltage VCC [V]
Power source current I
CC
[nA]
Power source voltage VCC [V]
Power source current I
CC
[nA]
Measuring condition: At STP instruction execution (at stop), Typical sample, Ta = 85 °C
APPENDIX
7534 Group 3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 10 of 70
REJ09B0178-0300
Fig. 3.2.5 ICC-VCC characteristic example (at USB suspend, Ta = 25 °C)
Power source voltage VCC [V]
Power source current I
CC
[mA]
Measuring condition: A/D conversion executed/not executed (f(XIN) = 6MHz, in double-speed mode),
Typical sample, Ta = 25 °C, At ceramic oscillation
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
During A/D conversion
During not A/D conversion
Fig. 3.2.6 ICC-VCC characteristic example (A/D conversion executed/not executed, f(XIN) = 6MHz, in double-
speed mode)
Power source current I
CC
[µA]
Power source voltage VCC [V]
Measuring condition: At STP instruction execution (at USB suspend)
(output current from USBVREFOUT pin included)
Typical sample, Ta = 25 °C
USBVREFOUT = 3.29 V
200
210
220
230
240
250
260
270
4.0 4.5 5.0 5.5
7534 Group
APPENDIX
3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 11 of 70
REJ09B0178-0300
-40
-30
-20
-10
00.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
3.2.2 VOH-IOH characteristic example
Fig. 3.2.7 VOH-IOH characteristic example of P-channel (Ta = 25 °C): normal port
Fig. 3.2.8 VOH-IOH characteristic example of P-channel (Ta = 85 °C): normal port
Measuring condition: Ta = 25 °C, IOH–VOH characteristics of P-channel (normal port)
(same charactersistics pins: P00–P07, P10–P16, P20–P27, P30–P37, P40, P41)
“H” output current I
OH
[mA]
Measuring condition: Ta = 85 °C, IOH–VOH characteristics of P-channel (normal port)
(same charactersistics pins: P00–P07, P10–P16, P20–P27, P30–P37, P40, P41)
VCC = 5.0 V
“H” output voltage VOH [V]
“H” output current I
OH
[mA]
-40
-30
-20
-10
00.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
“H” output voltage VOH [V]
VCC = 5.0 V
APPENDIX
7534 Group 3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 12 of 70
REJ09B0178-0300
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
10
20
30
40
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Fig. 3.2.9 VOL-IOL characteristic example of N-channel (Ta = 25 °C): Normal port
Fig. 3.2.10 VOL-IOL characteristic example of N-channel (Ta = 85 °C): Normal port
Measuring condition: Ta = 25 °C, VOL–IOL characteristics of N-channel (normal port)
(same charactersistics pins: P00–P07, P10–P16, P20–P27, P37, P40, P41)
VCC = 5.0 V
“L” output voltage VOL [V]
“L” output current I
OL
[mA]
VCC = 3.0 V
Measuring condition: Ta = 85 °C, VOL–IOL characteristics of N-channel (normal port)
(same charactersistics pins: P00–P07, P10–P16, P20–P27, P37, P40, P41)
VCC = 5.0 V
“L” output voltage VOL [V]
“L” output current I
OL
[mA]
VCC = 3.0 V
7534 Group
APPENDIX
3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 13 of 70
REJ09B0178-0300
0
20
40
60
80
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
20
40
60
80
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Fig. 3.2.11 VOL-IOL characteristic example of N-channel (Ta = 25 °C): LED drive port
Fig. 3.2.12 VOL-IOL characteristic example N-channel (Ta = 85 °C): LED drive port
Measuring condition: Ta = 25 °C, VOL–IOL characteristics of N-channel (LED drive port)
(same charactersistics pins: P30–P36)
VCC = 5.0 V
“L” output voltage VOL [V]
“L” output current I
OL
[mA]
VCC = 3.0 V
Measuring condition: Ta = 85 °C, VOL–IOL characteristics of N-channel (LED drive port)
(same charactersistics pins: P30–P36)
VCC = 5.0 V
“L” output voltage VOL [V]
“L” output current I
OL
[mA]
VCC = 3.0 V
APPENDIX
7534 Group 3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 14 of 70
REJ09B0178-0300
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Fig. 3.2.13 “L” input current of port at pull-up transistor connected
Measuring condition: “L” input current of port at pull-up transistor connected
(same charactersistics pins: P00–P07, P30–P37)
Ta = 85 °C
Ta = –25 °C
Power source voltage VCC [V]
“L” input current I
IL
[µA]
Ta = 25 °C
7534 Group
APPENDIX
3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 15 of 70
REJ09B0178-0300
3.2.3 A/D conversion typical characteristics example
(1) Definition of A/D conversion accuracy
The A/D conversion accuracy is defined below (refer to Fig. 3.2.14).
●Relative accuracy
➀ Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D conversion output data changes from
“0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from
“1023” to “1022.”
➂ Non-linearity error
This means a deviation from the line between VOT and VFST of a converted value between VOT and
VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value
between VOT and VFST by 1 LSB of the 1 LSB at the relative accuracy.
●Absolute accuracy
This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion
characteristics.
VREF
1024
Fig. 3.2.14 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
• 1 LSB at relative accuracy →(V)
• 1 LSB at absolute accuracy →(V)
VFST – VOT
1022
A
n
a
l
o
g
v
o
l
t
a
g
eV
RE
F
V
102
2
V
n
V
1
V
0
Z
e
r
o
t
r
a
n
s
i
t
i
o
n
v
o
l
t
a
g
e
(
V
0
T
)
F
u
l
l
-
s
c
a
l
e
t
r
a
n
s
i
t
i
o
n
v
o
l
t
a
g
e
(
V
F
S
T
)
Non-linearity error=
Actual A/D conversion
characteristics
V
n+1
n+1
n
1
0
2
2
1
0
2
3
1
0
I
d
e
a
l
l
i
n
e
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
b
e
t
w
e
e
n
V
0
t
o
V
1
0
2
2
O
u
t
p
u
t
d
a
t
a
b
a
a
:
1
L
S
B
a
t
r
e
l
a
t
i
v
e
a
c
c
u
r
a
c
y
b
:
V
n
+
1
-
V
n
c
:
D
i
f
f
e
r
e
n
c
e
b
e
t
w
e
e
n
t
h
e
i
d
e
a
l
V
n
a
n
d
a
c
t
u
a
l
V
n
Differential non-linearity error= b
-
a
a
[
L
S
B
]
c
c
a
[LSB]
APPENDIX
7534 Group 3.2 Typical characteristics
Rev.3.00 Oct 23, 2006 page 16 of 70
REJ09B0178-0300
•VCC = 5 [V]
•VREF = 5 [V]
•XIN = 6 [MHz]
•Temp. = 25 [°C]
•CPU mode = double-speed mode
•Zero transition voltage: 6.714 mV
•Full-scale transition voltage: 4994.812 mV
•Differential non-linearity error: 1.373 mV (0.281 LSB)
•Non-linearity error: –5.201 mV (–1.066 LSB)
M37534M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT
-7.32
-4.88
-2.44
0.00
2.44
4.88
7.32
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
STEP
1LSB WIDTH
ERROR
-7.32
-4.88
-2.44
0.00
2.44
4.88
7.32
256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512
STEP
-7.32
-4.88
-2.44
0.00
2.44
4.88
7.32
512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768
STEP
-7.32
-4.88
-2.44
0.00
2.44
4.88
7.32
768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024
STEP
Fig. 3.2.15 A/D conversion typical characteristic example
7534 Group
APPENDIX
3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 17 of 70
REJ09B0178-0300
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following
sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
(2) Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register
immediately after this bit is set to “0” by using a data transfer instruction, execute one or more
instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
● Reason
If the BBC or BBS instruction is executed
immediately after an interrupt request bit of
an interrupt request register is cleared to
“0”, the value of the interrupt request bit
before being cleared to “0” is read.
Fig. 3.3.2 Sequence of check of interrupt request bit
Fig. 3.3.1 Sequence of switch the detection edge
● Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
APPENDIX
7534 Group 3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 18 of 70
REJ09B0178-0300
(3) Structure of interrupt control register 1
Fix the bit 7 of the interrupt control register 1 to “0”. Figure 3.3.3 shows the structure of the interrupt
control register 1.
Fig. 3.3.3 Structure of interrupt control register 1
3.3.2 Notes on serial I/O
(1) Handling of serial I/O1 clear
When serial I/O1 is set again or the transmit/receive operation is stopped/restarted while serial I/O1
is operating, clear the serial I/O1 as shown in Figure 3.3.4.
Fig. 3.3.4 Sequence of clearing serial I/O
0
b7 b0
Interrupt control register 1 (address: 003E16)
Interrupt enable bit
Not used (fix this bit to “0”)
→Set again (Note)
○○ ○○
• Serial I/O1 enabled
• Serial I/O1 cleared
• Serial I/O1 disabled
• Serial I/O1 register set again
• Serial I/O1 enabled
Handling of clear serial I/O1
Note: When the contents of register is not changed, setting again is not necessary.
(2) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) Writing transmit data
When an external clock is used as the synchronous clock for the clock synchronous serial I/O, write
the transmit data to the transmit buffer register (serial I/O shift register) at “H” of the transfer clock
input level.
SIO1CON (address 1A16) bit 7, bit 6 ← 102
SIO1CON (address 1A16) bit 7, bit 6 ← 112
SIO1CON (address 1A16) bit 7, bit 6 ← 002
UARTCON (address 1B16)
BRG (address 1C16)
SIO1CON (address 1A16) ← 10✕✕✕✕✕✕2
Set again (Note)
7534 Group
APPENDIX
3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 19 of 70
REJ09B0178-0300
(4) Serial I/O2 transmit/receive shift completion flag
•The transmit/receive shift completion flag of the serial I/O2 control register is set to “1” after completing
transmit/receive shift. In order to set this flag to “0”, write data (dummy data at reception) to the
serial I/O2 register by program.
•Bit 7 of the serial I/O2 control register is set to “1” a half cycle (of the shift clock) earlier than
completion of shift operation. Accordingly, when using this bit to confirm shift completion, a half
cycle or more of the shift clock must pass after confirming that this bit is set to “1”, before performing
read/write to the serial I/O2 register.
3.3.3 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01
µ
F to 1
µ
F. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more
• Do not execute the STP instruction
(3) Method to stabilize A/D Converter
Method to stabilize A/D Converter is described below.
(a) A/D conversion accuracy could be affected for Bus Powered*1 USB devices, while the communicating.
Figure 3.3.5 shows the method to stabilize A/D conversion accuracy, inserting a capacitor between
Vref and VSS.
*1: Power supplied by USB VCC BUS.
(b) It is recommended for A/D accuracy to avoid converting while USB communication, and use
average value of several converted values.
Fig. 3.3.5 Method to stabilize A/D conversion accuracy
A
N0
t
o
A
N7
V
c
c
CNV
ss
1
µF
0
.
0
1
t
o
1
µF
Vref
V
s
s
1
t
o
1
0
kΩ
0
.
1
t
o
1
µF:
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r
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.
2
2
µF
7
5
3
4
G
r
o
u
p
1
.
5
kΩ
USBVREFOUT
D
-
APPENDIX
7534 Group 3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 20 of 70
REJ09B0178-0300
3.3.4 Notes on watchdog timer
The internal reset may not be generated correctly in the middle-speed mode, depending on the
underflow timing of the watchdog timer.
When using the watchdog timer, operate the MCU in any mode other than the middle-speed mode
(i.e., high-speed, low-speed or double-speed mode).
_____________
3.3.5 Notes on RESET pin
(1) Connecting capacitor
_____________
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
_____________
RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason _____________
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.6 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied current values:
• When setting as an input port : Fix its input level
•When setting as an output port : Prevent current from flowing out to external
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of a input port and an I/O port are “undefined”. This may cause power source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
7534 Group
APPENDIX
3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 21 of 70
REJ09B0178-0300
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
*2 bit managing instructions : SEB, and CLB instructions
3.3.7 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.8 Stack memory contents after PHP
instruction execution
PLP instruction execution
↓
NOP
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
Fig. 3.3.6 Initialization of processor status register
Fig. 3.3.7 Sequence of PLP instruction execution
(S)
(S)+1 Stored PS
APPENDIX
7534 Group 3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 22 of 70
REJ09B0178-0300
(2) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
(3) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
3.3.8 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank), its built-in PROM can be read or programmed
with a general-purpose PROM programmer using a special programming adapter.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.9 before actual use are recommended.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.9 Status flag at decimal calculations
Fig. 3.3.10 Programming and testing of One Time PROM version
Programming with PROM programmer
Screening (Caution)
(Leave at 150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution:The screening temperature is far higher than the
storage temperature. Never expose to 150 °C
exceeding 100 hours.
7534 Group
APPENDIX
3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 23 of 70
REJ09B0178-0300
3.3.9 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapters
M37534E4GP (One Time PROM version shipped in blank)
M37534E8SP (One Time PROM version shipped in blank)
M37534E8FP (One Time PROM version shipped in blank)
PCA7435GPG03
PCA7435SP, PCA7435SPG02
PCA7435FP, PCA7435FPG02
Programming adapter
Microcomputer
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions
of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming /reading. Take care not to apply 21 V
to VPP pin (is also used as the CNVSS pin), or the product may be permanently damaged.
• Programming voltage: 12.5 V
• Setting of PROM programmer switch: refer to Table 3.3.2.
Product name format PROM programmer
start address
Address 0C08016 (Note 2)
PROM programmer
end address
M37534E4GP
M37534E8SP
M37534E8FP
Table 3.3.2 PROM programmer address setting
Address 0FFFD16 (Note 2)
Notes 1: Addersses E08016 to FFFD16 in the built-in PROM corresponds to addresses 0E08016 to 0FFFD16
in the PROM programmer.
2: Addersses C08016 to FFFD16 in the built-in PROM corresponds to addresses 0C08016 to 0FFFD16
in the PROM programmer.
Address 0E08016 (Note 1) Address 0FFFD16 (Note 1)
APPENDIX
7534 Group 3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 24 of 70
REJ09B0178-0300
3.3.10 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. As for pins
whose potential affects to operation modes such as pins CNVSS, INT or others, select the VCC pin
or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
7534 Group
APPENDIX
3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 25 of 70
REJ09B0178-0300
3.3.11 Notes on CPU mode register
(1) Switching method of CPU mode register after releasing reset
Switch the CPU mode register (CPUM) at the head of program after releasing reset in the following
method.
Fig. 3.3.11 Switching method of CPU mode register
3.3.12 Notes on using 32-pin version
• Do not change the P35, P36 pull-up control bit of the pull-up control register from the initial value “1”.
• Do not write to “1” to the serial I/O1 or INT1 interrupt selection bit of the interrupt edge selection register.
3.3.13 Electric characteristic differences among mask ROM and One TIme PROM version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation
among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing
processes.
When manufacturing an application system with One Time PROM version and then switching to use of the
mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version.
3.3.14 Note on power source voltage
When the power source voltage value of a microcomputer is less than the value which is indicated as the
recommended operating conditions, the microcomputer does not operate normally and may perform unstable
operation.
In a system where the power source voltage drops slowly when the power source voltage drops or the
power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended
operating conditions and design a system not to cause errors to the system by this unstable operation.
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APPENDIX
7534 Group 3.3 Notes on use
Rev.3.00 Oct 23, 2006 page 26 of 70
REJ09B0178-0300
3.3.15 USB communication
• In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.
• When USB suspend mode with TTL level on P10, P12, P13 input level selection bit (bit 3 of address 1716)
set to “1”, suspend current as ICC might be greater than 300 µA as a spec.
[Countermeasure]
There are two countermeasures by software to avoid it as follows.
(1) Change from TTL input level to CMOS input level for P10, P12, P13 port input.
(2) Change from TTL input level to CMOS input level before STP instruction in suspend routine;
then after RESUME or Remote wake up interrupt, return to TTL input level from CMOS input level.
That is shown in Figure 3.3.12.
Fig. 3.3.12 Countermeasure (2) by software
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lev e l fo r P10, P12, P13 input level.
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7534 Group
APPENDIX
3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 27 of 70
REJ09B0178-0300
Fig. 3.4.2 Wiring for the RESET pin
3.4 Countermeasures against noise
3.4.1 Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
DIP
SDIP
SOP
QFP
RESET
Reset
circuit
Noise
V
SS
V
SS
Reset
circuit
V
SS
RESET
V
SS
N.G.
O.K.
APPENDIX
7534 Group 3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 28 of 70
REJ09B0178-0300
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected
to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Fig. 3.4.3 Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect the CNVSS pin to the VSS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Fig. 3.4.4 Wiring for CNVSS pin
Noise
X
IN
X
OUT
V
SS
X
IN
X
OUT
V
SS
N.G. O.K.
Noise
CNVSS
VSS
CNVSS
VSS
N.G. O.K.
7534 Group
APPENDIX
3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 29 of 70
REJ09B0178-0300
(5) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The VPP pin of the One Time PROM is the power source input pin for the built-in PROM. When
programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current
for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin,
abnormal instruction codes or data are read from the built-in PROM, which may cause a program
runaway.
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM
3.4.2 Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 1.0
µ
F bypass capacitor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line
CNV
SS
/V
PP
V
SS
In the shortest
distance
Approximately
5kΩ
V
SS
V
CC
AA
AA
AA
AA
AA
AA
V
SS
V
CC
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
N.G. O.K.
APPENDIX
7534 Group 3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 30 of 70
REJ09B0178-0300
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the VSS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far from
the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily.
This long wiring functions as an antenna which feeds noise into the microcomputer, which causes
noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Fig. 3.4.8 Wiring for a large current signal line
Analog
input pin
VSS
Noise
Thermistor
Microcomputer
N.G. O.K.
(Note)
Note : The resistor is used for dividing
resistance with a thermistor.
XIN
XOUT
VSS
M
Microcomputer
Mutual inductance
Large
current
GND
7534 Group
APPENDIX
3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 31 of 70
REJ09B0178-0300
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
Fig. 3.4.9 Wiring of signal lines where potential levels change frequently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other VSS patterns.
Fig. 3.4.10 VSS pattern on the underside of an oscillator
X
IN
X
OUT
V
SS
CNTR
Do not cross
N.G.
AAA
AAA
AAA
AAA
A
A
A
AAA
A
A
A
A
A
AA
AA
XIN
XOUT
VSS
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
Separate the VSS line for oscillation from other VSS lines
APPENDIX
7534 Group 3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 32 of 70
REJ09B0178-0300
Fig. 3.4.11 Setup for I/O ports
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
Direction register
Port latch
Data bus
I/O port
pins
Noise
Noise
N.G.
O.K.
7534 Group
APPENDIX
3.4 Countermeasures against noise
Rev.3.00 Oct 23, 2006 page 33 of 70
REJ09B0178-0300
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
Fig. 3.4.12 Watchdog timer by software
Main routine
(SWDT)← N
CLI
Main processing
(SWDT)
Interrupt processing
routine errors
N
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
(SWDT)
Main routine
errors
>0
≤0RTI
Return
=N?
≤0?
≠N
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 34 of 70
REJ09B0178-0300
3.5 List of registers
Fig. 3.5.1 Structure of Port Pi (i = 0 to 4)
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
B Function At reset RW
0
1
2
3
4
5
6
7
Name
Port Pi
0
Port Pi
1
Port Pi
2
Port Pi
3
Port Pi
4
Port Pi
5
Port Pi
6
Port Pi
7
In output mode
Write
Read
●
Port latch
In input mode
Write : Port latch
Read : Value of pins
●
Port Pi (Pi) (i = 0 to 4) [Address : 00
16
, 02
16
, 04
16
, 06
16
, 08
16
]
?
?
?
?
?
?
?
?
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P1
7
, P4
2
–P4
7
• 36-pin version: Ports P1
5
–P1
7
, P3
6
, P4
0
–P4
7
• 32-pin version: Ports P1
5
–P1
7
, P2
6
, P2
7
, P3
5
–P3
7
, P4
0
–P4
7
Fig. 3.5.2 Structure of Port Pi direction register (i = 0 to 4)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name
Port Pi
direction register
0
0
0
0
0
0
0
0
Port Pi direction register (PiD) (i = 0 to 4) [Address : 01
16
, 03
16
, 05
16
, 07
16
, 09
16
]
0 : Port Pi
0
input mode
1 : Port Pi
0
output mode
0 : Port Pi
1
input mode
1 : Port Pi
1
output mode
0 : Port Pi
2
input mode
1 : Port Pi
2
output mode
0 : Port Pi
3
input mode
1 : Port Pi
3
output mode
0 : Port Pi
4
input mode
1 : Port Pi
4
output mode
0 : Port Pi
5
input mode
1 : Port Pi
5
output mode
0 : Port Pi
6
input mode
1 : Port Pi
6
output mode
0 : Port Pi
7
input mode
1 : Port Pi
7
output mode
✕
✕
✕
✕
✕
✕
✕
✕
Note: The following ports do not exist, so that the corresponding bits are not used.
• 42-pin version: Ports P17, P42–P47
• 36-pin version: Ports P15–P17, P36, P40–P47
• 32-pin version: Ports P15–P17, P26, P27, P35–P37, P40–P47
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 35 of 70
REJ09B0178-0300
Fig. 3.5.3 Structure of Pull-up control register
Fig. 3.5.4 Structure of Port P1P3 control register
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name
P00 pull-up control bit
1
1
1
1
1
1
1
1
Pull-up control register (PULL) [Address : 16 16]
0 : Pull-up Off
1 : Pull-up On
Notes 1: Pins set to output are disconnected from the pull-up control.
2: • 36-pin version: P36 is not existed.
• 32-pin version: Not used.
3: 32-pin version: Not used.
P01 pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P02, P03 pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P04 – P07 pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P30 – P33 pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P34 pull-up control bit 0 : Pull-up Off
1 : Pull-up On
P35, P36 pull-up control bit
(Note 2)0 : Pull-up Off
1 : Pull-up On
P37 pull-up control bit
(Note 3)0 : Pull-up Off
1 : Pull-up On
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
P37/INT0 input level selection
bit (Note 1)
0
0
0
0
0
0
0
0
Port P1P3 control register (P1P3C) [Address : 17 16]
0 : CMOS level
1 : TTL level
P36/INT1 input level selection
bit (Note 2)
0 : CMOS level
1 : TTL level
P10, P12,P13 input level
selection bit 0 : CMOS level
1 : TTL level
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
✕
✕
✕
Notes 1: For the 32-pin version, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
2: For the 32-pin and 36-pin versions, nothing is allocated for this bit.
This is a write disabled bit.
When this bit is read out, the value is “0”.
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 36 of 70
REJ09B0178-0300
Fig. 3.5.5 Structure of Transmit/Receive buffer register
Fig. 3.5.6 Structure of UART status register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Transmit/Receive buffer
register (TB/RB) [Address : 18
16
]
The transmission data is written to or the receive data is read out
from this buffer register.
• At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
UART status register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 1
0
0
0
0
0
0
1
UART status register (UARTSTS) [Address : 19
16
]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
✕
✕
✕
✕
✕
✕
✕
✕
Transmit buffer empty flag
(TBE)
0 : (OE) ∪ (PE) ∪ (FE) = 0
1 : (OE) ∪ (PE) ∪ (FE) = 1
Overrun error flag (OE)
0 : Buffer full
1 : Buffer empty
Receive buffer full flag (RBF)
Transmit shift register shift
completion flag (TSC)
Parity error flag (PE)
Framing error flag (FE)
Summing error flag (SE)
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
0 : No error
1 : Framing error
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 37 of 70
REJ09B0178-0300
RxRDY SUME BSTFE PIDE CRCE FEOPE EOP TxRDY
EOP detection flag 0: Not detected
1: Detect
False EOP error flag 0: No error
1: False EOP error
CRC error flag 0: No error
1: CRC error
Setting condition of this flag to “1” is as follows;
• PID of DATA0 or DATA1 cannot be detected at data phase after OUT or SETUP
token
• ACK PID cannot be received at handshake phase during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when bit stuffing error occurs at data phase or handshake phase.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when any error of FEOPE, CRCE, PIDE, or BSTFE occurs.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when data is transferred from shift register to buffer by hardware.
This bit is cleared to “0” by reading from buffer.
Set/
Clear
Ena-
ble
CPU
RD CPU
WR H/W
RD H/W
WR
b7 b6 b5 b4 b3 b2 b1 b0
00000001
Initial value
USB status register (USBSTS) [Address 1916]
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble Set/
Clear
Set
Set
Set
Set
Set
Set
Clear
Clear
Clear
Clear
Clear
Clear
Transmit buffer
empty flag 0: Buffer full
1: Buffer empty
PID error flag 0: No error
1: PID error
Bit stuffing error flag 0: No error
1: Bit stuffing error
Summing error flag 0: No error
1: Summing error
Receive buffer full
flag 0: Buffer empty
1: Buffer full
This bit is set to “1” when data is transferred from buffer to shift register by hardware.
This bit is cleared to “0” by writing to buffer.
Setting condition of this flag to “1” is as follows;
• Normal EOP detected by hardware
• False EOP flag (FEOPE) set
• Time is out with EOP not detected at data phase or handshake phase
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when the phase is not completed normally.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when the CRC error occurs at the same timing of EOP detection
flag.
This bit is to “0” cleared by writing dummy to this register.
Fig. 3.5.7 Structure of USB status register
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 38 of 70
REJ09B0178-0300
Fig. 3.5.8 Structure of Serial I/O1 control register
Fig. 3.5.9 Structure of UART control register
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
1
0
0
0
0
0
0
Serial I/O1 control register (SIO1CON) [Address : 1A
16
]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”. ✕
0 : f(X
IN
)
1 : f(X
IN
)/4
BRG count source
selection bit (CSS)
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
Transmit interrupt
source selection bit (TIC)
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O1 enable bit
(SIOE)
Continuous transmit valid bit 0 : Continuous transmit invalid
1 : Continuous transmit valid
0 : Interrupt when transmit buffer
has emptied
1 : Interrupt when transmit shift
operation is completed
0 0 : I/O port
0 1 : Not available
1 0 : UART mode
1 1 : USB mode
b7 b6
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
1
UART control register (UARTCON) [Address : 1B 16]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “1”. ✕
✕
✕
UART control register
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Stop bit length selection
bit (STPS)
Parity selection bit
(PARS)
In output mode
0 : CMOS output
1 : N-channel open-drain
output
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : 1 stop bit
1 : 2 stop bits
0 : Even parity
1 : Odd parity
P11/TxD P-channel
output disable bit
(POFF)
1
1
0
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 39 of 70
REJ09B0178-0300
Fig. 3.5.10 Structure of Baud rate generator
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Baud rate generator (BRG) [Address : 1C
16
]
Set a count value of baud rate generator.
SQTGL CPU
RD CPU
WR H/W
RD H/W
WR
b7 b6 b5 b4 b3 b2 b1 b0
USB data toggle synchronization register (TRSYNC) [Address 1D
16
]
0Initial value Ena-
ble Clear Set
Sequence bit toggle
flag 0: No toggle
1: Sequence toggle
Setting condition of this flag to “1” is as follows;
• Setting of handshake for OUT token in EP0PID is ACK, toggle of data PID is
performed normally, and errors do not occur at data phase during OUT and
SETUP transaction.
• When ACK is received during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
Fig. 3.5.11 Structure of USB data toggle synchronization register
Endpoint
determination flag 0: Endpoint 0 interrupt
1: Endpoint 1 interrupt
This flag is set to “1” when IN token interrupt of endpoint 1 occurs.
This flag is cleared to “0” when IN token interrupt of endpoint 0 occurs.
Writing to this bit is invalid. Do not write “1” to bits 0 to 6.
RxEP
CPU
RD CPU
WR H/W
RD H/W
WR
b7 b6 b5 b4 b3 b2 b1 b0
0Initial value
USB interrupt source discrimination register 1 (USBIR1) [Address 1E
16
]
Ena-
ble Set/
Clear
Fig. 3.5.12 Structure of USB interrupt source discrimination register 1
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 40 of 70
REJ09B0178-0300
Fig. 3.5.13 Structure of USB interrupt source discrimination register 2
Suspend request flag 0: No request
1: Suspend request
Suspend request is set to “1” when system enters to state J for 3 ms or more.
Suspend request is cleared to “0” by writing dummy to this register.
RxPID OPID RSTRQ SPRQ
USB reset request
flag 0: No request
1: Reset request
USB reset request is set to “1” when the SE0 signal is input for 2.5 µs or more.
USB reset request is cleared to “0” when the SE0 signal is stopped.
Token PID
determination flag 0: SETUP interrupt
1: OUT interrupt
This flag is set to “1” during no SETUP transaction.
This flag is cleared to “0” when PID of SETUP is detected.
Token interrupt flag 0: No request
1: OUT/SETUP token request
This flag is set to “1” when OUT or SETUP interrupt occurs.
This flag is cleared to “0” after the end of transaction.
CPU
RD CPU
WR H/W
RD H/W
WR
USB interrupt source discrimination register 2 (USBIR2) [Address 1F
16
]
b7 b6 b5 b4 b3 b2 b1 b0
0Initial value 0 01
Ena-
ble SetClear
Ena-
ble
Ena-
ble
Ena-
ble Set/
Clear
Set/
Clear
Set/
Clear
Endpoint 1 enable 0: Endpoint 1 invalid
1: Endpoint 1 valid
USBE TKNE EP1ERSME
USB reset interrupt
enable 0:USB reset invalid
1:USB reset valid
This flag is invalid in suspend mode (USB reset is always valid in suspend mode).
Resume interrupt
enable 0: Resumue invalid
1: Resume valid
Token interrupt
enable 0:Token invalid
1:Token valid
RSTE
USB enable flag 0:USB invalid
1:USB valid
The internal state can be initialized by clearing this flag to “0”.
The initial values of registers are as follows;
• USB status register [address 19
16
] = (01
16
)
• USB data toggle synchronization register [address 1D
16
] = (7F
16
)
• USB interrupt source discrimination register 1 [address 1E
16
] = (7F
16
)
• Bits 7, 6 and 2 of USB interrupt source discrimination register 2 [address 1F
16
]
= (00xxx0xx
2
)
CPU
RD CPU
WR H/W
RD H/W
WR
b7 b6 b5 b4 b3 b2 b1 b0
0Initial value 0 0 0 0
USB interrupt control register (USBICON) [Address 20 16]
Ena-
ble Set/
Clear
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Set/
Clear
Set/
Clear
Set/
Clear
Set/
Clear
Use
Use
Use
Use
Use
Fig. 3.5.14 Structure of USB interrupt control register
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 41 of 70
REJ09B0178-0300
–Set the number of data byte for
transmitting with endpoint 0
EP0BYTE CPU
RD CPU
WR H/W
RD H/W
WR
b7 b6 b5 b4 b3 b2 b1 b0
USB transmit data byte number set register 0 (EP0BYTE) [Address 21 16]
Initial value
0000 0000
Ena-
ble Set/
Clear Use
Fig. 3.5.15 Structure of USB transmit data byte number set register 0
–Set the number of data byte for
transmitting with endpoint 1
EP1BYTE
CPU
RD CPU
WR H/W
RD H/W
WR
Initial value
b7 b6 b5 b4 b3 b2 b1 b0
0000 0000
USB transmit data byte number set register 1 (EP1BYTE) [Address 22
16]
Ena-
ble Set/
Clear Use
Fig. 3.5.16 Structure of USB transmit data byte number set register 1
0Endpoint 0 enable
flag 0: Endpoint 0 invalid
1: Endpoint 0 valid
Unexpected IN or OUT transaction can be ignored by clearing to this flag to “0”.
(SETUP transaction cannot be ignored, it is always valid.)
DPID0 0000
SPID0I APID0 SPID0O EP0E
Endpoint 0 PID selection
flag (OUT STALL)
DPID0 and SPID0I are used to control the response for IN token.
DPID0 is used with the token interrupt enable flag (TKNE).
DPID0 is cleared to “0” automatically by hardware when ACK is received.
SPID0O and APID0 are used to control the response for OUT token.
When DPID0 is changed during token packet, the changed value is valid after end
of token.
Endpoint 0 PID selection
flag (OUT ACK)
Endpoint 0 PID selection
flag (IN STALL)
Endpoint 0 PID selection
flag (IN DATA0/1)
CPU
RD CPU
WR H/W
RD H/W
WR
1✕✕✕: IN token interrupt of DATA 0/1 is valid
01✕✕: STALL handshake is valid for IN token
00✕✕: NAK handshake is valid for IN token
✕✕✕1: STALL handshake is valid for OUT
token
✕✕10: ACK handshake is valid for OUT token
✕✕00: NAK handshake is valid for OUT token
Initial value
b7 b6 b5 b4 b3 b2 b1 b0
✕: it can be set to 0 or 1.
USB PID control register 0 (EP0PID) [Address 23
16
]
Ena-
ble Set/
Clear Use
Set/
Clear Use
Set/
Clear Use
Set/
Clear Use
Set/
Clear Use Clear
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Fig. 3.5.17 Structure of USB PID control register 0
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 42 of 70
REJ09B0178-0300
Fig. 3.5.18 Structure of USB PID control register 1
0
DPID1
0
SPID1
1✕: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NAK handshake is valid for IN token
DPID1 and SPID1 are used to control the response for IN token.
DPID1 is used with the token interrupt enable flag (TKNE).
DPID1 is cleared to “0” automatically by hardware when ACK is received.
CPU
RD CPU
WR H/W
RD H/W
WR
Initial value
b7 b6 b5 b4 b3 b2 b1 b0
✕: it can be set to 0 or 1.
USB PID control register 1 (EP1PID) [Address 24
16]
Set/
Clear Use
Set/
Clear Use Clear
Endpoint 1 PID selection
flag (IN STALL)
Endpoint 1 PID selection
flag (IN DATA0/1)
Enable
Enable
USBA
0000000
b7 b6 b5 b4 b3 b2 b1 b0
CPU
RD CPU
WR H/W
RD H/W
WR
USB address register (USBA) [Address 25
16
]
Initial value
–Set/
Clear Use
Set an address allocated by the
USB host
Fig. 3.5.19 Structure of USB address register
As sequence bit of endpoint 1 is
initialized.
INISQ1
Dummy
Sequence is initialized by writing dummy.
b7 b6 b5 b4 b3 b2 b1 b0
CPU
RD CPU
WR H/W
RD H/W
WR
–
Initial value
USB sequence bit initialization register (INISQ1) [Address 26
16]
✕✕✕✕✕✕✕✕
Fig. 3.5.20 Structure of USB sequence bit initialization register
0
0: Output off
1: Output on
WKUP UVOE
Remote wake up
request flag 0: No request
1:Remote wake up request
Remote wake up request (K output) can be set by setting this flag to “1”.
This flag is cleaed to “0” automatically after 10 ms from remote wake up request.
Clear
USBV
REFOUT
output
valid flag
0
USB control register (USBCON) [Address 27
16
]
b7 b6 b5 b4 b3 b2 b1 b0
CPU
RD CPU
WR H/W
RD H/W
WR
Initial value
Set Use
Set/
Clear Use
Fig. 3.5.21 Structure of USB control register
Refer to “Figure 2.4.6 Description of register structure” for registers relevant to USB.
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 43 of 70
REJ09B0178-0300
Fig. 3.5.23 Structure of Timer 1
Fig. 3.5.22 Structure of Prescaler 12, Prescaler X
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
Prescaler 12 (PRE12) [Address : 28 16]
Prescaler X (PREX) [Address : 2C 16]
•Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres-
ponding prescaler is read out.
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
Timer 1 (T1) [Address : 2916]
•Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
latch at the same time.
•When this register is read out, the timer 1’s count value is read
out.
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 44 of 70
REJ09B0178-0300
Fig. 3.5.24 Structure of Timer 2
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
Timer 2 (T2) [Address : 2A
16
]
•Set a count value of timer 2.
•The value set in this register is written to both timer 2 and timer 2
latch at the same time.
•When this register is read out, the timer 2’s count value is read
out.
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 45 of 70
REJ09B0178-0300
Fig. 3.5.25 Structure of Timer X mode register
Timer X operation modes
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
CNTR0 active edge switch bit (bit 2 of address 2B16) contents
“0” CNTR0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR0 interrupt request occurrence: Rising edge
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
CNTR0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR0 interrupt request occurrence: Rising edge
“0” Timer X: Rising edge count
CNTR0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR0 interrupt request occurrence: Rising edge
“0” Timer X: “H” level width measurement
CNTR0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR0 interrupt request occurrence: Rising edge
Table 3.5.1 CNTR0 active edge switch bit function
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
2
3
4
5
6
7
Name
0
0
0
0
Timer X mode register (TM) [Address : 2B
16
]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
✕
Timer X mode register
0
0
0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement
mode
b1 b0
10
Timer X operating mode bits
CNTR
0
active edge switch bit The function depends on the
operating mode.
(Refer to Table 3.5.1)
Timer X count stop bit 0 : Count start
1 : Count stop ✕
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 46 of 70
REJ09B0178-0300
Fig. 3.5.26 Structure of Timer X
Fig. 3.5.27 Structure of Timer count source set register
Timer X
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
Timer X (TX) [Address : 2D16]
•Set a count value of timer X.
•The value set in this register is written to both timer X and timer X
latch at the same time.
•When this register is read out, the timer X’s count value is read
out.
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
Timer count source set register (TCSS) [Address : 2E
16
]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
✕
✕
✕
Timer count source set register
Timer X count source
selection bit (Note)0 : f(X
IN
) / 16
1 : f(X
IN
) / 2
0
0
0
✕
✕
✕
✕
Note: To switch the timer X count source selection bit, stop the timer X count
operation before do that.
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 47 of 70
REJ09B0178-0300
Fig. 3.5.28 Structure of Serial I/O2 control register
Fig. 3.5.29 Structure of Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
Serial I/O2 control register (SIO2CON) [Address : 30
16
]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
✕
Serial I/O2 control register
0
0
Note: When using it as a S
DATA
input, set the port P1
3
direction register bit to “0”.
0 : LSB first
1 : MSB first
0 0 0 : f(X
IN
)/8
0 0 1 : f(X
IN
)/16
0 1 0 : f(X
IN
)/32
0 1 1 : f(X
IN
)/64
1 1 0 : f(X
IN
)/128
1 1 1 : f(X
IN
)/256
Internal synchronous
clock selection bits
Transfer direction selection bit
b2 b1 b0
S
DATA
pin selection bit
(Note)0 : I/O port / S
DATA
input
1 : S
DATA
output
S
CLK
pin selection bit 0 : External clock (S
CLK
is input)
1 : Internal clock (S
CLK
is output)
Transmit / receive shift
completion flag 0 : shift in progress
1 : shift completed
0
0
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Serial I/O2 register (SIO2) [Address : 31 16]
A shift register for serial transmission and reception.
• At transmitting : Set a transmission data.
• At receiving : A reception data is stored.
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 48 of 70
REJ09B0178-0300
Fig. 3.5.30 Structure of A/D control register
b
7b
6b
5b
4b3b
2b
1b
0
BF
u
n
c
t
i
o
n
A
t
r
e
s
e
tRW
0
1
2
3
4
5
6
7
Name
0
1
0
0
A/D control register (ADCON) [Address : 3416]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
✕
A
/
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
0
0
0
:
P
20/
A
N0
0
0
1
:
P
21/
A
N1
0
1
0
:
P
22/
A
N2
0
1
1
:
P
23/
A
N3
1
0
0
:
P
24/
A
N4
1
0
1
:
P
25/
A
N5
1
1
0
:
P
26/
A
N6(N
o
t
e)
1
1
1
:
P
27/
A
N7
(
N
o
t
e
)
Analog input pin selection bits
b
2
b
1
b
0
0
0
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
✕
✕
Note: P26/AN6, P27/AN7 can be selected in the 36-pin and 42-pin versions.
✽:
T
h
i
s
b
i
t
c
a
n
b
e
c
l
e
a
r
e
d
t
o
“
0
”
b
y
p
r
o
g
r
a
m
,
b
u
t
c
a
n
n
o
t
b
e
s
e
t
t
o
“
1
”
.
✽
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 49 of 70
REJ09B0178-0300
Fig. 3.5.32 Structure of A/D conversion register (low-order)
Fig. 3.5.31 Structure of A/D conversion register (high-order)
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
b
7b
6b
5b
4b3b
2b
1b
0
BFunction
A
t reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
A/D conversion register (high-order) (ADH) [Address : 3616]
The read-only register in which the A/D conversion’s results are
stored. ✕
✕
✕
✕
✕
✕
✕
✕
< 10-bit read>
b
7b9 b0
b8
N
o
t
h
i
n
g
i
s
a
l
l
o
c
a
t
e
d
f
o
r
t
h
e
s
e
b
i
t
s
.
T
h
e
s
e
a
r
e
w
r
i
t
e
d
i
s
a
b
l
e
d
b
i
t
s
.
W
h
e
n
t
h
e
s
e
b
i
t
s
a
r
e
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
s
a
r
e
“
0
”
.
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
b7 b6 b5 b4 b3 b2 b1 b0
BF
u
n
c
t
i
o
n
A
t reset
RW
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
A/D conversion register (low-order) (ADL) [Address : 35
16
]
T
h
e
r
e
a
d
-
o
n
l
y
r
e
g
i
s
t
e
r
i
n
w
h
i
c
h
t
h
e
A
/
D
c
o
n
v
e
r
s
i
o
n
’
s
r
e
s
u
l
t
s
a
r
e
s
t
o
r
e
d
.✕
✕
✕
✕
✕
✕
✕
✕
< 8-bit read>
b
7b8 b
7b
6b5b
4b3b
0
b
2b
9
< 10-bit read>
b
7b6 b5 b4 b3 b2 b1 b
0
b0b7
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 50 of 70
REJ09B0178-0300
Fig. 3.5.34 Structure of Watchdog timer control register
Fig. 3.5.33 Structure of MISRG
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name
0
0
0
0
MISRG [Address : 3816]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
MISRG
Oscillation stabilization time
set bit after release of the
STP instruction
0
0 : Set “0116” in timer 1, and
“FF16” in prescaler 12
automatically
1 : Not set automatically
These are reserved bits. “0”
Do not write “1” to these bits.
0
0
0
✕
✕
✕
✕
✕
✕
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction
At reset
RW
0
1
2
3
4
5
6
7
Name 1
1
1
1
1
1
0
0
Watchdog timer control register (WDTCON) [Address : 39
16
]
Watchdog timer H
(The high-order 6 bits are read-only bits.)
STP instruction disable bit 0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count
source selection bit 0 : Watchdog timer L underflow
1 : f(X
IN
)/16
✕
✕
✕
✕
✕
✕
7534 Group
APPENDIX
3.5 List of registers
Rev.3.00 Oct 23, 2006 page 51 of 70
REJ09B0178-0300
Fig. 3.5.36 Structure of CPU mode register
Fig. 3.5.35 Structure of Interrupt edge selection register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A
16
]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”. ✕
✕
INT
0
interrupt edge
selection bit (Note 1)
INT
1
interrupt edge
selection bit (Note 2)
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
Serial I/O1 or INT
1
interrupt
selection bit
Timer X or key-on wake up
interrupt selection bit
Timer 2 or serial I/O2 interrupt
selection bit
CNTR
0
or AD converter
interrupt selection bit
0 : Serial I/O1
1 : INT
1
0 : Timer X
1 : Key-on wake up
0 : Timer 2
1 : Serial I/O2
0 : CNTR
0
1 : AD converter
Notes 1: 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
2: 36-pin and 32-pin version: Not used.
This is a write disabled bit. When this bit is read out, the value is “0”.
b
7b
6b
5b
4b
3b
2b
1b
0
BFunction
A
t
r
e
s
e
tRW
0
2
3
4
5
6
7
N
a
m
e
0
0
0
1
CPU mode register (CPUM) [Address : 3B16]
N
o
t
h
i
n
g
i
s
a
l
l
o
c
a
t
e
d
f
o
r
t
h
e
s
e
b
i
t
s
.
T
h
e
s
e
a
r
e
w
r
i
t
e
d
i
s
a
b
l
e
d
b
i
t
s
.
W
h
e
n
t
h
e
s
e
b
i
t
s
a
r
e
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
s
a
r
e
“
0
”
.
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
0
0
0
0
0
:
S
i
n
g
l
e
-
c
h
i
p
m
o
d
e
0
1
:
N
o
t
a
v
a
i
l
a
b
l
e
1
0
:
N
o
t
a
v
a
i
l
a
b
l
e
1
1
:
N
o
t
a
v
a
i
l
a
b
l
e
b
1
b
0
10
P
r
o
c
e
s
s
o
r
m
o
d
e
b
i
t
s
✕
0 : 0 page
1 : 1 page
S
t
a
c
k
p
a
g
e
s
e
l
e
c
t
i
o
n
b
i
t
✕
Clock division ratio selection
bits 0 0 : φ = f(XIN)/2
(high-speedmode)
0 1 : φ = f(XIN)/8
(middle-speed mode)
1 0 : Applied from on-chip oscillator
1 1 : φ = f(XIN)
(double-speed mode)
b
7
b
6
✕
APPENDIX
7534 Group 3.5 List of registers
Rev.3.00 Oct 23, 2006 page 52 of 70
REJ09B0178-0300
Fig. 3.5.38 Structure of Interrupt control register 1
Fig. 3.5.37 Structure of Interrupt request register 1
CNTR0 or AD converter
interrupt request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C 16]
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”. ✕
UART receive/USBIN token
interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 or serial I/O2 interrupt
request bit
✽: These bits can be cleared to “0” by program, but cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
INT0 interrupt request bit
(Note 2)
Timer X or key-on wake up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
✽
✽
✽
✽
✽
Notes 1: 36-pin version and 32-pin version: INT1 interrupt does not exist.
2: 32-pin version: INT0 interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT1 interrupt
request bit (Note 1)
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
BFunction At reset RW
0
1
2
3
4
5
6
7
Name 0
0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Nothing is allocated for this bit. Do not write “1” to this bit.
When this bit is read out, the value is “0”. ✕
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 or serial I/O2 interrupt
enable bit
CNTR
0
or AD converter
interrupt enable bit
INT
0
interrupt enable bit
(Note 2)
Timer X or key-on wake up
interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
UART receive/USBIN token
interrupt enable bit
UART transmit/USBSETUP/
OUT token/Reset/Suspend/
Resume/INT
1
interrupt enable
bit (Note 1)
Notes 1: 36-pin version and 32-pin version: INT
1
interrupt does not exist.
2: 32-pin version: INT
0
interrupt does not exist.
This is a write disabled bit. When this bit is read out, the value is “0”.
7534 Group
APPENDIX
3.6 Package outline
Rev.3.00 Oct 23, 2006 page 53 of 70
REJ09B0178-0300
3.6 Package outline
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APPENDIX
7534 Group 3.6 Package outline
Rev.3.00 Oct 23, 2006 page 54 of 70
REJ09B0178-0300
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7534 Group
APPENDIX
3.7 List of instruction code
Rev.3.00 Oct 23, 2006 page 55 of 70
REJ09B0178-0300
3.7 List of instruction code
D7 – D4
D3 – D0
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0
BRK
BPL
JSR
ABS
BMI
RTI
BVC
RTS
BVS
BRA
BCC
LDY
IMM
BCS
CPY
IMM
BNE
CPX
IMM
BEQ
0001
1
ORA
IND, X
ORA
IND, Y
AND
IND, X
AND
IND, Y
EOR
IND, X
EOR
IND, Y
ADC
IND, X
ADC
IND, Y
STA
IND, X
STA
IND, Y
LDA
IND, X
LDA
IND, Y
CMP
IND, X
CMP
IND, Y
SBC
IND, X
SBC
IND, Y
0010
2
JSR
ZP, IND
CLT
JSR
SP
SET
STP
—
—
—
RRF
ZP
—
LDX
IMM
JMP
ZP, IND
WIT
—
—
—
0011
3
BBS
0, A
BBC
0, A
BBS
1, A
BBC
1, A
BBS
2, A
BBC
2, A
BBS
3, A
BBC
3, A
BBS
4, A
BBC
4, A
BBS
5, A
BBC
5, A
BBS
6, A
BBC
6, A
BBS
7, A
BBC
7, A
0100
4
—
—
BIT
ZP
—
COM
ZP
—
TST
ZP
—
STY
ZP
STY
ZP, X
LDY
ZP
LDY
ZP, X
CPY
ZP
—
CPX
ZP
—
0101
5
ORA
ZP
ORA
ZP, X
AND
ZP
AND
ZP, X
EOR
ZP
EOR
ZP, X
ADC
ZP
ADC
ZP, X
STA
ZP
STA
ZP, X
LDA
ZP
LDA
ZP, X
CMP
ZP
CMP
ZP, X
SBC
ZP
SBC
ZP, X
0110
6
ASL
ZP
ASL
ZP, X
ROL
ZP
ROL
ZP, X
LSR
ZP
LSR
ZP, X
ROR
ZP
ROR
ZP, X
STX
ZP
STX
ZP, Y
LDX
ZP
LDX
ZP, Y
DEC
ZP
DEC
ZP, X
INC
ZP
INC
ZP, X
0111
7
BBS
0, ZP
BBC
0, ZP
BBS
1, ZP
BBC
1, ZP
BBS
2, ZP
BBC
2, ZP
BBS
3, ZP
BBC
3, ZP
BBS
4, ZP
BBC
4, ZP
BBS
5, ZP
BBC
5, ZP
BBS
6, ZP
BBC
6, ZP
BBS
7, ZP
BBC
7, ZP
1000
8
PHP
CLC
PLP
SEC
PHA
CLI
PLA
SEI
DEY
TYA
TAY
CLV
INY
CLD
INX
SED
1001
9
ORA
IMM
ORA
ABS, Y
AND
IMM
AND
ABS, Y
EOR
IMM
EOR
ABS, Y
ADC
IMM
ADC
ABS, Y
—
STA
ABS, Y
LDA
IMM
LDA
ABS, Y
CMP
IMM
CMP
ABS, Y
SBC
IMM
SBC
ABS, Y
1010
A
ASL
A
DEC
A
ROL
A
INC
A
LSR
A
—
ROR
A
—
TXA
TXS
TAX
TSX
DEX
—
NOP
—
1011
B
SEB
0, A
CLB
0, A
SEB
1, A
CLB
1, A
SEB
2, A
CLB
2, A
SEB
3, A
CLB
3, A
SEB
4, A
CLB
4, A
SEB
5, A
CLB
5, A
SEB
6, A
CLB
6, A
SEB
7, A
CLB
7, A
1100
C
—
—
BIT
ABS
LDM
ZP
JMP
ABS
—
JMP
IND
—
STY
ABS
—
LDY
ABS
LDY
ABS, X
CPY
ABS
—
CPX
ABS
—
1101
D
ORA
ABS
ORA
ABS, X
AND
ABS
AND
ABS, X
EOR
ABS
EOR
ABS, X
ADC
ABS
ADC
ABS, X
STA
ABS
STA
ABS, X
LDA
ABS
LDA
ABS, X
CMP
ABS
CMP
ABS, X
SBC
ABS
SBC
ABS, X
1110
E
ASL
ABS
ASL
ABS, X
ROL
ABS
ROL
ABS, X
LSR
ABS
LSR
ABS, X
ROR
ABS
ROR
ABS, X
STX
ABS
—
LDX
ABS
LDX
ABS, Y
DEC
ABS
DEC
ABS, X
INC
ABS
INC
ABS, X
1111
F
SEB
0, ZP
CLB
0, ZP
SEB
1, ZP
CLB
1, ZP
SEB
2, ZP
CLB
2, ZP
SEB
3, ZP
CLB
3, ZP
SEB
4, ZP
CLB
4, ZP
SEB
5, ZP
CLB
5, ZP
SEB
6, ZP
CLB
6, ZP
SEB
7, ZP
CLB
7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
Addressing mode
Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP
OPn#OPn#OPn#OPn#OPn#OP n #
APPENDIX
7534 Group 3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 56 of 70
REJ09B0178-0300
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative ad-
dress. If the bit is 1, next instruction is
executed.
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative ad-
dress. If the bit is 0, next instruction is
executed.
This instruction takes a branch to the ap-
pointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
This instruction takes a branch to the ap-
pointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
ADC
(Note 1)
(Note 5)
AND
(Note 1)
ASL
BBC
(Note 4)
BBS
(Note 4)
BCC
(Note 4)
BCS
(Note 4)
BEQ
(Note 4)
BIT
BMI
(Note 4)
BNE
(Note 4)
7 0
C
←
←
0
29 2 2
0A 2 1
03
+
20i
17
+
20i
07
+
20i
06 5 2
25 3 2
3
65 3 269 2 2
4
4
2
2
13
+
20i 5
5
3
3
24
When T = 0
A ← A + M + C
When T = 1
M(X) ← M(X) + M + C
When T = 0
A ← A M
When T = 1
M(X) ← M(X) M
Ai or Mi = 0?
Ai or Mi = 1?
C = 0?
C = 1?
Z = 1?
A M
N = 1?
Z = 0?
V
V
V
2
3.8 Machine instructions
BIT, A, R BIT, ZP, R
Addressing mode
ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0
Processor status register
NVTBDI ZC
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #
7534 Group
APPENDIX
3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 57 of 70
REJ09B0178-0300
75
35
16
4
4
6
2
2
2
6D
2D
0E
2C
4
4
6
4
3
3
3
3
7D
3D
1E
5
5
7
3
3
3
79
39
5
5
3
3
61
21
6
6
2
2
90
B0
F0
2
2
2
2
2
2
71
31
6
6
2
2
N
N
N
•
•
•
•
•
M7
•
•
V
•
•
•
•
•
•
•
M6
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
•
•
•
•
•
Z
•
•
C
•
C
•
•
•
•
•
•
•
•
30
D0
2
2
2
2
Addressing mode
Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP
OPn#OPn#OPn#OPn#OPn#OP n #
APPENDIX
7534 Group 3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 58 of 70
REJ09B0178-0300
This instruction takes a branch to the ap-
pointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
This instruction branches to the appointed ad-
dress. The branch address is specified by a
relative address.
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
This instruction takes a branch to the ap-
pointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
This instruction takes a branch to the ap-
pointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
This instruction clears the designated bit i of A
or M.
This instruction clears C.
This instruction clears D.
This instruction clears I.
This instruction clears T.
This instruction clears V.
When T = 0, this instruction subtracts the con-
tents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
This instruction takes the one’s complement of
the contents of M and stores the result in M.
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
This instruction subtracts 1 from the contents
of A or M.
BPL
(Note 4)
BRA
BRK
BVC
(Note 4)
BVS
(Note 4)
CLB
CLC
CLD
CLI
CLT
CLV
CMP
(Note 3)
COM
CPX
CPY
DEC
N = 0?
PC ← PC ± offset
B ← 1
(PC) ← (PC) + 2
M(S) ← PCH
S ← S – 1
M(S) ← PCL
S ← S – 1
M(S) ← PS
S ← S – 1
I← 1
PCL ← ADL
PCH ← ADH
V = 0?
V = 1?
Ai or Mi ← 0
C ← 0
D ← 0
I ← 0
T ← 0
V ← 0
When T = 0
A – M
When T = 1
M(X) – M
__
M ← M
X – M
Y – M
A ← A – 1 or
M ← M – 1
18
D8
58
12
B8
2
2
2
2
2
1
1
1
1
1
C9
E0
C0
2
2
2
2
2
2
1A 2 1
1B
+
20i
C5
44
E4
C4
C6
3
5
3
3
5
2
2
2
2
2
1F
+
20i
21 52
00 7 1
Addressing mode
ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0
Processor status register
NVTBDI ZC
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #
7534 Group
APPENDIX
3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 59 of 70
REJ09B0178-0300
D5
D6
CD
EC
CC
CE
50
70
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
N
N
N
N
N
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
4
6
4
4
4
6
3
3
3
3
DD
DE
5
7
3
3
D9 5 3 C1 6 2 D1 6 2
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
•
•
•
•
•
•
0
•
•
•
•
C
•
C
C
•
2
2
10
80
2
4
2
2
Addressing mode
Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP
OPn#OPn#OPn#OPn#OPn#OP n #
APPENDIX
7534 Group 3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 60 of 70
REJ09B0178-0300
This instruction subtracts one from the current
contents of X.
This instruction subtracts one from the current
contents of Y.
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction adds one to the contents of A
or M.
This instruction adds one to the contents of X.
This instruction adds one to the contents of Y.
This instruction jumps to the address desig-
nated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
When T = 0, this instruction transfers the con-
tents of M to A.
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction loads the immediate value in
M.
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
DEX
DEY
EOR
(Note 1)
INC
INX
INY
JMP
JSR
LDA
(Note 2)
LDM
LDX
LDY
X ← X – 1
Y ← Y – 1
When T = 0
A ← A V
– M
When T = 1
M(X) ← M(X) V
– M
A ← A + 1 or
M ← M + 1
X ← X + 1
Y ← Y + 1
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PC
H
← M (AD
H
, AD
L
+ 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
M(S) ← PCH
S ← S – 1
M(S) ← PCL
S ← S – 1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
When T = 0
A ← M
When T = 1
M(X) ← M
M ← nn
X ← M
Y ← M
3A 21
1
1
1
1
2
2
2
2
CA
88
E8
C8
45
E6
3
5
2
2
49 22
A9
A2
A0
A5
3C
A6
A4
3
4
3
3
2
3
2
2
2
2
2
2
2
2
Addressing mode
ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0
Processor status register
NVTBDI ZC
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #
7534 Group
APPENDIX
3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 61 of 70
REJ09B0178-0300
55
F6
4
6
2
2
4D
EE
4
6
3
3
5D
FE
5
7
3
3
59 53
N
N
N
N
N
N
•
•
N
•
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
Z
•
•
Z
•
Z
Z
•
•
•
•
•
•
•
•
•
•
•
•
41 6 2 51 6 2
B5
B4
4C
20
AD
AE
AC
6C
A14
4
2
2
B6 4 2
3
6
4
4
4
3
3
3
3
3
BD
BC
5
5
B9
BE
5
5
3
3
3
3
53B2
02
4
7
2
2
62B162
22 5 2
Addressing mode
Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP
OPn#OPn#OPn#OPn#OPn#OP n #
APPENDIX
7534 Group 3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 62 of 70
REJ09B0178-0300
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
This instruction adds one to the PC but does
no otheroperation.
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
This instruction pushes the contents of PS to
the memory location designated by S and dec-
rements the contents of S by one.
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
This instruction rotates 4 bits of the M content
to the right.
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
This instruction increments S by one and
stores the contents of the memory location
designated by S in PCL. S is again
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
LSR
NOP
ORA
(Note 1)
PHA
PHP
PLA
PLP
ROL
ROR
RRF
RTI
RTS
PC ← PC + 1
When T = 0
A ← A V M
When T = 1
M(X) ← M(X) V M
S ← S – 1
M(S) ← PS
S ← S – 1
S ← S + 1
A ← M(S)
S ← S + 1
PS ← M(S)
S ← S + 1
PS ← M(S)
S ← S + 1
PCL ← M(S)
S ← S + 1
PCH ← M(S)
S ← S + 1
PCL ← M(S)
S ← S + 1
PCH ← M(S)
(PC) ← (PC) + 1
7 0
←
←
C
←
7 0
→
→
7 0
C
→
→
7 0
0
→
→
C4A 2 1
EA 2 1
09 22
46
05
5
3
2
2
2A
6A
26
66
82
48
08
68
28
40
60
3
3
4
4
6
6
1
1
1
1
1
1
2
2
1
1
5
5
8
2
2
2
Addressing mode
ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0
Processor status register
NVTBDI ZC
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #
7534 Group
APPENDIX
3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 63 of 70
REJ09B0178-0300
0
•
N
•
•
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
•
Z
•
•
Z
Z
Z
•
•
C
•
•
•
•
•
C
C
•
•
56
15
6
4
2
2
4E
0D
6
4
3
3
5E
1D
7
5
3
319 53 01 6 2 11 6 2
36
76
2E
6E
6
6
2
2
6
6
3
3
3E
7E
7
7
3
3
(Value saved in stack)
(Value saved in stack)
Addressing mode
Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP
OPn#OPn#OPn#OPn#OPn#OP n #
APPENDIX
7534 Group 3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 64 of 70
REJ09B0178-0300
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction sets the designated bit i of A
or M.
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
This instruction stores the contents of X in M.
The contents of X does not change.
This instruction stores the contents of Y in M.
The contents of Y does not change.
This instruction stores the contents of A in X.
The contents of A does not change.
This instruction stores the contents of A in Y.
The contents of A does not change.
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
This instruction transfers the contents of S in
X.
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
SBC
(Note 1)
(Note 5)
SEB
SEC
SED
SEI
SET
STA
STP
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
When T = 0
_
A ← A – M – C
When T = 1
_
M(X) ← M(X) – M – C
Ai or Mi ← 1
C ← 1
D ← 1
I ← 1
T ← 1
M ← A
M ← X
M ← Y
X ← A
Y ← A
M = 0?
X ← S
A ← X
S ← X
A ← Y
85
86
84
64
4
4
4
3
2
2
2
2
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
E9 2 2
0B
+
20i 0F
+
20i
21 52
E5 3 2
38
F8
78
32
2
2
2
2
1
1
1
1
42
AA
A8
BA
8A
9A
98
C2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
Addressing mode
ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0
Processor status register
NVTBDI ZC
OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n #OP n # OP n # OP n #
7534 Group
APPENDIX
3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 65 of 70
REJ09B0178-0300
•
•
•
•
N
N
N
N
N
•
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
335FD4ED
2
4
F5 F9 5 3 E1 6 2 F1 6 2
95
94
5
5
2
2
96 52
8D
8E
8C
5
5
5
3
3
3
9D 6 3 99 6 3 81 7 2 91 7 2
N
•
•
•
•
•
V
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
1
•
Z
•
•
•
•
•
C
•
1
•
•
•
APPENDIX
7534 Group 3.8 Machine instructions
Rev.3.00 Oct 23, 2006 page 66 of 70
REJ09B0178-0300
Addition
Subtraction
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any ad-
dressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
Zero page indirect absolute addressing mode
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Symbol Contents Symbol Contents
+
–
V
V
–
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
V
7534 Group
APPENDIX
3.9 SFR memory map
Rev.3.00 Oct 23, 2006 page 67 of 70
REJ09B0178-0300
3.9 SFR memory map
0
0
0
01
6
0
0
0
11
6
000216
000316
000416
000516
0
0
0
61
6
0
0
0
71
6
0
0
0
81
6
0
0
0
91
6
0
0
0
A1
6
000B16
000C16
000D16
000E16
0
0
0
F1
6
001016
001116
001216
001316
001416
001516
0
0
1
61
6
0
0
1
71
6
0
0
1
81
6
0
0
1
91
6
0
0
1
A1
6
0
0
1
B1
6
0
0
1
C1
6
0
0
1
D1
6
0
0
1
E1
6
0
0
1
F1
6
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
3
D
)
P
u
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
U
L
L
)
T
r
a
n
s
m
i
t
/
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
T
B
/
R
B
)
U
S
B
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
U
S
B
S
T
S
)
/
U
A
R
T
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
U
A
R
T
S
T
S
)
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
1
C
O
N
)
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
(
B
R
G
)
P
o
r
t
P
1
P
3
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
1
P
3
C
)
U
S
B
d
a
t
a
t
o
g
g
l
e
s
y
n
c
h
r
o
n
i
z
a
t
i
o
n
r
e
g
i
s
t
e
r
(
T
R
S
Y
N
C
)
U
S
B
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
d
i
s
c
r
i
m
i
n
a
t
i
o
n
r
e
g
i
s
t
e
r
1
(
U
S
B
I
R
1
)
U
S
B
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
d
i
s
c
r
i
m
i
n
a
t
i
o
n
r
e
g
i
s
t
e
r
2
(
U
S
B
I
R
2
)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer count source set register (TCSS)
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
(
A
D
L
)
P
r
e
s
c
a
l
e
r
1
2
(
P
R
E
1
2
)
T
i
m
e
r
1
(
T
1
)
T
i
m
e
r
2
(
T
2
)
Timer X mode register
(TM)
Prescaler X
(PREX)
Timer X
(TX)
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
I
O
2
C
O
N
)
S
e
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
(
S
I
O
2
)
A
/
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
)
A
/
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
(
A
D
H
)
M
I
S
R
G
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
W
D
T
C
O
N
)
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
I
N
T
E
D
G
E
)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
(
I
R
E
Q
1
)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
U
S
B
i
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
S
B
I
C
O
N
)
U
S
B
t
r
a
n
s
m
i
t
d
a
t
a
b
y
t
e
n
u
m
b
e
r
s
e
t
r
e
g
i
s
t
e
r
0
(
E
P
0
B
Y
T
E
)
U
S
B
t
r
a
n
s
m
i
t
d
a
t
a
b
y
t
e
n
u
m
b
e
r
s
e
t
r
e
g
i
s
t
e
r
1
(
E
P
1
B
Y
T
E
)
U
S
B
P
I
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
(
E
P
0
P
I
D
)
U
S
B
P
I
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
E
P
1
P
I
D
)
U
S
B
a
d
d
r
e
s
s
r
e
g
i
s
t
e
r
(
U
S
B
A
)
U
S
B
s
e
q
u
e
n
c
e
b
i
t
i
n
i
t
i
a
l
i
z
a
t
i
o
n
r
e
g
i
s
t
e
r
(
I
N
I
S
Q
1
)
U
S
B
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
S
B
C
O
N
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
APPENDIX
7534 Group 3.10 Pin configurations
Rev.3.00 Oct 23, 2006 page 68 of 70
REJ09B0178-0300
3.10 Pin configurations
Fig. 3.10.1 M37534M4-XXXFP, M37534E8FP pin configuration
(Top view)
O
u
t
l
i
n
e
:
P
R
S
P
0
0
3
6
G
A
-
A
1
0
1
2
3
4
6
7
8
9
11
1
2
1
4
1
5
1
6
5
1
3
1
7
1
8
3
6
3
5
3
4
3
3
31
3
0
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
3
2
2
7
2
9
2
8
P00
C
N
VS
S
XOUT
XI
N
VS
S
P
01
P
02
P
03
P
04
P
30(
L
E
D0)
V
c
c
VR
E
F
P
05
P
10/
RXD
/
D
-
P26/AN6
P
27/
A
N7
P
11/
TXD
/
D
+
P
12/
SC
L
K
P
13/
SD
A
T
A
P
23/
A
N3
P22/AN2
P
21/
A
N1
P
20/
A
N0
P
31(
L
E
D1)
P
37/
I
N
T0
P
24/
A
N4
P
25/
A
N5
P
06
P
07
U
S
B
VR
E
F
O
U
T
RESET
M
3
7
5
3
4
M
4
-
X
X
X
F
P
M
3
7
5
3
4
E
8
F
P
P
14/
C
N
T
R0
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
7534 Group
APPENDIX
3.10 Pin configurations
Rev.3.00 Oct 23, 2006 page 69 of 70
REJ09B0178-0300
Fig. 3.10.2 M37534M4-XXXGP, M37534E4GP pin configuration
(Top view)
Outline PLQP0032GB-A
P
0
7
P
10/
RXD
/
D
-
P
11/
TXD
/
D
+
P
12/
SC
L
K
P
13/
SD
A
T
A
P
14/
C
N
T
R
0
P
20/
A
N
0
P
21/
A
N1
3
2
3
1
3
0
29
2
8
2
7
2
6
25 P
34(
L
E
D4)
P
33(
L
E
D3)
P
32(
L
E
D2)
P
31(
L
E
D1)
P
30(
L
E
D0)
VS
S
XO
U
T
XI
N
9
10
11
12
13
14
15
16
2
8
7
6
5
3
1
4
VC
C
C
N
VS
S
R
E
S
E
T
P
22/
A
N2P
05
2
0
1
7
1
8
1
9
2
1
2
4
P
02
P
04
P
03
P
06
2
3
2
2
P
01
P
00
U
S
B
VR
E
F
O
U
T
M
3
7
5
3
4
M
4
-
X
X
X
G
P
M
3
7
5
3
4
E
4
G
P
P
23/
A
N3
P
24/
A
N4
P
25/
A
N5
VR
E
F
APPENDIX
7534 Group 3.10 Pin configurations
Rev.3.00 Oct 23, 2006 page 70 of 70
REJ09B0178-0300
Fig. 3.10.3 M37534M4-XXXSP, M37534E8SP, M37534RSS pin configuration
(Top view)
O
u
t
l
i
n
e
4
2
S
1
M
,
P
R
D
P
0
0
4
2
B
A
-
A
1
0
1
2
3
4
6
7
8
9
11
1
2
1
4
1
5
1
6
5
1
3
1
7
1
8
3
6
3
5
3
4
3
3
3
1
3
0
2
6
2
5
2
4
2
3
2
2
3
2
2
7
2
9
2
8
1
9
2
0
21
4
2
4
1
4
0
3
9
3
7
3
8
P
00
CNVSS
XO
U
T
XIN
VS
S
P
01
P02
P03
P
04
P
30(
L
E
D0)
V
c
c
VR
E
F
P
05
P
12/
SC
L
K
P
25/
A
N5
P
26/
A
N6
P
13/
SD
A
T
A
P
14/
C
N
T
R0
P
22/
A
N2
N
C
P21/AN1
P
20/
A
N0
P
31(
L
E
D1)
P23/AN3
P
24/
A
N4
P
06
P07
P
37/
I
N
T0
R
E
S
E
T
M
3
7
5
3
4
R
S
S
M
3
7
5
3
4
M
4
-
X
X
X
S
P
M
3
7
5
3
4
E
8
S
P
P
35(
L
E
D5)
P
34(
L
E
D4)
P
33(
L
E
D3)
P
32(
L
E
D2)
U
S
B
VR
E
F
O
U
T
P
10/
RXD
/
D
-
P11/TXD/D+
P
27/
A
N7
P
16
P
15
P
40
P
41P
36(
L
E
D6)
/
I
N
T1
REVISION HISTORY
Rev. Date Description
Page Summary
7534 Group User’s Manual
(1/2)
1.00 Nov 24, 2000 First edition–
1.10 Sep 15, 2001 Preface: Home page address revised.
BEFORE USING THIS MANUAL: Home page address revised.
Table 1 Function description of VSS, VCC revised.
Fig. 7 “Under development” eliminated.
“Note on stack page” added.
Fig. 17 Ports P36, P37 revised.
NOTES ON PROGRAMMING “Note on Stack Page” added.
Table 8 32P6U-A added. Name of Programming Adapter revised.
4
5
1-8
1-9
1-13
1-19
1-42
1-43
2.00
Jun. 21, 2004
Words standardized: On-chip oscillator, A/D converter
Electric Characteristic Difference Among Mask ROM and One Time PROM
Version MCUs added.
Note on Power Source Voltage added.
DATA REQUIRED FOR MASK ORDERS revised.
3.3.12 Electric Characteristic Difference Among Mask ROM and One Time
PROM Version MCUs,
3.3.13 Note on Power Source Voltage added.
32P6U-A revised.
All pages
1-42
1-43
3-26
3-53
3.00
Oct. 23, 2006
Package names “36P2R-A” → “PRSP0036GA-A” revised
Package names “32P6U-A” → “PLQP0032GB-A” revised
Package names “42P4B” → “PRDP0042BA-A” revised
“USB Spec. Rev.1.1” → “Low-Speed USB2.0 specification” revised
Clock Generating Circuit; “No external resistor is needed .... resistor exists on-
chip.” → “No external resistor is needed .... depending on conditions.)
Fig. 45; Pulled up added, NOTE added
Fig. 48; NOTE 2 added
NOTES ON PROGRAMMING; Watchdog Timer added
NOTES ON USE; USB Communication added
NOTES ON USE; Note on A/D Converter added
2.4.1 Transfer type: “Hi-Speed function: H.S.” added
2.4.5; USB Communication added
2.5.4 (3) Method to stabilize A/D Converter added
All pages
Chapter 1
40
41
42
43
Chapter 2
50
69
77
REVISION HISTORY
Rev. Date Description
Page Summary
7534 Group User’s Manual
(2/2)
3.3.3 (3) Method to stabilize A/D Converter
3.3.4 Notes on watchdog timer
3.3.15 USB Communication added
3.6 Package outline revised
Chapter 3
19
20
26
53
3.00
Oct. 23, 2006
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
7534 Group
Publication Data : Rev.1.00 Nov 24, 2000
Rev.3.00 Oct 23, 2006
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
7534 Group
REJ09B0178-0300
User’s Manual
