THC63LVD824A-B - CALIFORNIA EASTERN LABORATORIES

THC63LVD824A _Rev1.20_E

THC63LVD824A

Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA

General Description

The THC63LVD824A receiver is designed to support

Single Link transmission between Host and Flat Panel

Display up to SXGA resolutions and Dual Link trans-

mission between Host and Flat Panel Display up to

UXGA resolutions. The THC63LVD824A converts the

LVDS data streams back into 48bits of CMOS/TTL data

with falling edge or rising edge clock for convenient

with a variety of LCD panel controllers.

In Single Link, data transmit clock frequency of

112MHz, 48bits of RGB data are transmitted at an

effective rate of 784Mbps per LVDS channel. Using a

112MHz clock, the data throughput is 392Mbytes per

second.

In Dual Link, data tran smit clock frequency of 85 MHz,

48bits of RGB data are transmitted at an effective rate

of 595Mbps per LVDS channel. Using a 85MHz clock,

the data throughput is 595Mbytes per second.

Features

•Wide dot clock range: 25-17 0MHz suit ed for VGA,

SVGA, XGA, SXGA, SX GA+ and UXGA

•PLL requires No external components

•Supports Single Link up to 112MHz dot clock for

SXGA

•Supports Dual Link up to 170MHz dot clock for

UXGA

•50% output clo c k d ut y cycle

•TTL clock edge programmable

•TTL output driverbility selectable for lower EMI

•Power down mode

•Low power single 3.3V CMOS design

•100pin TQFP

•THC63LV DF84B com pati ble

•Pin compatible with THC63LVD824

Block Diagram

SERIAL TO PARALLEL

PLL

SERIAL TO PARALLEL

PLL

28

DEMUX

RA1 +/-

RB1 +/-

RC1 +/-

RD1 +/-

RCLK1 +/-

RA2 +/-

RB2 +/-

RC2 +/-

RD2 +/-

R/F

/PDWN

(25 to 112MHz)

RCLK2 +/-

(25 to 85MHz)

1st Link

8

RED1

GREEN1

BLUE1

HSYNC

VSYNC

DE

RED2

GREEN2

BLUE2

RECEIVER CLOCK OUT

(12.5 to 85MHz)

1st DATA

2nd DATA

CMOS/TTL OUTPUT

2nd Link

LVDS INPUT

THC63LVD824A _Rev1.20_E

Pin Out

LVDS GND

RA1-

RA1+

RB1-

RB1+

LVDS VCC

RC1-

RC1+

RCLK1-

RCLK1+

RD1-

RD1+

LVDS GND

RA2-

RA2+

RB2-

RB2+

LVDS VCC

RC2-

RC2+

RCLK2-

RCLK2+

RD2-

RD2+

LVDS GND

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

R15

GND

VCC

R14

R13

R12

R11

R10

GND

VCC

CLKOUT

B27

B26

B25

B24

B23

GND

VCC

B22

B21

B20

G27

GND

VCC

G26

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

PLL GND

PLL VCC

GND

/PDWN

MODE0

MODE1

GND

R/F

DRVSEL

R20

R21

R22

R23

R24

VCC

GND

R25

R26

R27

G20

G21

G22

G23

G24

G25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DE

VSYNC

HSYNC

B17

B16

GND

VCC

B15

B14

B13

B12

B11

B10

G17

G16

G15

G14

G13

GND

VCC

G12

G11

G10

R17

R16

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

THC63LVD824A _Rev1.20_E

Pin Description

Pin Name Pin # Type Description

RA1+, RA1- 78, 77 LVDS IN

The 1st Link. The 1st pixel input data when Dual Link.

RB1+, RB1- 80, 79 LVDS IN

RC1+, RC1- 83, 82 LVDS IN

RD1+, RD1- 87, 86 LVDS IN

RCLK1+, RCLK1- 85, 84 LVDS IN LVDS Cloc k Input fo r 1st Link.

RA2+, RA2- 90, 89 LVDS IN

The 2nd Link. These pins are disabled when Single Link.

RB2+, RB2- 92, 91 LVDS IN

RC2+, RC2- 95, 94 LVDS IN

RD2+, RD2- 99, 98 LVDS IN

RCLK2+, RCLK2- 97, 96 LVDS IN LVDS Clock Input fo r 2nd Link.

R17 ~ R10 52, 51, 50, 47,

46, 45, 44, 43 OUT

The 1st Pixe l Data Outputs.G17 ~ G10 62, 61, 60, 59,

58, 55, 54, 53 OUT

B17 ~ B10 72, 71, 68, 67,

66, 65, 64, 63 OUT

R27 ~ R20 19, 18, 17, 14,

13, 12, 11, 10 OUT

The 2nd Pixel Data Outputs.G27 ~ G20 29, 26, 25, 24,

23, 22, 21, 20 OUT

B27 ~ B20 39, 38, 37, 36,

35, 32, 31, 30 OUT

DE 75 OUT Data Enable Output.

VSYNC 74 OUT Vsync Output.

HSYNC 73 OUT Hsync Output.

CLKOUT 40 OUT Clock Output.

DRVSEL 9 IN

R/F 8 IN Output Clock Triggering Edge Select.

H: Rising edge, L: Falling edge.

MODE1, MODE0 6, 5 IN

/PDWN 4 IN H: Normal operation,

L: Power down (all outputs are pulled to ground)

VCC 15, 27, 33, 41,

48, 56, 69 Power Power Supply Pins for TTL outpu ts and digital circuitry.

GND 3, 7, 16, 28, 34,

42, 49, 57, 70 Ground Ground Pins for TTL outputs and digit a l ci rcuitry.

LVDS VCC 81,93 Power Power Supply Pins for LVDS inputs.

LVDS GND 76, 88, 100 Ground Ground Pins for LVDS inputs.

Output Driverbility Select.

DRVSEL clock data

H 8mA 4mA

L 4mA 2mA

Pixel Data Mode.

MODE1 MODE0 Mode

L L Dual Link (Dual-in/Dual-out)

L H Single Link(Single-in/Dual-out)

other Not Available

THC63LVD824A _Rev1.20_E

Absolute Maximum Ratings 1

Electrical Characteristics

CMOS/TTL DC Specifications VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

LVDS Receiver DC Specifications VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

PLL VCC 2 Power Power Supply Pin for PLL circuitry.

PLL GND 1 Ground Ground Pin for PLL circuitry.

Supply Voltage (VCC)-0.3V ~ +4.0V

CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V) ( ≦4.0V)

CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V) ( ≦4.0V)

LVDS Receiver Input Voltage -0.3V ~ (VCC + 0.3V) ( ≦4.0V)

Output Current -15mA ~ 15mA

Junction Temperature +125

Storage Temperature Range -55 ~ +125

Maximum Power Dissip ation @+25 1.7W

1. “Absolute Maximum Ratings” are those valued beyond whi c h the safety of the devi ce can not be guaranteed. They

are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”

specify conditions for device operation.

Symbol Parameter Conditions Min. Typ. Max. Units

VIH High Level Input Voltage 2.0 VCC V

VIL Low Level Input Voltage GND 0.8 V

VOH High Level Output Voltage IOH= -2mA, -4mA (data)

IOH= -4mA, -8mA (clock) 2.4 V

VOL Low Level Output Voltage IOL= 2mA, 4mA (data)

IOL= 4mA, 8mA (clock) 0.4 V

IINC Input Current μA

Symbol Parameter Conditions Min. Typ. Max. Units

VTH Differential Input High Threshold VIC= 1.2V 100 mV

VTL Differential Input Low Threshold VIC= 1.2V -100 mV

IINL Input Current VIN= 2.4V / 0V

VCC= 3.6V μA

Pin Name Pin # Type Description

°C

°C°C

°C

°C°C

0V VIN VCC

≤≤ 10±

°C°C

20±

THC63LVD824A _Rev1.20_E

Switching Characteristics

VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

Symbol Parameter Min. Typ. Max. Units

tRCP CLKOUT Period Dual-in / Dual-out 11.76 tRCIP 40.0 ns

Single-in / Dual-out 17.85 2tRCIP 80.0 ns

tRCH CLKOUT High Time ns

tRCL CKLOUT Low Time ns

tRS TTL Data Setup to CLKOUT 0.3tRCP-0.5 ns

tRH TTL Data Hold from CKLOUT 0.3tRCP-0.5 ns

tTLH TTL Low to High Transition Time 2.5 4.0 ns

tTHL TTL High to Low Transition Time 2.5 4.0 ns

tSK Receiver Skew

Margin CLKIN=85MHz -0.40 +0.40 ns

CLKIN=112MHz -0.25 +0.25 ns

tRIP1 Input Data Position0 -tSK 0.0 +tSK ns

tRIP0 Input Data Position1 ns

tRIP6 Input Data Position2 ns

tRIP5 Input Data Position3 ns

tRIP4 Input Data Position4 ns

tRIP3 Input Data Position5 ns

tRIP2 Input Data Position6 ns

tRPLL Phase Lock Loop Set 10.0 ms

tRCIP CLKIN Period 8.92 40.0 ns

tCK12 Skew Time between RCLK1 and

RCLK2 ns

°C°C

tRCP

2

-----------

tRCP

2

-----------

tRCIP

7

-------------t

SK

–tRCIP

7

-------------tRCIP

7

-------------t

SK

+

2tRCIP

7

-------------t

SK

–2

tRCIP

7

-------------2

tRCIP

7

-------------t

SK

+

3tRCIP

7

-------------t

SK

–3

tRCIP

7

-------------3

tRCIP

7

-------------t

SK

+

4tRCIP

7

-------------t

SK

–4

tRCIP

7

-------------4

tRCIP

7

-------------t

SK

+

5tRCIP

7

-------------t

SK

–5

tRCIP

7

-------------5

tRCIP

7

-------------t

SK

+

6tRCIP

7

-------------t

SK

–6

tRCIP

7

-------------6

tRCIP

7

-------------t

SK

+

0.3tRCIP

±

Supply Current

VCC = 3.0V ~ 3.6V, Ta = -10 ~ +70

Symbol Parameter Condition(*) Typ. Max. Units

IRCCW

Receiver Supply

Current

(Worst Case Pattern)

fCLKOUT = 85MHz MODE<1:0>=LL

CL=8pF,

Vcc=3.6V 225 mA

IRCCS Receiver Power Down

Supply Current /PDWN = L 10 μA

°C°C

THC63LVD824A _Rev1.20_E

AC Timing Diagrams

TTL Outputs

Phase Lock Loop Set Time

VCC 3.0V

2.0V

tRPLL

RCLKx+/-

/PDWN

CLKOUT

VCC/2

R/F = L

R/F = H

tRCP

tRS tRH

tRCH tRCL

CLKOUT VCC/2

VCC/2

Rxn

Gxn

Bxn

x = 1,2

n = 0~7

8pF

TTL Output

TTL Output Load

20%

80%

20%

80%

tTLH tTHL

THC63LVD824A _Rev1.20_E

Pixel Map Table for Single/Dual Link

TFT Panel Data

LSB 24Bit 18Bit

824A TTLOutputPin

1st Pixel Data

R10 -

MSB

R11

R12

R13

R14

R15

R16

R17

-

R10

R11

R12

R13

R14

R15

LSB

MSB

G11

G12

G13

G14

G15

G16

G17

-

G10

G11

G12

G13

G14

G15

G10 -

LSB

MSB

B11

B12

B13

B14

B15

B16

B17

-

B10

B11

B12

B13

B14

B15

B10 -

R10

R11

R12

R13

R14

R15

R16

R17

G11

G12

G13

G14

G15

G16

G17

G10

B11

B12

B13

B14

B15

B16

B17

B10

TFT Panel Data

LSB 24Bit 18Bit

824A TTLOutputPin

2nd Pixel Data

R20 -

MSB

R21

R22

R23

R24

R25

R26

R27

-

R20

R21

R22

R23

R24

R25

LSB

MSB

G21

G22

G23

G24

G25

G26

G27

-

G20

G21

G22

G23

G24

G25

G20 -

LSB

MSB

B21

B22

B23

B24

B25

B26

B27

-

B20

B21

B22

B23

B24

B25

B20 -

R20

R21

R22

R23

R24

R25

R26

R27

G21

G22

G23

G24

G25

G26

G27

G20

B21

B22

B23

B24

B25

B26

B27

B20

THC63LVD824A _Rev1.20_E

TFT Panel

(1280 x 1024)

#1 #2 #1280#1279

HSYNC

DE

CLKOUT

R1x/G1x/B1x

R2x/G2x/B2x

#1

#2

#3

#4

#5

#6 #8

#1279

#1280

#1277

#1278

1275

1276

#7

n = 0~7

824A TTL Data Output Timing for Single/Dual Link

Example : SXGA(1280 x 1024)

THC63LVD824A _Rev1.20_E

Vdiff = 0V

Ryx+/-

AC Timing Diagrams

LVDS Inputs

Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0 Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1

Vdiff = 0V

tRIP2

tRIP3

tRIP4

tRIP5

tRIP6

tRIP0

tRIP1

tRCIP

RCLKx+

x = 1,2

y = A,B,C,D

Vdiff = 0V

tCK12

RCLK1+

Vdiff = 0V

RCLK2+

Note:

Vdiff = (Ryx+) - (Ryx-), (RCLKx+) - (RCLKx-)

THC63LVD824A _Rev1.20_E

LVDS Data Inputs Timing Diagrams in Single Link

RA1+/- R26’ R25’ R24’ R23’ R22’ G12 R17 R16 R15 R14 R13 R12 G22’’

RB1+/- G27’ G26’ G25’ G24’ G23’ B13 B12 G17 G16 G15 G14 G13 B23’’

RC1+/- HSYNC’ B27’ B26’ B25’ B24’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’

RD1+/- B20’ G21’ G20’ R21’ R20’ x B11 B10 G11 G10 R11 R10 x’’

RCLK1+

Previous Cycle Current Cycle

(2nd pixel data) (1st pixel data)

THC63LVD824A _Rev1.20_E

LVDS Data Inputs Timing Diagrams in Dual Link

RA1+/- R16’ R15’ R14’ R13’ R12’ G12 R17 R16 R15 R14 R13 R12 G12’’

RB1+/- G17’ G16’ G15’ G14’ G13’ B13 B12 G17 G16 G15 G14 G13 B13’’

RC1+/- HSYNC’ B17’ B16’ B15’ B14’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’

RD1+/- B10’ G11’ G10’ R11’ R10’ xB11 B10 G11 G10 R11 R10 x’’

RA2+/- R26’ R25’ R24’ R23’ R22’ G22 R27 R26 R25 R24 R23 R22 G22’’

RB2+/- G27’ G26’ G25’ G24’ G23’ B23 B22 G27 G26 G25 G24 G23 B23’’

RC2+/- B27’ B26’ B25’ B24’ B27 B26 B25 B24

RD2+/- B20’ G21’ G20’ R21’ R20’ xB21 B20 G21 G20 R21 R20 x’’

RCLK1+

RCLK2+

x’’xxxx’

Previous Cycle Current Cycle

THC63LVD824A _Rev1.20_E

Note

1)Power On Sequence

Power on LVDS-Tx after THC63LVD824A. If it is not avoidable, please contact to

mspsupport@thine.co.jp (for FAE mailing list)

2)Cable Connection and Disconnection

Don't connect and disconnect the LVDS cable , when the power is supplied to the system.

3)GND Connection

Connect the each GND of the PCB which LVDS-Tx and THC63LVD824A on it. It is better for EMI reduction to place

GND cable as close to LVDS cable as possible.

4)Multi Drop Connection

Multi drop connection is not recommended .

5)Asynchronous use

Asynchronous use such as following systems are not recommended. If it is not avoidable, please contact to

mspsupport@thine.co.jp (for FAE mailing list)

THC63LVD824A

LVDS-Tx THC63LVD824A

TCLK+

TCLK-

THC63LVD824A

THC63LVD824ALVDS-Tx

LVDS-Tx

IC

CLKOUT

DATA

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

THC63LVD824A

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

IC

THC63LVD824A _Rev1.20_E

Package

76100

5026

INDEX

PIN No.1

25 51

75

0.20

0.5TYP

1.2MAX

UNITS:mm

14.0SQ TYP

16.0SQ TYP

THC63LVD824A _Rev1.20_E

Notices and Requests

1. The product specifications described in this material are subject to change without prior notice.

2. The circuit diagrams described in this material are examples of the application which may not

always apply to the customer's design. We are not responsible for possible errors and omissions

in this material. Please note if errors or omissions should be found in this material, we may not

be able to correct them immediately.

3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to

third parties the contents of this material without our prior permission is prohibited.

4. Note that if infringement of any third party's industrial ownership should occur by using this

product, we will be exempted from the responsibility unless it directly relates to the production

process or functions of the product.

5. This product is presumed to be used for general electric equipment, not for the applications

which require very high reliability (including medical equipment directly concerning people's

life, aerospace equipment, or nuclear control equipment). Also, when using this product for the

equipment concerned with the control and safety of the transportation means, the traffic signal

equipment, or various Types of safety equipment, please do it after applying appropriate

measures to the product.

6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur

with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you

are encouraged to have suff iciently redundant or error preventive design applied to the use of the

product so as not to have our product cause any social or public damage.

7. Please note that this product is not designed to be radiation-proof.

8. Customers are asked, if required, to judge by themselves if this product falls under the category

of strategic goods under the Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.

E-mail : sales@thine.co.jp