1
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
FEATURES
■LVPECL or LVDS input to 22 LVPECL outputs
■100K ECL compatible outputs
■LVDS input includes 100Ω termination
■Guaranteed AC parameters over voltage:
• > 1GHz fMAX (toggle)
• < 35ps max. ch-ch skew
■Low voltage operation: 2.5V, 3.3V
■Temperature range: –40°C to +85°C
■Output enable pin
■Available in a 64-Pin EPAD-TQFP
The SY89825U is a High Performance Bus Clock Driver
with 22 differential LVPECL output pairs. This part is
designed for use in low voltage (2.5V, 3.3V) applications
which require a large number of outputs to drive precisely
aligned, ultra low skew signals to their destination. The
input is multiplexed from either LVDS or LVPECL by the
CLK_SEL pin. The LVDS input includes a 100Ω internal
termination, thus eliminating the need for external
termination. The Output Enable (OE) is synchronous so
that the outputs will only be enabled/disabled when they
are already in the LOW state. This eliminates any chance
of generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The SY89825U features low pin-to-pin skew (35ps max.)
—performance previously unachievable in a standard
product having such a high number of outputs. The
SY89825U is available in a single space saving package
which provides a lower overall cost solution. In addition, a
single chip solution improves timing budgets by eliminating
the multiple device solution with their corresponding large
part-to-part skew.
2.5/3.3V 1:22 HIGH-PERFORMANCE,
LOW-VOL TAGE PECL BUS CLOCK DRIVER
& TRANSLATOR w/ INTERNAL TERMINATION
DESCRIPTION
Precision Edge®
SY89825U
APPLICATIONS
■High-performance PCs
■Workstations
■Parallel processor-based systems
■Other high-performance computing
■Communications
Rev.: D Amendment: /0
Issue Date:
November 2005
Precision Edge®
Precision Edge is a registered trademark of Micrel, Inc.
2
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
/Q5
VCCO
Q0
/Q0
Q1
/Q1
Q2
/Q2
Q3
/Q3
Q4
/Q4
Q5
Q6
/Q6
VCCO
VCCO
NC
NC
VCCI
LVDS_CLK
/LVDS_CLK
CLK_SEL
LVPECL_CLK
/LVPECL_CLK
GND
OE
NC
NC
/Q21
Q21
VCCO
VCCO
Q7
/Q7
Q8
/Q8
Q9
/Q9
Q10
/Q10
Q11
/Q11
Q12
/Q12
Q13
/Q13
VCCO
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Pin
EPAD-TQFP
(T op View)
/Q19
VCCO
Q14
/Q14
Q15
/Q15
Q16
/Q16
Q17
/Q17
Q18
/Q18
Q19
Q20
/Q20
VCCO
64-Pin EPAD-TQFP (H64-1)
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89825UHI H64-1 Industrial SY89825UHI Sn-Pb
SY89825UHITR(2) H64-1 Industrial SY89825UHI Sn-Pb
SY89825UHG(3) H64-1 Industrial SY89825UHG with Pb-Free
Pb-Free bar-line indicator NiPdAu
SY89825UHGTR(2,3) H64-1 Industrial SY89825UHG with Pb-Free
Pb-Free bar-line indicator NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
LOGIC SYMBOL
CLK_SEL
LVDS_CLK
/LVDS_CLK
LVPECL_CLK
/LVPECL_CLK
OE
0
1
22
22 Q0 - Q21
/Q0 - /Q21
LEN
D
Q
Pin Function
LVDS_CLK, Differential LVDS Inputs
/LVDS_CLK
(Internal 100Ω termination included)
LVPECL_CLK, Differential LVPECL Inputs.
/LVPECL_CLK
CLK_SEL Input CLK Select (LVTTL)
OE Output Enable (LVTTL)
Q0–Q21, /Q0–/Q21 Differential LVPECL Outputs.
Terminate with 50Ω to VCC-2V
GND Ground
VCCI Power Supply. Connect to
VCC on PCB. VCCI and VCCO are not
internally connected
VCCO Power Supply for Output Buffer.
Connect to VCCI on PCB. VCCI and
VCCO are not internally connected
PIN NAMES
3
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
OE(1) CLK_SEL Q0–Q21 /Q0–/Q21
0 0 LOW HIGH
0 1 LOW HIGH
1 0 LVDS_CLK /LVDS_CLK
1 1 LVPECL_CLK /LVPECL_CLK
TRUTH TABLE
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
LVDS_CLK and LVPECL_CLK signal.
Signal I/O Level
LVDS_CLK, /LVDS_CLK Input LVDS
Q0–Q21, /Q0–/Q21 Output LVPECL
LVPECL_CLK, /LVPECL_CLK Input LVPECL
CLK_SEL, OE Input LVCMOS/LVTTL
SIGNAL GROUPS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Value Unit
VCCI/V
CCO VCC Pin Potential to Ground Pin –0.5 to +4.0 V
VIN Input Voltage –0.5 to VCCI V
IOUT DC Output Current –50 mA
TLEAD Lead Temperature (soldering, 20 sec.) +260 °C
Tstore Storage Temperature –65 to +150 °C
θJA Package Thermal Resistance (Junction-to-Ambient)
With exposed pad soldered to GND – Still-Air (multi-layer PCB) 23 °C/W
– 200lfpm (multi-layer PCB) 18 °C/W
– 500lfpm (multi-layer PCB) 15 °C/W
Exposed pad
not
soldered to GND – Still-Air (multi-layer PCB) 44 °C/W
– 200lfpm (multi-layer PCB) 36 °C/W
– 500lfpm (multi-layer PCB) 30 °C/W
θJC Package Thermal Resistance 4.3 °C/W
(Junction-to-Case)
NOTE:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data book. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
4
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
DC ELECTRICAL CHARACTERISTICS
TA = –40°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VIN Input Voltage Range 0 —2.4 0 —2.4 0 —2.4 V
VID Differential Input Swing 100 ——100 ——100 ——mV
IIL Input Low Current(1) –1.25 ——–1.25 ——–1.25 ——mA
RIN LVDS Differential Input Resistance 80 100 120 80 100 120 80 100 120 Ω
(LVDS_CLK to /LVDS_CLK)
LVDS Input (VCC = 2.37V to 3.6V, GND = 0V)
TA = –40°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VCCI, Power Supply(1) 2.37 —3.6 2.37 —3.6 2.37 —3.6 V
VCCO
ICC Total Supply Current(2) —100 150 —100 150 —100 150 mA
Power Supply
TA = –40°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
VIH Input HIGH Voltage VCC – 1.165 VCC – 0.88 VCC – 1.165 VCC – 0.88 VCC – 1.165 VCC – 0.88 V
(Single ended)
VIL Input LOW Voltage VCC – 1.945 VCC – 1.625 VCC – 1.945 VCC – 1.625 VCC – 1.945 VCC – 1.625 V
VPP Minimum Input Swing(1) 600 —600 —600 —mV
LVPECL_CLK
VCMR Common Mode Range(2) –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 V
LVPECL_CLK
VOH Output HIGH Voltage(3) VCCO – 1.085 VCCO – 0.880 VCCO – 1.025 VCCO – 0.880 VCCO – 1.025 VCCO – 0.880 V
VOL Output LOW Voltage(3) VCCO – 1.830 VCCO – 1.555 VCCO – 1.810 VCCO – 1.620 VCCO – 1.810 VCCO – 1.620 V
IIH Input HIGH Current —150 —150 —150 µA
IIL Input LOW Current 0.5 —0.5 —0.5 —µA
LVPECL Input/Output (VCC = 2.37V to 3.6V, GND = 0V)
Notes:
1. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are
referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). The lower end of the
CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V – |VCMR (min)|.
3. Outputs loaded with 50Ω to VCC -2V.
Notes:
1. VCCI and VCCO must be connected together on the PCB such that they remain at the same potential. VCCI and VCCO are not internally connected on the die.
2. No load. Outputs floating.
TA = –40°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VIH Input HIGH Voltage 2.0 ——2.0 ——2.0 ——V
VIL Input LOW Voltage ——0.8 ——0.8 ——0.8 V
IIH Input HIGH Current +20 —–250 +20 —–250 +20 —–250 µA
IIL Input LOW Current ——–600 ——–600 ——–600 µA
LVCMOS/LVTTL Control Inputs (OE, CLK_SEL) (VCC = 2.37V to 3.6V, GND = 0V)
Note:
1. For IIL, both LVDS inputs are grounded.
5
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
TA = –40°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
fMAX Max Toggle Frequency(2) 1—— 1—— 1——GHz
tPD Propagation Delay ns
(Differential)(3) LVPECL IN 0.600 —1.2 0.600 0.900 1.2 0.600 —1.2
LVDS IN 0.800 —1.4 0.800 1.1 1.4 0.800 —1.4
tSKEW Within-Device Skew(4) ——35 —20 35 ——35 ps
Part-to-Part Skew(5) —100 200 —100 200 —100 200 ps
tS(OE) OE Set-Up Time(6) 1.0 ——1.0 ——1.0 ——ns
tH(OE) OE Hold Time(6) 0.5 ——0.5 ——0.5 ——ns
tJITTER Random Jitter(7) —— 1—— 1—— 1ps
RMS
Cycle-to-Cylce Jitter(8) —— 1—— 1—— 1ps
RMS
Total Jitter(9) ——10 ——10 ——10 psPP
trOutput Rise/Fall Time 300 —600 300 450 600 300 —600 ps
tf(20% – 80%)
t(switchover) Input Switchover ——1.2 ——1.2 ——1.2 ns
CLK_SEL-to-valid output
Notes:
1. Outputs loaded with 50Ω to VCC – 2V. Airflow ≥ 300lfpm.
2. fMAX is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, output swing ≥ 200mV, and all loading with 50Ω
to VCC –2V.
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
7. Random jitter is measured using K28.7 pattern, measured at ≤ fMAX.
8. Cycle-to-cycle definition: the variation of periods between adjacent cycles, Tn–Tn-1 where T is the time between rising edges of the output signal.
9. Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will d eviate by more than the
specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(1)
VCC = 2.37V to 3.6V, GND = 0V
6
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
75k
75k75k
GND
LVPECL_CLK
VCC
/LVPECL_CLK
LVPECL Input Stage
Figure 1. Simplified LVPECL & LVDS Input Stage
1.9k
1.9k1.9k
GND
VCC
V
IN
V
IN
1.9k
100Ω
LVDS Input Stage
LVDS/LVPECL INPUTS
7
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
TYPICAL CHARACTERISTICS
0
100
200
300
400
500
600
700
800
0 200 400 600 800 1000 1200
OUTPUT AMPLITUDE (mV)
FREQUENCY (MHz)
Frequency Response
vs. Output Amplitude @ 2.5V
0
100
200
300
400
500
600
700
800
0 200 400 600 800 1000 1200
OUTPUT AMPLITUDE (mV)
FREQUENCY (MHz)
Frequency Response
vs. Output Amplitude @3.3V
8
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
LVPECL TERMINATION RECOMMENDATIONS
Output Considerations
Be sure to properly terminate all outputs as shown below, or
equivalent. For AC coupled applications, be sure to include a pull
down resistor at the output of each driver. The emmiter follower
outputs requires a DC current path to GND. Unused outputs can be
left floating with minimal impact on skew and jitter.
R2
82Ω
R2
82Ω
Z
O
= 50Ω
Z
O
= 50Ω
+3.3V +3.3V
Vt = V
CC
—2
V
R1
130ΩR1
130Ω
+3.3V
Figure 1. Parallel Termination–Thevenin Equivalent
Notes:
1. For +2.5V systems:
R1 = 250Ω
R2 = 62.5Ω
Z = 50Ω
Z = 50Ω50Ω50Ω
46Ω to 49Ω
+3.3V +3.3V
“source”“destination”
Rb
Figure 2. Three-Resistor “Y–Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. Rb resistor sets the DC bias voltage equal to Vt. For +3.3V systems Rb = 46Ω to 49Ω.
4. Precision, low-cost 3-Resistor networks are available from resistor manufacturers such as Thin Film Technology (www.thinfilm.com).
9
Precision Edge®
SY89825U
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
64-PIN EPAD-TQFP (DIE UP) (H64-1)
Rev. 03
+0.05
–0.05
+0.002
–0.002
+0.006
–0.006
+0.012
–0.012
16
+0.002
–0.002
+0.15
–0.15
+0.03
–0.03
+0.05
–0.05
+0.012
–0.012
+0.05
–0.05
12.00 0.472
0.394 BSC SQ.
BSC SQ.
0.177
10.00
4.50
1.20
0.01 0.004
0.047 MAX 0.50
0.22
0.009
0.020
BSC SEE DETAIL "A"
0.177
4.50
17 32
33
48
6
48
64 0.15
1.00
0.039 0.20 0.008
67
0.004
0° MIN.
0°- 7°
0.60
0.024
1.00 0.039 REF.
DETAIL "A"
0.09
0.006
0.002
0.05
5
7
4
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
