August 8, 2012 | ADVANCED DATASHEET | V2.2 | PD97601
1
IR3473
6A Highly Integrated SupIRBuckTM
FEATURES
Input Voltage Range: 3V to 27V
Output Voltage Range: 0.5V to 12V
Continuous 6A Load Capability
Constant On-Time Control
Compensation Loop not Required
Excellent Efficiency at Very Low Output Currents
Programmable Switching Frequency and Soft Start
Thermally Compensated Over Current Protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Enable Input with Voltage Monitoring Capability
Pre-bias Start Up
Thermal Shut Down
Under/Over Voltage Fault Protection
Forced Continuous Conduction Mode Option
Very Small, Low Profile 4mm x 5mm QFN Package
BASIC APPLICATION
Figure 1: IR3473 Basic Application Circuit
DESCRIPTION
The IR3473 SupIRBuckTM is an easy-to-use, fully integrated
and highly efficient DC/DC voltage regulator. The onboard
constant on time hysteretic controller and MOSFETs make
IR3473 a space-efficient solution that delivers up to 6A of
precisely controlled output voltage.
Programmable switching frequency, soft start, and
thermally compensated over current protection allows for
a very flexible solution suitable for many different
applications and an ideal choice for battery powered
applications.
Additional features include pre-bias startup, very precise
0.5V reference, under/over voltage shutdown, thermal
protection, power good output, and enable input with
voltage monitoring capability.
APPLICATIONS
Notebook and Desktop Computers
Consumer Electronics – STB, LCD, TV, Printers
12V and 24V Distributed Power Systems
General Purpose POL DC-DC Converters
Game Consoles and Graphics Cards
EFFICIENCY
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
0.01 0.1 110
Load Current (A)
Efficiency
VIN = 12V
VIN = 8V
VIN = 19V
Figure 2: IR3473 Efficiency
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IR3473
6A Highly Integrated SupIRBuckTM
ORDERING INFORMATION
IR3473 ―
MARKING INFORMATION
Package
Tape & Reel Qty
Part Number
M
750
IR3473MTR1PBF
M
4000
IR3473MTRPBF
PIN DIAGRAM
WC
WC
o
PCBJ
o
JA
/2
/32
-
PBF – Lead Free
TR – Tape and Reel
M – Package Type
3473M
?YWW?
xxxxx
Site/Date/Marking Code
Lot Code
Pin 1 Identifier
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IR3473
6A Highly Integrated SupIRBuckTM
FUNCTIONAL BLOCK DIAGRAM
Figure 3: IR3473 Functional Block Diagram
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IR3473
6A Highly Integrated SupIRBuckTM
TYPICAL APPLICATION
TP7
TP10
EN
VCC
TP23
VOUTS
TP24
PGNDS
C26
open C27
open
VIN
C7
open C8
open
C24
open
C9
150uF C10
47uF C11
open
C1
1uF
R7
2.80K
R8
2.55K
C12
0.1uF
PGOOD
ISET
+3.3V
VOUT
VCC
+3.3V
VIN
TP6
PGNDS
TP14
+3.3V
U1
IR3473
3VCBP
8
FCCM
1
SS
6
PGOOD
3
FF 15
GND1
4
FB
5
GND 17
NC1
7
ISET
2
BOOT 14
VIN 13
VCC
10 NC2
9
PGND
11
PHASE 12
EN 16
C4
0.22uF
VCC
SW1
EN / FCCM
1
24
3
TP4
EN
TP17
PGND
C20
0.1uF
TP26
AGND
VSW
C21
1uF
TP11
PGOOD
R9
open
L1
2.2uH
R6
open
TP1
VINS
R4
15.8K
R3
200K
C13
open
C2
22uF
C16
open
+C3
68uF
TP2
VIN
TP5
PGND
C14
open
C17
open C18
open
TP16
VCC
FB
R5
10K
C15
open
R10
open
C6
open
TP18
VOLTAGE SENSE
+Vins
1
+Vdd1s
2
+Vdd2s
3
+Vout1s
4
+Vout2s
5-Vout2s 10
-Vdd2s 8
-Vout1s 9
-Vins 6
-Vdd1s 7
R1
10K
FCCM
IR3473
+3.3V
R11
20
C22
open
TP25
B
C25
1uF
VOUT
TP27
A
+3.3V
TP28
VID
TP13
SS
VSW
R12
4.99
SS
R2
10K
C19
open
Q1
open
2
1
3
PGND
VOUT
R13
open
C23
open
Figure 4: Demoboard Schematic for VOUT = 1.05V, FS = 300kHz
DEMOBOARD BILL OF MATERIALS
QTY
REFERENCE DESIGNATOR
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
3
C1, C21, C25
1.00uF
capacitor, X7R, 1.00uF, 25V, 0.1, 0603
Murata
GRM188R71E105KA12D
1
C10
47uF
capacitor, 47uF, 6.3V, 805
TDK
C2012X5R0J476M
2
C12, C20
0.100uF
capacitor, X7R, 0.100uF, 25V, 0.1, 603
TDK
C1608X7R1E104K
1
C2
22.0uF
capacitor, X5R, 22.0uF, 16V, 20%, 1206
Taiyo Yuden
EMK316BJ226ML-T
1
C3
68uF
capacitor, electrolytic, 68uF, 25V, 0.2, SMD
Panasonic
EEV-FK1E680P
1
C4
0.22uF
capacitor, X5R, 0.22uF, 10V, 0.1, 0603
TDK
C1608X5R1A224K
1
C9
150uF
capacitor, tantalum polymer, 150uF, 6.3V, 20%,
7343
Sanyo
6TPC150M
1
L1
2.2uH
inductor, ferrite, 2.2uH, 8.0A, 11.2mOhm, SMT
Cyntec
PCMB065T-2R2MS
1
R4
15.8K
resistor, thick film, 15.8K, 1/10W, 0.01, 603
KOA
RK73H1JLTD1582F
3
R1, R2, R5
10.0K
resistor, thick film, 10.0K, 1/10W, 0.01, 0603
KOA
RK73H1J1002F
1
R11
20
resistor, thick film, 20, 1/10W, 0.01, 603
KOA
RK73H1JLTD20R0F
1
R12
4.99
resistor, thick film, 4.99, 1/8W, 0.01, 603
KOA
RK73H1J4R99F
1
R3
200K
resistor, thick film, 200K, 1/10W, 0.01, 603
KOA
RK73H1JLTD2003F
1
R7
2.80K
resistor, thick film, 2.80K, 1/10W, 0.01, 603
KOA
RK73H1JLTD2801F
1
R8
2.55K
resistor, thick film, 2.55K, 1/10W, 0.01, 0603
KOA
RK73H1J2551F
1
SW1
SPST
switch, DIP, SPST, 2 position, SMT
C&K Components
SD02H0SK
1
U1
IR3473
4mm X 5mm QFN
IRF
IR3473MTRPBF
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IR3473
6A Highly Integrated SupIRBuckTM
PIN DESCRIPTIONS
PIN #
PIN NAME
I/O LEVEL
PIN DESCRIPTION
1
FCCM
3.3V
Forced Continuous Conduction Mode (CCM). Ground this pin to enable diode
emulation mode or discontinuous conduction mode (DCM). Pull this pin to 3.3V
to operate in CCM under all load conditions.
2
ISET
Connecting resistor to PHASE pin sets over current trip point.
3
PGOOD
5V
Power good open drain output – pull up with a resistor to 3.3V
4, 17
GND
Reference
Bias return and signal reference.
5
FB
3.3V
Inverting input to PWM comparator, OVP / PGOOD sense.
6
SS
3.3V
Soft start/shutdown. This pin provides user programmable soft-start function.
Connect an external capacitor from this pin to GND to set the startup time of the
output voltage. The converter can be shutdown by pulling this pin below 0.3V.
7
NC
-
-
8
3VCBP
3.3V
For internal LDO. Bypass with a 1.0µF capacitor to GND. A resistor in series with
the bypass capacitor may be required in single-ground plane designs. Refer to
Layout Recommendation for details.
9
NC
-
-
10
VCC
5V
VCC input. Gate drive supply. A minimum of 1.0µF ceramic capacitor is required.
11
PGND
Reference
Power return.
12
PHASE
VIN
Phase node (or switching node) of MOSFET half bridge.
13
VIN
VIN
Input voltage for the system.
14
BOOT
VIN + VCC
Bootstrapped gate drive supply – connect a capacitor to PHASE.
15
FF
VIN
Input voltage feed forward – sets on-time with a resistor to VIN.
16
EN
5V
Enable pin to turn on and off the device. Use two external resistors to set the
turn on threshold (see Electrical Specifications) for input voltage monitoring.
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IR3473
6A Highly Integrated SupIRBuckTM
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
VIN, FF
-0.3V to 30V
VCC, PGOOD, EN
-0.3V to 8V
BOOT
-0.3V to 38V
PHASE
-0.3V to 30V (DC), -5V (100ns)
BOOT to PHASE
-0.3V to 8V
ISET
-0.3V to 30V, 30mA
PGND to GND
-0.3V to +0.3V
All other pins
-0.3V to 3.9V
Storage Temperature Range
-65°C to 150°C
Junction Temperature Range
-40°C to 150°C
ESD Classification
JEDEC Class 1C
Moisture Sensitivity Level
JEDEC Level 2 @ 260°C (Note 2)
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IR3473
6A Highly Integrated SupIRBuckTM
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
SYMBOL
MIN
MAX
UNITS
Recommended VIN Range
VIN
3
27*
V
Recommended VCC Range
VCC
4.5
5.5
Recommended Output Voltage Range
VOUT
0.5
12
Recommended Output Current Range
IOUT
0
6
A
Recommended Switching Frequency
FS
N/A
750
kHz
Recommended Operating Junction Temperature
TJ
-40
125
°C
* PHASE pin must not exceed 30V.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over VIN = 12V, 4.5V < VCC < 5.5V, 0°C ≤ TJ ≤ 125°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Control Loop
Reference Accuracy
VREF
VFB = 0.5V
0.495
0.5
0.505
V
On-Time Accuracy
RFF = 180K, TJ = 65°C
280
300
320
ns
Min. Off Time
500
580
ns
Soft-Start Current
EN = High
8
10
12
µA
DCM Comparator Offset
Measure at VPHASE
-4.5
-2.5
0
mV
Feedback Input Current
VFB = 0.5V, TA = 25°C, Note 1
0.01
0.2
µA
Supply Current
VCC Supply Current (standby)
EN = Low, No Switching
23
µA
VCC Supply Current (dynamic)
EN = High, FS = 300kHz
6
mA
FF Shutdown Current
EN = Low, RFF = 180K
2
µA
Forced Continuous Conduction Mode (FCCM)
FCCM Start Threshold
2
V
FCCM Stop Threshold
0.6
V
Gate Drive
Deadtime
Monitor body diode
conduction on PHASE pin,
Note 1
5
30
ns
Bootstrap PFET
Forward Voltage
I(BOOT) = 10mA
300
mV
Upper MOSFET
Static Drain-to-Source On-Resistance
VCC = 5V, ID = 5A, TJ = 25°C
25
32
mΩ
Lower MOSFET
Static Drain-to-Source On-Resistance
VCC = 5V, ID = 5A, TJ = 25°C
24
33
mΩ
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IR3473
6A Highly Integrated SupIRBuckTM
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Fault Protection
ISET Pin Output Current
On the basis of 25°C
17
19
21
µA
ISET Pin Output Current
Temperature Coefficient
On the basis of 25°C, Note 1
4400
ppm/
°C
Under Voltage Threshold
Falling VFB & Monitor
PGOOD
0.37
0.4
0.43
V
Under Voltage Hysteresis
Rising VFB, Note 1
7.5
mV
Over Voltage Threshold
Rising VFB & Monitor PGOOD
0.586
0.625
0.655
V
Over Voltage Hysteresis
Falling VFB, Note 1
7.5
mV
VCC Turn-on Threshold
-40°C to 125°C
3.9
4.2
4.5
V
VCC Turn-off Threshold
3.6
3.9
4.2
V
VCC Threshold Hysteresis
300
mV
EN Rising Threshold
-40°C to 125°C
1.1
1.25
1.45
V
EN Hysteresis
400
mV
EN Input Current
EN = 3.3V
15
µA
PGOOD Pull Down Resistance
25
50
Ω
PGOOD Delay Threshold
VSS
1
V
Thermal Shutdown Threshold
Note 1
125
140
°C
Thermal Shutdown Threshold
Hysteresis
Note 1
20
°C
Note:
1. Guaranteed by design but not tested in production
2. Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2).
Products with prior date code of 1227 are qualified with MSL3 for Consumer Market.
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IR3473
6A Highly Integrated SupIRBuckTM
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified.
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
0.01 0.1 110
Load Current (A)
Efficiency
VIN = 12V
VIN = 8V
VIN = 19V
Figure 5: Efficiency vs. Load Current for VOUT = 1.05V
0
50
100
150
200
250
300
350
0 1 2 3 4 5 6
Load Current (A)
Switching Frequency (kHz)
Figure 7: Switching Frequency vs. Load Current
1.050
1.055
1.060
1.065
1.070
1.075
1.080
0 1 2 3 4 5 6
Load Current (A)
Output Voltage (V)
12VIN
8VIN
19VIN
Figure 9: Load Regulation
45%
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
0.01 0.1 110
Load Current (A)
Efficiency
VOUT = 1.05V; L = 2.2µH, 11.2mΩ
VOUT = 1.5V; L = 3.3µH, 19.9mΩ
VOUT = 3.3V; L = 4.7µH, 23mΩ
Figure 6: Efficiency vs. Load Current for VIN = 12V
0
200
400
600
800
1000
1200
1400
200 250 300 350 400 450 500 550 600 650 700 750
Switching Frequency (kHz)
RFF (kOhm)
5.0 Vout 4.5
4.0 3.5
3.0 2.5
2.0 1.5
1.0 0.5
Figure 8: RFF vs. Switching Frequency
1.050
1.055
1.060
1.065
1.070
1.075
1.080
8 9 10 11 12 13 14 15 16 17 18 19
Input Voltage (V)
Output Voltage (V)
Figure 10: Line Regulation at IOUT = 6A
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IR3473
6A Highly Integrated SupIRBuckTM
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow, unless
otherwise specified.
Figure 11: Startup
Figure 13: DCM (IOUT = 0.1A)
Figure 15: Over Current Protection
(tested by shorting VOUT to PGND)
Figure 12: Shutdown
Figure 14: CCM (IOUT = 6A)
Figure 16: Over Voltage Protection
(tested by shorting FB to VOUT)
EN
PGOOD
SS
VOUT
5V/div 5V/div 1V/div 500mV/div 5ms/div
EN
PGOOD
SS
VOUT
5V/div 5V/div 1V/div 500mV/div 500µs/div
VOUT
PHASE
iL
20mV/div 10V/div 500mA/div 5µs/div
VOUT
PHASE
iL
20mV/div 10V/div 5A/div 2µs/div
PGOOD
SS
VOUT
iL
5V/div 1V/div 500mV/div 10A/div 2ms/div
PGOOD
FB
VOUT
iL
5V/div 1V/div 500mV/div 2A/div 50µs/div
August 8, 2012 | ADVANCED DATASHEET | V2.2 | PD97601
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IR3473
6A Highly Integrated SupIRBuckTM
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no airflow, unless
otherwise specified.
Figure 17: Load Transient 0-3A
Figure 19: DCM/FCCM Transition
Figure 21: Thermal Image at VIN = 12V, IOUT = 6A
(IR3473: 64oC, Inductor: 48oC, PCB: 37oC)
Figure 18: Load Transient 3-6A
Figure 20: FCCM/DCM Transition
Figure 22: Thermal Image at VIN = 19V, IOUT = 6A
(IR3473: 67oC, Inductor: 49oC, PCB: 38oC)
VOUT
PHASE
iL
50mV/div 10V/div 2A/div 100µs/div
VOUT
PHASE
iL
50mV/div 10V/div 5A/div 100µs/div
FCCM
PHASE
VOUT
iL
5V/div 10V/div 500mV/div 5A/div 10µs/div
FCCM
PHASE
VOUT
iL
2V/div 10V/div 500mV/div 5A/div 5µs/div
August 8, 2012 | ADVANCED DATASHEET | V2.2 | PD97601
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IR3473
6A Highly Integrated SupIRBuckTM
THEORY OF OPERATION
PWM COMPARATOR
The PWM comparator initiates a SET signal (PWM pulse)
when the FB pin falls below the reference (VREF) or the
soft start (SS) voltage.
ON-TIME GENERATOR
The PWM on-time duration is programmed with an
external resistor (RFF) from the input supply (VIN) to the FF
pin. The simplified equation for RFF is shown in equation 1.
The FF pin is held to an internal reference after EN goes
HIGH. A copy of the current in RFF charges a timing
capacitor, which sets the on-time duration, as shown in
equation 2.
CONTROL LOGIC
The control logic monitors input power sources, sequences
the converter through the soft-start and protective modes,
and initiates an internal RUN signal when all conditions are
met.
VCC and 3VCBP pins are continuously monitored, and the
IR3473 will be disabled if the voltage of either pin drops
below the falling thresholds. EN_DELAY will become HIGH
when VCC and 3VCBP are in the normal operating range
and the EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current source charges
the external capacitor (CSS) on the SS pin to set the output
voltage slew rate during the soft start interval. The soft
start time (tSS) can be calculated from equation 3.
The feedback voltage tracks the SS pin until SS reaches the
0.5V reference voltage (Vref), then feedback is regulated
to Vref. CSS will continue to be charged, and when SS pin
reaches VSS (see Electrical Specification), SS_DELAY goes
HIGH. With EN_DELAY = LOW, the capacitor voltage and SS
pin is held to the FB pin voltage. A normal startup
sequence is shown in Figure 23.
PGOOD
The PGOOD pin is open drain and it needs to be externally
pulled high. High state indicates that output is in
regulation. The PGOOD logic monitors EN_DELAY,
SS_DELAY, and under/over voltage fault signals. PGOOD is
released only when EN_DELAY and SS_DELAY = HIGH and
output voltage is within the OV and UV thresholds.
PRE-BIAS STARTUP
IR3473 is able to start up into pre-charged output, which
prevents oscillation and disturbances of the output
voltage.
With constant on-time control, the output voltage is
compared with the soft start voltage (SS) or Vref,
depending on which one is lower, and will not start
switching unless the output voltage drops below the
reference. This scheme prevents discharge of a pre-biased
output voltage.
SHUTDOWN
The IR3473 will shutdown if VCC is below its UVLO limit.
The IR3473 can be shutdown by pulling the EN pin below
its lower threshold. Alternatively, the output can be
shutdown by pulling the soft start pin below 0.3V.
Figure 23: Normal Startup
(1)
F201V
RSW
OUT
FF
pFV
(2)
V201R
TIN
FF
ON pFV
(3)
A10 5.0
VC
tSS
SS
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13
IR3473
6A Highly Integrated SupIRBuckTM
UNDER/OVER VOLTAGE MONITOR
The IR3473 monitors the voltage at the FB node through a
350ns filter. If the FB voltage is below the under voltage
threshold, UV# is set to LOW holding PGOOD to be LOW. If
the FB voltage is above the over voltage threshold, OV# is
set to LOW, the shutdown signal (SD) is set to HIGH,
MOSFET gates are turned off, and PGOOD signal is pulled
low. Toggling VCC or EN will allow the next start up. Figure
24 and 25 show PGOOD status change when UV/OV is
detected. The over voltage and under voltage thresholds
can be found in the Electrical Specification section.
* typical filter delay
Figure 24: Under/Over Voltage Monitor
* typical filter delay
Figure 25: Over Voltage Protection
OVER CURRENT MONITOR
The over-current circuitry monitors the output current
during each switching cycle. The voltage across the lower
MOSFET, VPHASE, is monitored for over current and zero
crossing. The OCP circuit evaluates VPHASE for an over
current condition typically 270ns after the lower MOSFET
is gated on. This delay functions to filter out switching
noise. The minimum lower gate interval allows time to
sample VPHASE.
The over current trip point is programmed with a resistor
from the ISET pin to PHASE pin, as shown in equation 4.
When over current is detected, the MOSFET gates are tri-
state and SS voltage is pulled to 0V. This initiates a new
soft start cycle. If there is a total of four OC events, the
IR3473 will disable switching. Toggling VCC or EN will allow
the next start up.
Figure 26: Over Current Protection
UNDER VOLTAGE LOCK-OUT
The IR3473 has VCC and EN under voltage lock-out (UVLO)
protection. When either VCC or EN is below their UVLO
threshold, IR3473 is disabled. IR3473 will restart when
both VCC and EN are above their UVLO thresholds.
OVER TEMPERATURE PROTECTION
When the IR3473 exceeds its over temperature threshold,
the MOSFET gates are tri-state and PGOOD is pulled low.
Switching resumes once temperature drops below the over
temperature hysteresis level.
(4)
19 IR
ROC DSON
SET A
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IR3473
6A Highly Integrated SupIRBuckTM
GATE DRIVE LOGIC
The gate drive logic features adaptive dead time,
diode emulation, and a minimum lower gate interval.
An adaptive dead time prevents the simultaneous
conduction of the upper and lower MOSFETs. The lower
gate voltage must be below approximately 1V after PWM
goes HIGH before the upper MOSFET can be gated on.
Also, the differential voltage between the upper gate and
PHASE must be below approximately 1V after PWM goes
LOW before the lower MOSFET can be gated on.
The upper MOSFET is gated on after the adaptive delay
for PWM = HIGH and the lower MOSFET is gated on after
the adaptive delay for PWM = LOW. When FCCM = LOW,
the lower MOSFET is driven ‘off’ when the ZCROSS signal
indicates that the inductor current is about to reverse
direction. The ZCROSS comparator monitors the PHASE
voltage to determine when to turn off the lower MOSFET.
The lower MOSFET stays ‘off’ until the next PWM falling
edge. When the lower peak of the inductor current is
above zero, IR3473 operates in continuous conduction
mode. The continuous conduction mode can also be
selected for all load current levels by pulling FCCM to
HIGH.
Whenever the upper MOSFET is turned ‘off’, it stays
‘off’ for the Min Off Time denoted in the Electrical
Specifications. This minimum duration allows time to
recharge the bootstrap capacitor and allows the over
current monitor to sample the PHASE voltage.
COMPONENT SELECTION
Selection of components for the converter is an iterative
process which involves meeting the specifications and
tradeoffs between performance and cost. The following
sections will guide one through the process.
Inductor Selection
Inductor selection involves meeting the steady state
output ripple requirement, minimizing the switching loss
of the upper MOSFET, meeting transient response
specifications and minimizing the output capacitance.
The output voltage includes a DC voltage and a small AC
ripple component due to the low pass filter which has
incomplete attenuation of the switching harmonics.
Neglecting the inductance in series with the output
capacitor, the magnitude of the AC voltage ripple is
determined by the total inductor ripple current flowing
through the total equivalent series resistance (ESR) of the
output capacitor bank.
One can use equation 5 to find the required inductance.
ΔI is defined as shown in Figure 27. The main advantage
of small inductance is increased inductor current slew rate
during a load transient, which leads to a smaller output
capacitance requirement as discussed in the Output
Capacitor Selection section. The drawback of using smaller
inductances is increased switching power loss in the upper
MOSFET, which reduces the system efficiency and
increases the thermal dissipation.
Figure 27: Typical Input Current Waveform
Input Capacitor Selection
The main function of the input capacitor bank is to provide
the input ripple current and fast slew rate current during
the load current step up. The input capacitor bank must
have adequate ripple current carrying capability to handle
the total RMS current. Figure 27 shows a typical input
current. Equation 6 shows the RMS input current.
The RMS input current contains the DC load current and
the inductor ripple current. As shown in equation 5, the
inductor ripple current is unrelated to the load current.
The maximum RMS input current occurs at the maximum
output current. The maximum power dissipation in the
input capacitor equals the square of the maximum RMS
input current times the input capacitor’s total ESR.
The voltage rating of the input capacitor needs to be
greater than the maximum input voltage because of high
frequency ringing at the phase node. The typical
percentage is 25%.
(6)
I
ΔI
3
1
1FsTI
dttf
Ts
1
I
2
OUT
ON
OUT
Ts
0
2
IN_RMS
(5)
L2 VVT
ΔI OUTINON
August 8, 2012 | ADVANCED DATASHEET | V2.2 | PD97601
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IR3473
6A Highly Integrated SupIRBuckTM
Output Capacitor Selection
Selection of the output capacitor requires meeting
voltage overshoot requirements during load removal, and
meeting steady state output ripple voltage requirements.
The output capacitor is the most expensive converter
component and increases the overall system cost.
The output capacitor decoupling in the converter typically
includes the low frequency capacitor, such as Specialty
Polymer Aluminum, and mid frequency ceramic capacitors.
The first purpose of output capacitors is to provide current
when the load demand exceeds the inductor current,
as shown in Figure 28. Equation 7 shows the charge
requirement for a certain load step. The advantage
provided by the IR3473 at a load step is the reduced delay
compared to a fixed frequency control method. If the
load increases right after the PWM signal goes low, the
longest delay will be equal to the minimum lower gate
on-time as shown in the Electrical Specifications section.
The IR3473 also reduces the inductor current slew time,
the time it takes for the inductor current to reach equality
with the output current, by increasing the switching
frequency up to 1/(TON + Min Off Time). This results in
reduced recovery time.
Figure 28: Charge Requirement during Load Step
The output voltage drop, VDROP, initially depends on the
characteristic of the output capacitor. VDROP is the sum of
the equivalent series inductance (ESL) of the output
capacitor times the rate of change of the output current
and the ESR times the change of the output current.
VESR is usually much greater than VESL. The IR3473
requires a total ESR such that the ripple voltage at the
FB pin is greater than 7mV.
The second purpose of the output capacitor is to minimize
the overshoot of the output voltage when the load
decreases as shown in Figure 29. By using the law of
energy before and after the load removal, equation 8
shows the output capacitance requirement for a load
step down.
Figure 29: Typical Output Voltage Response Waveform
Boot Capacitor Selection
The boot capacitor starts the cycle fully charged to a
voltage of VB(0). Cg equals 0.58nF in IR3473. Choose a
sufficiently small ΔV such that VB(0)-ΔV exceeds the
maximum gate threshold voltage to turn on the upper
MOSFET.
Choose a boot capacitor value larger than the calculated
CBOOT in equation 9. Equation 9 is based on charge balance
at CCM operation. Usually the boot capacitor will be
discharged to a much lower voltage when the circuit is
operating in DCM mode at light load, due to much longer
lower MOSFET off time and the bias current drawn by the
IC. Boot capacitance needs to be increased if insufficient
turn-on of the upper MOSFET is observed at light load,
typically larger than 0.1µF is needed. The voltage rating of
this part needs to be larger than VB(0) plus the desired
derating voltage. It’s ESR and ESL needs to be low in order
to allow it to deliver the large current and di/dt’s which
drive MOSFETs most efficiently. In support of these
requirements a ceramic capacitor should be chosen.
IOUT ISTEP
VOUT VL
VESR
VOS
VDROP
(8)
VV IL
C 2
OUT
2
OS
2
STEP
OUT
(9) 1
ΔV
(0)V
CC B
gBOOT
t
Load
Current ISTEP
Inductor
Slew
Rate
Output
Charge
Δt
(7b)
VV IL
2
1
V1
C
(7a)t I0.5VC Q
OUTIN
2
STEP
DROP
OUT
STEP
August 8, 2012 | ADVANCED DATASHEET | V2.2 | PD97601
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IR3473
6A Highly Integrated SupIRBuckTM
DESIGN EXAMPLE
DESIGN CRITERIA
Input Voltage, VIN = 6V to 21V
Output Voltage, VOUT = 1.25V
Switching Frequency, Fs = 400kHz
Inductor Ripple Current, 2ΔI = 2A
Maximum Output Current, IOUT = 6A
Over Current Trip, IOC = 9A
Current Transient Step Size = 3A
Overshoot Allowance, VOS = VOUT + 50mV
Undershoot Allowance, VDROP = 50mV
Find RFF:
Pick a standard value 158 kΩ, 1% resistor.
Find RSET:
Pick a 11.5kΩ, 1% standard resistor.
Find a resistive voltage divider for VOUT = 1.25V:
R2 = 1.33kΩ, R1 = 1.96 kΩ, both 1% standard resistors.
Choose the soft start capacitor:
Once the soft start time has chosen, such as 1000µs to
reach to the reference voltage, a 22nF for CSS is used to
meet 1000µs.
Choose an inductor to meet the design specification:
Choose the inductor with the lowest DCR and AC power
loss as possible to increase the overall system efficiency.
For instance, choose a PCMB065T-1R5MS manufactured by
CYNTEC. The inductance of this part is 1.5µH and has 6.7mΩ
DCR. Ripple current needs to be recalculated using the chosen
inductor.
Choose an input capacitor:
A Panasonic 10µF (ECJ3YB1E106M) accommodates 6 Arms of
ripple current at 300kHz. Due to the chemistry of multilayer
ceramic capacitors, the capacitance varies over temperature
and operating voltage, both AC and DC. One 10µF capacitor is
recommended. In a practical solution, one 1µF capacitor is
required along with 10µF. The purpose of the 1µF capacitor is
to suppress the switching noise and deliver high frequency
current.
Choose an output capacitor:
To meet the undershoot and overshoot specification,
equations 7b and 8 will be used to calculate the minimum
output capacitance. As a result, 110μF will be needed for 3A
load removal. To meet the stability requirement, choose an
output capacitor with ESR larger than 9mΩ. Combine those
two requirements, one can choose a set of output capacitors
from manufactures such as SP-Cap (Specialty Polymer
Capacitor) from Panasonic or POSCAP from Sanyo. A 150μF
(4TPE150MI) from Sanyo with 18mΩ ESR will meet both
requirements.
If an all ceramic output capacitor solution is desired, the
external slope injection circuit composed of R6, C13, and C14
is required as explained in the Stability Considerations
section. In this design example, we can choose C14 = 1nF and
C13 = 100nF. To calculate the value of R6 with PCMB065T-
1R5MS as our inductor:
Pick a standard value for R6 = 2.26kΩ.
k 156
400k2011.25
RFF
HzpFVV
k4.11
91 9 24m
R
SET AA
V0.5 V
RR R
VOUT
12
2
FB
HHzAV VVV
1.5
400k221 1.25-211.25 FΔI2V VVV
LsIN
OUTINOUT
A
HzHV VVV
I2
400k1.521 1.25-211.25
2Δ
A
A
A
V
V
A5.1
6
1
3
1
1
21
1.25
6I 2
IN_RMS
knFmH
CDCR
L
24.2 1007.6 5.1
R
13
6
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IR3473
6A Highly Integrated SupIRBuckTM
STABILITY CONSIDERATIONS
Constant-on-time control is a fast, ripple based control
scheme. Unstable operation can occur if certain conditions
are not met. The system instability is usually caused by:
Switching noise coupled to FB input:
This causes the PWM comparator to trigger prematurely
after the 500ns minimum on-time for lower MOSFET.
It will result in double or multiple pulses every switching
cycle instead of the expected single pulse. Double pulsing
can causes higher output voltage ripple, but in most
application it will not affect operation. This can usually be
prevented by careful layout of the ground plane and the
FB sensing trace.
Steady state ripple on FB pin being too small:
The PWM comparator in IR3473 requires minimum
7mVp-p ripple voltage to operate stably. Not enough ripple
will result in similar double pulsing issue described above.
Solving this may require using output capacitors with
higher ESR.
ESR loop instability:
The stability criteria of constant on-time is:
If ESR is too small that this criteria is violated then sub-
harmonic oscillation will occur. This is similar to the
instability problem of peak-current-mode control with
D>0.5. Increasing ESR is the most effective way to stabilize
the system, but the tradeoff is the larger output voltage
ripple.
System with all ceramic output capacitors:
For applications with all ceramic output capacitors, the ESR
is usually too small to meet the stability criteria. In these
applications, external slope compensation is necessary to
make the loop stable. The ramp injection circuit, composed
of R6, C13, and C14, shown in Figure 4 is required.
The inductor current ripple sensed by R6 and C13 is AC
coupled to the FB pin through C14. C14 is usually chosen
between 1 to 10nF, and C13 between 10 to 100nF. R6
should then be chosen such that L/DCR = C13*R6.
LAYOUT RECOMMENDATIONS
Bypass Capacitor:
As VCC bypass capacitor, a 1µF high quality ceramic
capacitor should be placed on the same side as the IR3473
and connected to VCC and PGND pins directly. A 1µF
ceramic capacitor should be connected from 3VCBP to
GND to avoid noise coupling into controller circuits. For
single-ground designs, a resistor (R12) in the range of 5 to
10Ω in series with the 1µF capacitor as shown in Figure 4 is
recommended.
Boot Circuit:
CBOOT should be placed near the BOOT and PHASE pins to
reduce the impedance when the upper MOSFET turns on.
Power Stage:
Figure 30 shows the current paths and their directions
for the on and off periods. The on time path has low
average DC current and high AC current. Therefore, it is
recommended to place the input ceramic capacitor, upper,
and lower MOSFET in a tight loop as shown in Figure 30.
The purpose of the tight loop from the input ceramic
capacitor is to suppress the high frequency (10MHz range)
switching noise and reduce Electromagnetic Interference
(EMI). If this path has high inductance, the circuit will
cause voltage spikes and ringing, and increase the
switching loss. The off time path has low AC and high
average DC current. Therefore, it should be laid out with
a tight loop and wide trace at both ends of the inductor.
Lowering the loop resistance reduces the power loss. The
typical resistance value of 1-ounce copper thickness is
0.5mΩ per square inch.
Figure 30: Current Path of Power Stage
2
ONOUT TCESR
Q1
Q2
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IR3473
6A Highly Integrated SupIRBuckTM
PCB METAL AND COMPONENT PLACEMENT
Lead lands (the 13 IC pins) width should be equal
to nominal part lead width. The minimum lead to
lead spacing should be ≥ 0.2mm to minimize
shorting.
Lead land length should be equal to maximum
part lead length + 0.3 mm outboard extension.
The outboard extension ensures a large toe fillet
that can be easily inspected.
Pad lands (the 4 big pads) length and width
should be equal to maximum part pad length and
width. However, the minimum metal to metal
spacing should be no less than; 0.17mm for 2 oz.
Copper or no less than 0.1mm for 1 oz. Copper or
no less than 0.23mm for 3 oz. Copper.
Figure 31: Metal and Component Placement
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IR3473
6A Highly Integrated SupIRBuckTM
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IR3473
6A Highly Integrated SupIRBuckTM
SOLDER RESIST
It is recommended that the lead lands are Non
Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands
by a minimum of 0.025mm to ensure NSMD
pads.
The land pad should be Solder Mask Defined
(SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to
accommodate solder resist misalignment.
Ensure that the solder resist in between the lead
lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip
separating the lead lands from the pad land.
Figure 32: Solder Resist
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IR3473
6A Highly Integrated SupIRBuckTM
STENCIL DESIGN
The Stencil apertures for the lead lands should be
approximately 80% of the area of the lead lads.
Reducing the amount of solder deposited will
minimize the occurrences of lead shorts. If too
much solder is deposited on the center pad the
part will float and the lead lands will open.
The maximum length and width of the land pad
stencil aperture should be equal to the solder
resist opening minus an annular 0.2mm pull back
in order to decrease the risk of shorting the
center land to the lead lands when the part is
pushed into the solder paste.
Figure 33: Stencil Design
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IR3473
6A Highly Integrated SupIRBuckTM
PACKAGE INFORMATION
Figure 34: Package Dimensions
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial Market (Note2).
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
