MC14557B 1-to-64 Bit Variable Length Shift Register The MC14557B is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. The number of bits selected is equal to the sum of the subscripts of the enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be selected from the A or B data inputs with the A/B select input. This feature is useful for recirculation purposes. A Clock Enable (CE) input is provided to allow gating of the clock or negative edge clocking capability. The device can be effectively used for variable digital delay lines or simply to implement odd length shift registers. * * * * * * * http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 P SUFFIX CASE 648 1-64 Bit Programmable Length Q and Q Serial Buffered Outputs Asynchronous Master Reset All Inputs Buffered No Limit On Clock Rise and Fall Times Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or one Low-power Schottky TTL Load Over the Rated Temperature Range MC14557BCP AWLYYWW 1 16 14557B SOIC-16 DW SUFFIX CASE 751G AWLYYWW 1 16 SOEIAJ-16 F SUFFIX CASE 966 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol Value Unit -0.5 to +18.0 V -0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin 10 mA PD Power Dissipation, per Package (Note 3.) 500 mW TA Ambient Temperature Range -55 to +125 C Tstg Storage Temperature Range -65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C VDD Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/C From 65C To 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Semiconductor Components Industries, LLC, 2000 August, 2000 - Rev. 4 1 MC14557B ALYW 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC14557BCP PDIP-16 2000/Box MC14557BDW SOIC-16 47/Rail MC14557BDWR2 SOIC-16 1000/Tape & Reel MC14557BF SOEIAJ-16 See Note 1. MC14557BFEL SOEIAJ-16 See Note 1. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Publication Order Number: MC14557B/D MC14557B PIN ASSIGNMENT L2 1 16 VDD L1 2 15 L4 RESET 3 14 L8 CLOCK 4 13 L16 CE 5 12 L32 B 6 11 Q A 7 10 Q VSS 8 9 A/B SEL BLOCK DIAGRAM 3 4 5 6 7 9 2 1 15 14 13 12 RESET CLOCK CE B A A/B SELECT L1 L2 L4 L8 L16 L32 Q 10 Q 11 VDD = PIN 16 VSS = PIN 8 TRUTH TABLE Inputs Rst A/B 0 0 0 0 1 0 1 0 1 X Output Clock 1 1 X CE Q 0 0 B A B A 0 X Q is the output of the first selected shift register stage. X = Don't Care LENGTH SELECT TRUTH TABLE L32 L16 L8 L4 L2 L1 Register Length 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 Bit 2 Bits Bi 3 Bits 4 Bits 5 Bits 6 Bits 1 1 0 0 0 0 0 0 0 0 0 1 33 Bit Bits 34 Bits 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 1 61 Bits 62 Bits 63 Bi Bits 64 Bits NOTE: Length equals the sum of the binary length control subscripts plus one. http://onsemi.com 2 MC14557B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55C 25C 125C VDD Vdc Min Max Min Typ (4.) Max Min Max Unit "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 -- -- -- 1.5 3.0 4.0 -- -- -- 2.25 4.50 6.75 1.5 3.0 4.0 -- -- -- 1.5 3.0 4.0 "1" Level VIH 5.0 10 15 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 5.0 10 20 -- -- -- 0.010 0.020 0.030 5.0 10 20 -- -- -- 150 300 600 Adc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc mAdc IOH Source Sink Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT = (1.75 A/kHz) f + IDD IT = (3.50 A/kHz) f + IDD IT = (5.25 A/kHz) f + IDD 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 Adc MC14557B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25C) Characteristic Symbol Rise and Fall Time, Q or Q Output tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay, Clock or CE to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns tPLH, tPHL Propagation Delay, Reset to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 70 ns tPLH, tPHL VDD Min Typ (8.) Max 5 10 15 -- -- -- 100 50 40 200 100 80 5 10 15 -- -- -- 300 130 90 600 260 180 5 10 15 -- -- -- 300 130 95 600 260 190 Unit ns ns ns Pulse Width, Clock tWH(cl) 5 10 15 200 100 75 95 45 35 -- -- -- ns Pulse Width, Reset tWH(rst) 5 10 15 300 140 100 150 70 50 -- -- -- ns Clock Frequency (50% Duty Cycle) fcl 5 10 15 -- -- -- 3.0 7.5 13.0 1.7 5.0 6.7 MHz Setup Time, A or B to Clock or CE Worst case condition: L1 = L2 = L4 = L8 = L16 = L32 = VSS (Register Length = 1) tsu 5 10 15 700 290 145 350 130 85 -- -- -- 5 10 15 400 165 60 45 5 0 -- -- -- 5 10 15 200 100 10 - 150 - 60 - 50 -- -- -- 5 10 15 400 185 85 50 25 22 -- -- -- Best case condition: L32 = VDD, L1 through L16 = Don't Care (Any register length from 33 to 64) Hold Time, Clock or CE to A or B Best case condition: L1 = L2 = L4 = L8 = L16 = L32 = VSS (Register Length = 1) th ns Worst case condition: L32 = VDD, L1 through L16 = Don't Care (Any register length from 33 to 64) Rise and Fall Time, Clock Rise and Fall Time, Reset or CE Removal Time, Reset to Clock or CE ns tr, tf 5 10 15 -- tr, tf 5 10 15 -- -- -- -- -- -- 15 5 4 s trem 5 10 15 160 80 70 80 40 35 -- -- -- ns No Limit 7. The formulas given are for the typical characteristics only at 25C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. http://onsemi.com 4 MC14557B TIMING DIAGRAM 50% CLOCK VDD tWH(cl) VSS 1/fcl VDD 50% A INPUT th RESET 1-bit length: CE = 0 Q A/B = 1 L1 = L2 = L4 = L8 = L16 = L32 = 0 VSS trem tsu tTHL tTLH tPLH VDD 50% 90% 50% 10% tPHL http://onsemi.com 5 VSS PWR VOH tPHL VOL CE CLOCK RESET A 4 3 7 C R 32 BIT C R 16 BIT C 8 BIT C R 4 BIT R 6 12 13 14 15 L32 L16 L8 L4 C 2 BIT R C 1 BIT R C 1 BIT R 10 11 1 2 L2 L1 Q Q VDD = PIN 16 VSS = PIN 8 MC14557B A/B 9 SELECT LOGIC DIAGRAM 6 http://onsemi.com B 5 MC14557B PACKAGE DIMENSIONS PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C L S -T- SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SOIC-16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE B A D 9 1 8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. h X 45 E 0.25 16X M T A S B S 14X e L A 0.25 B B A1 H 8X M B M 16 SEATING PLANE T C http://onsemi.com 7 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 MC14557B PACKAGE DIMENSIONS SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O 16 LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.031 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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